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- removed edge trigger capabilty

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- removed xmem_wait
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git-svn-id: http://moon:8086/svn/vhdl/trunk@363 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-28 12:42:44 +00:00
parent 15651ad162
commit 62e35386a5
1 changed files with 6 additions and 49 deletions
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lib/CPUs/JCpu/src/core/cpu_pkg.vhd
+6 -49
View File
@@ -49,7 +49,7 @@ package cpu_pkg is
constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
-- Microcode ROM
constant MUCODE_ADDR_WIDTH : integer := 10;
constant MUCODE_ADDR_WIDTH : integer := 9;
-- Stack depth (uses lower half of CHIPRAM)
constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
@@ -100,7 +100,6 @@ package cpu_pkg is
type cpu_status_t is record
alu : alu_status_t;
xmem_wait : STD_LOGIC;
end record;
type ctrl_lines_t is record
@@ -134,7 +133,6 @@ package cpu_pkg is
type int_ctrl_in_t is record
enable : std_logic;
polarity : std_logic;
edge_sens : std_logic;
request : std_logic;
end record;
@@ -334,12 +332,11 @@ package body cpu_pkg is
function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
variable result : ctrl_lines_t;
variable ze, cy, xmem_wait : STD_LOGIC;
variable ze, cy : STD_LOGIC;
begin
ze := status.alu.zero;
cy := status.alu.carry;
xmem_wait := status.xmem_wait;
result := ctrl_lines_default;
if iphase = 0 then
@@ -435,10 +432,6 @@ package body cpu_pkg is
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.mem_write := '1';
result.pc_inc := '0';
end if;
when "MOVX|Ri|K " => -- [R(a)] <= kk
result.mem_access := xmem_access;
result.daddr_src_sel := reg_a;
@@ -446,10 +439,6 @@ package body cpu_pkg is
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.mem_write := '1';
result.pc_inc := '0';
end if;
when "XOUT|Ri|K " => -- [R(a)] <= kk
result.mem_access := xio_access;
result.daddr_src_sel := reg_a;
@@ -457,55 +446,33 @@ package body cpu_pkg is
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.pc_inc := '0';
result.mem_write := '1';
end if;
when "MOVX|R|Ri " => -- R(a) <= [R(b)]
result.mem_access := xmem_access;
result.reg_src_sel := xmem_src;
result.daddr_src_sel := reg_b;
if iphase = 0 then
result.mem_read := '1';
end if;
if xmem_wait = '0' then
if iphase = 1 then
elsif iphase = 1 then
result.reg_we := '1';
end if;
else
result.pc_inc := '0';
result.mem_read := '1';
end if;
when "MOVX|R|Ki " => -- R(a) <= [#addr]
result.mem_access := xmem_access;
result.reg_src_sel := xmem_src;
result.daddr_src_sel := const;
if iphase = 0 then
result.mem_read := '1';
end if;
if xmem_wait = '0' then
if iphase = 1 then
elsif iphase = 1 then
result.reg_we := '1';
end if;
else
result.pc_inc := '0';
result.mem_read := '1';
end if;
when "XIN|R|Ki " => -- R(a) <= [#addr]
result.mem_access := xio_access;
result.reg_src_sel := xmem_src;
result.daddr_src_sel := const;
if iphase = 0 then
result.mem_read := '1';
end if;
if xmem_wait = '0' then
if iphase = 1 then
elsif iphase = 1 then
result.reg_we := '1';
end if;
else
result.pc_inc := '0';
result.mem_read := '1';
end if;
when "MOVX|Ki|R " => -- [#addr] <= R(a)
result.mem_access := xmem_access;
result.daddr_src_sel := const;
@@ -513,10 +480,6 @@ package body cpu_pkg is
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.pc_inc := '0';
result.mem_write := '1';
end if;
when "XOUT|Ki|R " => -- [#addr] <= R(a)
result.mem_access := xio_access;
result.daddr_src_sel := const;
@@ -524,10 +487,6 @@ package body cpu_pkg is
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.pc_inc := '0';
result.mem_write := '1';
end if;
when "ADD|R|R " => -- R(a) <= R(a) + R(b)
result.alu_opsel := op1_add_op2;
result.alu_op1_src_sel := reg_a;
@@ -855,8 +814,6 @@ package body cpu_pkg is
status.alu.zero := addr(pos);
pos := pos + 1;
status.alu.carry := addr(pos);
pos := pos + 1;
status.xmem_wait := addr(pos);
result(i) := idecoder(opcode, iphase, status);
end loop;
@@ -867,7 +824,7 @@ package body cpu_pkg is
function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
begin
addr := status.xmem_wait & status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
addr := status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
return addr;
end get_muromaddr;