- using now 64-bit SDR interface (2 SDRAMS)
git-svn-id: http://moon:8086/svn/vhdl/trunk@72 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -27,7 +27,7 @@ USE IEEE.NUMERIC_STD.ALL;
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package sdram_config is
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constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width
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constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
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constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
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constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
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constant DDR_ROW_ADDR_WIDTH : positive := 13; --
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@@ -76,8 +76,43 @@ architecture struct of tb_sdram_ctrl_frontend_wb is
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signal dout_reg : unsigned(31 downto 0);
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signal dout_cnt : natural range 0 to 255;
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type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
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signal sd_cmd : sd_cmd_t;
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begin
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process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
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variable cmd : unsigned (2 downto 0);
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begin
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cmd := part_ras_n & part_cas_n & part_we_n;
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sd_cmd <= nop;
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if part_cs_n = '0' then
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case cmd is
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when "000" =>
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sd_cmd <= lmr;
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when "001" =>
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sd_cmd <= ar;
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when "010" =>
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sd_cmd <= pre;
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when "011" =>
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sd_cmd <= act;
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when "100" =>
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sd_cmd <= write;
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when "101" =>
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sd_cmd <= read;
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when "110" =>
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sd_cmd <= bst;
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when "111" =>
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sd_cmd <= nop;
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when others =>
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sd_cmd <= nop;
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end case;
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end if;
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end process;
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inst_clockgen : entity work.clockgen
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GENERIC MAP
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(
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@@ -144,13 +179,12 @@ inst_clockgen : entity work.clockgen
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);
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-- MICRON DDR SDRAM Simulation Model
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i_mt46v16m16_0 : entity work.mt46v16m16
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port map
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(
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dq => std_logic_vector(part_data),
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dqs => std_logic_vector(part_dqs),
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dq => std_logic_vector(part_data(15 downto 0)),
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dqs => std_logic_vector(part_dqs(1 downto 0)),
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addr => std_logic_vector(part_addr),
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ba => std_logic_vector(part_ba),
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clk => part_clk_p,
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@@ -160,7 +194,25 @@ i_mt46v16m16_0 : entity work.mt46v16m16
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ras_n => part_ras_n,
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cas_n => part_cas_n,
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we_n => part_we_n,
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dm => std_logic_vector(part_dm)
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dm => std_logic_vector(part_dm(1 downto 0))
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);
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-- MICRON DDR SDRAM Simulation Model
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i_mt46v16m16_1 : entity work.mt46v16m16
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port map
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(
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dq => std_logic_vector(part_data(31 downto 16)),
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dqs => std_logic_vector(part_dqs(3 downto 2)),
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addr => std_logic_vector(part_addr),
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ba => std_logic_vector(part_ba),
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clk => part_clk_p,
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clk_n => part_clk_n,
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cke => part_cke,
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cs_n => part_cs_n,
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ras_n => part_ras_n,
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cas_n => part_cas_n,
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we_n => part_we_n,
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dm => std_logic_vector(part_dm(3 downto 2))
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);
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CLK_GEN: process
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@@ -198,125 +250,22 @@ STIMULUS: process
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WE_O <= '1';
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DAT_O <= X"1234_0000";
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ADDR_O <= X"0000_0000";
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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for i in 0 to 8192 loop
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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end loop;
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STB_O <= '0';
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wait until rising_edge(CLK_O) and ACK_I = '1';
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wait until rising_edge(CLK_O);
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CYC_O <= '0';
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-- 8-word burst cycle
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------------------------------------------------------------
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wait for 3*CLK_PERIOD;
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------------------------------------------------------------
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-- 8-word burst cycle
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dout_rst <= '1';
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wait until rising_edge(CLK_O);
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dout_rst <= '0';
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@@ -324,27 +273,21 @@ STIMULUS: process
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STB_O <= '1';
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WE_O <= '0';
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ADDR_O <= X"0000_0000";
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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STB_O <= '0';
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for i in 0 to 31 loop
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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DAT_O <= DAT_O + 1;
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ADDR_O <= ADDR_O + 4;
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end loop;
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wait until rising_edge(CLK_O) and dout_cnt = 7;
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STB_O <= '0';
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wait until rising_edge(CLK_O) and dout_cnt = 31;
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CYC_O <= '0';
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------------------------------------------------------------
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wait for 3*CLK_PERIOD;
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------------------------------------------------------------
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wait until rising_edge(CLK_O);
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-- 1-word burst cycle
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CYC_O <= '1';
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@@ -355,10 +298,13 @@ STIMULUS: process
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DAT_O <= X"DEADBEEF";
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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STB_O <= '0';
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wait until rising_edge(CLK_O) and ACK_I = '1';
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wait until rising_edge(CLK_O);
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CYC_O <= '0';
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------------------------------------------------------------
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wait for 3*CLK_PERIOD;
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------------------------------------------------------------
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wait until rising_edge(CLK_O);
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-- 1-word burst cycle
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CYC_O <= '1';
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@@ -370,134 +316,536 @@ STIMULUS: process
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wait until rising_edge(CLK_O) and ACK_I = '1';
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CYC_O <= '0';
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-- 8-word burst cycle
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------------------------------------------------------------
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wait for 3*CLK_PERIOD;
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------------------------------------------------------------
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-- 8-word burst cycle
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dout_rst <= '1';
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wait until rising_edge(CLK_O);
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dout_rst <= '0';
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CYC_O <= '1';
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STB_O <= '1';
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WE_O <= '0';
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ADDR_O <= X"0000_0000";
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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STB_O <= '0';
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MRDY_O <= '0';
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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STB_O <= '1';
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MRDY_O <= '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
|
||||
for i in 0 to 31 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 54;
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 31;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
ADDR_O <= X"0000_0000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
ADDR_O <= X"0000_0400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
ADDR_O <= X"0000_0800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
ADDR_O <= X"0000_0C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
ADDR_O <= X"0000_1000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
ADDR_O <= X"0000_1400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
ADDR_O <= X"0000_1800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
ADDR_O <= X"0000_1C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 10*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
for k in 0 to 3 loop
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1000";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1400";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1800";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
-- wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
-- 8-word burst cycle
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_1C00";
|
||||
|
||||
for i in 0 to 7 loop
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
end loop;
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
Reference in New Issue
Block a user