- deleted
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@266 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -1,17 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
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||||
## Compile Post-Map Model
|
||||
vcom -explicit -93 "../syn/ise9/netgen/par/mips_top_syn_timesim.vhd"
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||||
vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/par/mips_top_syn_timesim.sdf" -lib work mips_top_syn
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_instr.vhd"
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||||
vcom -explicit -93 "../src/irom_hello.vhd"
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||||
vcom -explicit -93 "../src/tb_mips_top_syn.vhd"
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vsim -t 1ps -lib work tb_mips_top_syn
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do {tb_mips_top_syn.wdo}
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view wave
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#add wave *
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||||
view structure
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||||
view signals
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run 2400ns
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||||
@@ -1,31 +0,0 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_mips_top_syn/rst
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||||
add wave -noupdate -format Logic /tb_mips_top_syn/clk
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||||
add wave -noupdate -format Logic /tb_mips_top_syn/ce
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_addr
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_dout
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_addr
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||||
add wave -noupdate -format Logic /tb_mips_top_syn/dmem_we
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||||
add wave -noupdate -format Logic /tb_mips_top_syn/dmem_re
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_id_stage_boff
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_stage_ex_inst_alu_sum_res
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||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top_syn/sram
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||||
TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {118199 ps} 0}
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configure wave -namecolwidth 188
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||||
configure wave -valuecolwidth 100
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configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
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configure wave -datasetprefix 0
|
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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||||
configure wave -gridoffset 0
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configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
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configure wave -timeline 1
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||||
update
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WaveRestoreZoom {0 ps} {2520 ns}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,320 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
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||||
--------------------------------------------------------------------------
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||||
|
||||
LIBRARY ieee;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
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||||
);
|
||||
Port
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||||
(
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||||
clk : in STD_LOGIC;
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||||
addr : in unsigned(addr_width-1 downto 0);
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||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
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||||
END rom;
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||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
X"3C1D7FFF", -- 00000000
|
||||
X"0C100014", -- 00000004
|
||||
X"37BDEFFC", -- 00000008
|
||||
X"24080002", -- 0000000C
|
||||
X"0107102A", -- 00000010
|
||||
X"ACC40000", -- 00000014
|
||||
X"1040000B", -- 00000018
|
||||
X"ACC50004", -- 0000001C
|
||||
X"24C60008", -- 00000020
|
||||
X"24E8FFFE", -- 00000024
|
||||
X"8CC2FFF8", -- 00000028
|
||||
X"8CC3FFFC", -- 0000002C
|
||||
X"2508FFFF", -- 00000030
|
||||
X"00431021", -- 00000034
|
||||
X"ACC20000", -- 00000038
|
||||
X"1500FFFA", -- 0000003C
|
||||
X"24C60004", -- 00000040
|
||||
X"00E04021", -- 00000044
|
||||
X"03E00008", -- 00000048
|
||||
X"01001021", -- 0000004C
|
||||
X"27BDFF78", -- 00000050
|
||||
X"3C021003", -- 00000054
|
||||
X"3C030001", -- 00000058
|
||||
X"AFB60078", -- 0000005C
|
||||
X"3456FFFC", -- 00000060
|
||||
X"3C02AAAA", -- 00000064
|
||||
X"AFB7007C", -- 00000068
|
||||
X"AFB50074", -- 0000006C
|
||||
X"AFB40070", -- 00000070
|
||||
X"AFB20068", -- 00000074
|
||||
X"AFB00060", -- 00000078
|
||||
X"AFBF0080", -- 0000007C
|
||||
X"AFB3006C", -- 00000080
|
||||
X"AFB10064", -- 00000084
|
||||
X"AEC00000", -- 00000088
|
||||
X"3450AAAA", -- 0000008C
|
||||
X"347786A0", -- 00000090
|
||||
X"27B20010", -- 00000094
|
||||
X"24150014", -- 00000098
|
||||
X"3474869F", -- 0000009C
|
||||
X"00009821", -- 000000A0
|
||||
X"00002021", -- 000000A4
|
||||
X"02401021", -- 000000A8
|
||||
X"24060013", -- 000000AC
|
||||
X"24C6FFFF", -- 000000B0
|
||||
X"AC500000", -- 000000B4
|
||||
X"04C1FFFD", -- 000000B8
|
||||
X"24420004", -- 000000BC
|
||||
X"02041026", -- 000000C0
|
||||
X"24910001", -- 000000C4
|
||||
X"24420001", -- 000000C8
|
||||
X"02202821", -- 000000CC
|
||||
X"27A60010", -- 000000D0
|
||||
X"24070014", -- 000000D4
|
||||
X"0C100003", -- 000000D8
|
||||
X"00028040", -- 000000DC
|
||||
X"24070002", -- 000000E0
|
||||
X"26450008", -- 000000E4
|
||||
X"0810003E", -- 000000E8
|
||||
X"24060011", -- 000000EC
|
||||
X"04C0000A", -- 000000F0
|
||||
X"00000000", -- 000000F4
|
||||
X"8CA20000", -- 000000F8
|
||||
X"8CA3FFFC", -- 000000FC
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||||
X"8CA4FFF8", -- 00000100
|
||||
X"00431023", -- 00000104
|
||||
X"24C6FFFF", -- 00000108
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||||
X"1482FFF8", -- 0000010C
|
||||
X"24A50004", -- 00000110
|
||||
X"04C1FFF8", -- 00000114
|
||||
X"24E70001", -- 00000118
|
||||
X"10F5000C", -- 0000011C
|
||||
X"00000000", -- 00000120
|
||||
X"0291102A", -- 00000124
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||||
X"1040FFDF", -- 00000128
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||||
X"02202021", -- 0000012C
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||||
X"1677FFDB", -- 00000130
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||||
X"00009821", -- 00000134
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||||
X"8EC20000", -- 00000138
|
||||
X"00000000", -- 0000013C
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||||
X"24420001", -- 00000140
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||||
X"AEC20000", -- 00000144
|
||||
X"0810002A", -- 00000148
|
||||
X"00002021", -- 0000014C
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||||
X"08100049", -- 00000150
|
||||
X"26730001", -- 00000154
|
||||
X"00000000", -- 00000158
|
||||
X"00000000", -- 0000015C
|
||||
X"00000000", -- 00000160
|
||||
X"00000000", -- 00000164
|
||||
X"00000000", -- 00000168
|
||||
X"00000000", -- 0000016C
|
||||
X"00000000", -- 00000170
|
||||
X"00000000", -- 00000174
|
||||
X"00000000", -- 00000178
|
||||
X"00000000", -- 0000017C
|
||||
X"00000000", -- 00000180
|
||||
X"00000000", -- 00000184
|
||||
X"00000000", -- 00000188
|
||||
X"00000000", -- 0000018C
|
||||
X"00000000", -- 00000190
|
||||
X"00000000", -- 00000194
|
||||
X"00000000", -- 00000198
|
||||
X"00000000", -- 0000019C
|
||||
X"00000000", -- 000001A0
|
||||
X"00000000", -- 000001A4
|
||||
X"00000000", -- 000001A8
|
||||
X"00000000", -- 000001AC
|
||||
X"00000000", -- 000001B0
|
||||
X"00000000", -- 000001B4
|
||||
X"00000000", -- 000001B8
|
||||
X"00000000", -- 000001BC
|
||||
X"00000000", -- 000001C0
|
||||
X"00000000", -- 000001C4
|
||||
X"00000000", -- 000001C8
|
||||
X"00000000", -- 000001CC
|
||||
X"00000000", -- 000001D0
|
||||
X"00000000", -- 000001D4
|
||||
X"00000000", -- 000001D8
|
||||
X"00000000", -- 000001DC
|
||||
X"00000000", -- 000001E0
|
||||
X"00000000", -- 000001E4
|
||||
X"00000000", -- 000001E8
|
||||
X"00000000", -- 000001EC
|
||||
X"00000000", -- 000001F0
|
||||
X"00000000", -- 000001F4
|
||||
X"00000000", -- 000001F8
|
||||
X"00000000", -- 000001FC
|
||||
X"00000000", -- 00000200
|
||||
X"00000000", -- 00000204
|
||||
X"00000000", -- 00000208
|
||||
X"00000000", -- 0000020C
|
||||
X"00000000", -- 00000210
|
||||
X"00000000", -- 00000214
|
||||
X"00000000", -- 00000218
|
||||
X"00000000", -- 0000021C
|
||||
X"00000000", -- 00000220
|
||||
X"00000000", -- 00000224
|
||||
X"00000000", -- 00000228
|
||||
X"00000000", -- 0000022C
|
||||
X"00000000", -- 00000230
|
||||
X"00000000", -- 00000234
|
||||
X"00000000", -- 00000238
|
||||
X"00000000", -- 0000023C
|
||||
X"00000000", -- 00000240
|
||||
X"00000000", -- 00000244
|
||||
X"00000000", -- 00000248
|
||||
X"00000000", -- 0000024C
|
||||
X"00000000", -- 00000250
|
||||
X"00000000", -- 00000254
|
||||
X"00000000", -- 00000258
|
||||
X"00000000", -- 0000025C
|
||||
X"00000000", -- 00000260
|
||||
X"00000000", -- 00000264
|
||||
X"00000000", -- 00000268
|
||||
X"00000000", -- 0000026C
|
||||
X"00000000", -- 00000270
|
||||
X"00000000", -- 00000274
|
||||
X"00000000", -- 00000278
|
||||
X"00000000", -- 0000027C
|
||||
X"00000000", -- 00000280
|
||||
X"00000000", -- 00000284
|
||||
X"00000000", -- 00000288
|
||||
X"00000000", -- 0000028C
|
||||
X"00000000", -- 00000290
|
||||
X"00000000", -- 00000294
|
||||
X"00000000", -- 00000298
|
||||
X"00000000", -- 0000029C
|
||||
X"00000000", -- 000002A0
|
||||
X"00000000", -- 000002A4
|
||||
X"00000000", -- 000002A8
|
||||
X"00000000", -- 000002AC
|
||||
X"00000000", -- 000002B0
|
||||
X"00000000", -- 000002B4
|
||||
X"00000000", -- 000002B8
|
||||
X"00000000", -- 000002BC
|
||||
X"00000000", -- 000002C0
|
||||
X"00000000", -- 000002C4
|
||||
X"00000000", -- 000002C8
|
||||
X"00000000", -- 000002CC
|
||||
X"00000000", -- 000002D0
|
||||
X"00000000", -- 000002D4
|
||||
X"00000000", -- 000002D8
|
||||
X"00000000", -- 000002DC
|
||||
X"00000000", -- 000002E0
|
||||
X"00000000", -- 000002E4
|
||||
X"00000000", -- 000002E8
|
||||
X"00000000", -- 000002EC
|
||||
X"00000000", -- 000002F0
|
||||
X"00000000", -- 000002F4
|
||||
X"00000000", -- 000002F8
|
||||
X"00000000", -- 000002FC
|
||||
X"00000000", -- 00000300
|
||||
X"00000000", -- 00000304
|
||||
X"00000000", -- 00000308
|
||||
X"00000000", -- 0000030C
|
||||
X"00000000", -- 00000310
|
||||
X"00000000", -- 00000314
|
||||
X"00000000", -- 00000318
|
||||
X"00000000", -- 0000031C
|
||||
X"00000000", -- 00000320
|
||||
X"00000000", -- 00000324
|
||||
X"00000000", -- 00000328
|
||||
X"00000000", -- 0000032C
|
||||
X"00000000", -- 00000330
|
||||
X"00000000", -- 00000334
|
||||
X"00000000", -- 00000338
|
||||
X"00000000", -- 0000033C
|
||||
X"00000000", -- 00000340
|
||||
X"00000000", -- 00000344
|
||||
X"00000000", -- 00000348
|
||||
X"00000000", -- 0000034C
|
||||
X"00000000", -- 00000350
|
||||
X"00000000", -- 00000354
|
||||
X"00000000", -- 00000358
|
||||
X"00000000", -- 0000035C
|
||||
X"00000000", -- 00000360
|
||||
X"00000000", -- 00000364
|
||||
X"00000000", -- 00000368
|
||||
X"00000000", -- 0000036C
|
||||
X"00000000", -- 00000370
|
||||
X"00000000", -- 00000374
|
||||
X"00000000", -- 00000378
|
||||
X"00000000", -- 0000037C
|
||||
X"00000000", -- 00000380
|
||||
X"00000000", -- 00000384
|
||||
X"00000000", -- 00000388
|
||||
X"00000000", -- 0000038C
|
||||
X"00000000", -- 00000390
|
||||
X"00000000", -- 00000394
|
||||
X"00000000", -- 00000398
|
||||
X"00000000", -- 0000039C
|
||||
X"00000000", -- 000003A0
|
||||
X"00000000", -- 000003A4
|
||||
X"00000000", -- 000003A8
|
||||
X"00000000", -- 000003AC
|
||||
X"00000000", -- 000003B0
|
||||
X"00000000", -- 000003B4
|
||||
X"00000000", -- 000003B8
|
||||
X"00000000", -- 000003BC
|
||||
X"00000000", -- 000003C0
|
||||
X"00000000", -- 000003C4
|
||||
X"00000000", -- 000003C8
|
||||
X"00000000", -- 000003CC
|
||||
X"00000000", -- 000003D0
|
||||
X"00000000", -- 000003D4
|
||||
X"00000000", -- 000003D8
|
||||
X"00000000", -- 000003DC
|
||||
X"00000000", -- 000003E0
|
||||
X"00000000", -- 000003E4
|
||||
X"00000000", -- 000003E8
|
||||
X"00000000", -- 000003EC
|
||||
X"00000000", -- 000003F0
|
||||
X"00000000", -- 000003F4
|
||||
X"00000000", -- 000003F8
|
||||
X"00000000" -- 000003FC
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dout <= word_array(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end itest;
|
||||
@@ -1,121 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
X"08100001", -- [0x00400000] j 0x00400004 [main]
|
||||
X"3c011234", -- [0x00400004] lui $1, 4660
|
||||
X"34215678", -- [0x00400008] ori $1, $1, 22136
|
||||
X"3021f00f", -- [0x0040000c] andi $1, $1, -4081
|
||||
X"2021affc", -- [0x00400010] addi $1, $1, -20484
|
||||
X"2021ffff", -- [0x00400014] addi $1, $1, -1
|
||||
X"1c20fffe", -- [0x00400018] bgtz $1 -8 [loop-0x00400018]
|
||||
X"3c020000", -- [0x0040001c] lui $2, 0
|
||||
X"34420001", -- [0x00400020] ori $2, $2, 1
|
||||
X"3c010000", -- [0x00400024] lui $1, 0
|
||||
X"34210004", -- [0x00400028] ori $1, $1, 4
|
||||
X"00220822", -- [0x0040002c] sub $1, $1, $2
|
||||
X"1c20fffe", -- [0x00400030] bgtz $1 -8 [loop2-0x00400030]
|
||||
X"3c1f0040", -- [0x00400034] lui $31, 64
|
||||
X"03e00008", -- [0x00400038] jr $31
|
||||
X"00000000", -- [0x0040003c] nop
|
||||
X"00000000", -- [0x00400040] nop
|
||||
X"00000000", -- [0x00400044] nop
|
||||
X"00000000", -- [0x00400048] nop
|
||||
X"00000000", -- [0x0040004c] nop
|
||||
X"00000000", -- [0x00400050] nop
|
||||
X"00000000", -- [0x00400054] nop
|
||||
X"00000000", -- [0x00400058] nop
|
||||
X"00000000", -- [0x0040005c] nop
|
||||
X"00000000", -- [0x00400060] nop
|
||||
X"00000000", -- [0x00400064] nop
|
||||
X"00000000", -- [0x00400068] nop
|
||||
X"00000000", -- [0x0040006c] nop
|
||||
X"00000000", -- [0x00400070] nop
|
||||
X"00000000", -- [0x00400074] nop
|
||||
X"00000000", -- [0x00400078] nop
|
||||
X"00000000", -- [0x0040007c] nop
|
||||
X"00000000", -- [0x00400080] nop
|
||||
X"00000000", -- [0x00400084] nop
|
||||
X"00000000", -- [0x00400088] nop
|
||||
X"00000000", -- [0x0040008c] nop
|
||||
X"00000000", -- [0x00400090] nop
|
||||
X"00000000", -- [0x00400094] nop
|
||||
X"00000000", -- [0x00400098] nop
|
||||
X"00000000", -- [0x0040009c] nop
|
||||
X"00000000", -- [0x004000a0] nop
|
||||
X"00000000", -- [0x004000a4] nop
|
||||
X"00000000", -- [0x004000a8] nop
|
||||
X"00000000", -- [0x004000ac] nop
|
||||
X"00000000", -- [0x004000b0] nop
|
||||
X"00000000", -- [0x004000b4] nop
|
||||
X"00000000", -- [0x004000b8] nop
|
||||
X"00000000", -- [0x004000bc] nop
|
||||
X"00000000", -- [0x004000c0] nop
|
||||
X"00000000", -- [0x004000c4] nop
|
||||
X"00000000", -- [0x004000c8] nop
|
||||
X"00000000", -- [0x004000cc] nop
|
||||
X"00000000", -- [0x004000d0] nop
|
||||
X"00000000", -- [0x004000d4] nop
|
||||
X"00000000", -- [0x004000d8] nop
|
||||
X"00000000", -- [0x004000dc] nop
|
||||
X"00000000", -- [0x004000e0] nop
|
||||
X"00000000", -- [0x004000e4] nop
|
||||
X"00000000", -- [0x004000e8] nop
|
||||
X"00000000", -- [0x004000ec] nop
|
||||
X"00000000", -- [0x004000f0] nop
|
||||
X"00000000", -- [0x004000f4] nop
|
||||
X"00000000", -- [0x004000f8] nop
|
||||
X"00000000" -- [0x004000fc] nop
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,73 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
X"08100001", -- j 0x00400004 [main] ; 5: j main
|
||||
X"3c011234", -- lui $1, 4660 ; 7: lui $1, 0x1234
|
||||
X"34215678", -- ori $1, $1, 22136 ; 8: ori $1, $1, 0x5678
|
||||
X"3c035555", -- lui $3, 21845 ; 9: lui $3, 0x5555
|
||||
X"3463aaaa", -- ori $3, $3, -21846 ; 10: ori $3, $3, 0xAAAA
|
||||
X"3c021000", -- lui $2, 4096 ; 11: lui $2, 0x1000
|
||||
X"ac410000", -- sw $1, 0($2) ; 12: sw $1, 0($2)
|
||||
X"ac430004", -- sw $3, 4($2) ; 13: sw $3, 4($2)
|
||||
X"00000000", -- nop ; 14: sll $0, $0, 0
|
||||
X"ac400000", -- sw $0, 0($2) ; 15: sw $0, 0($2)
|
||||
X"ac400004", -- sw $0, 4($2) ; 16: sw $0, 4($2)
|
||||
X"8c410000", -- lw $1, 0($2) ; 17: lw $1, 0($2)
|
||||
X"8c430004", -- lw $3, 4($2) ; 18: lw $3, 4($2)
|
||||
X"00000000", -- nop ; 19: sll $0, $0, 0
|
||||
X"00000000", -- nop ; 20: sll $0, $0, 0
|
||||
X"08100001" -- j 0x00400004 [main] ; 21: j main
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,122 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
|
||||
X"08100001", -- [0x00400000] j 0x00400004 [main]
|
||||
X"3c011234", -- [0x00400004] lui $1, 4660
|
||||
X"34215a5a", -- [0x00400008] ori $1, $1, 23130
|
||||
X"00010840", -- [0x0040000c] sll $1, $1, 1
|
||||
X"00010900", -- [0x00400010] sll $1, $1, 4
|
||||
X"00010880", -- [0x00400014] sll $1, $1, 2
|
||||
X"00010840", -- [0x00400018] sll $1, $1, 1
|
||||
X"00010a00", -- [0x0040001c] sll $1, $1, 8
|
||||
X"00010882", -- [0x00400020] srl $1, $1, 2
|
||||
X"00010942", -- [0x00400024] srl $1, $1, 5
|
||||
X"00010842", -- [0x00400028] srl $1, $1, 1
|
||||
X"00010a02", -- [0x0040002c] srl $1, $1, 8
|
||||
X"3821ffff", -- [0x00400030] xori $1, $1, -1
|
||||
X"3c1f0040", -- [0x00400034] lui $31, 64
|
||||
X"03e00008", -- [0x00400038] jr $31
|
||||
X"003f0826", -- [0x0040003c] xor $1, $1, $31
|
||||
X"00000000", -- [0x00400040] nop
|
||||
X"00000000", -- [0x00400044] nop
|
||||
X"00000000", -- [0x00400048] nop
|
||||
X"00000000", -- [0x0040004c] nop
|
||||
X"00000000", -- [0x00400050] nop
|
||||
X"00000000", -- [0x00400054] nop
|
||||
X"00000000", -- [0x00400058] nop
|
||||
X"00000000", -- [0x0040005c] nop
|
||||
X"00000000", -- [0x00400060] nop
|
||||
X"00000000", -- [0x00400064] nop
|
||||
X"00000000", -- [0x00400068] nop
|
||||
X"00000000", -- [0x0040006c] nop
|
||||
X"00000000", -- [0x00400070] nop
|
||||
X"00000000", -- [0x00400074] nop
|
||||
X"00000000", -- [0x00400078] nop
|
||||
X"00000000", -- [0x0040007c] nop
|
||||
X"00000000", -- [0x00400080] nop
|
||||
X"00000000", -- [0x00400084] nop
|
||||
X"00000000", -- [0x00400088] nop
|
||||
X"00000000", -- [0x0040008c] nop
|
||||
X"00000000", -- [0x00400090] nop
|
||||
X"00000000", -- [0x00400094] nop
|
||||
X"00000000", -- [0x00400098] nop
|
||||
X"00000000", -- [0x0040009c] nop
|
||||
X"00000000", -- [0x004000a0] nop
|
||||
X"00000000", -- [0x004000a4] nop
|
||||
X"00000000", -- [0x004000a8] nop
|
||||
X"00000000", -- [0x004000ac] nop
|
||||
X"00000000", -- [0x004000b0] nop
|
||||
X"00000000", -- [0x004000b4] nop
|
||||
X"00000000", -- [0x004000b8]
|
||||
X"00000000", -- [0x004000bc]
|
||||
X"00000000", -- [0x004000c0]
|
||||
X"00000000", -- [0x004000c4]
|
||||
X"00000000", -- [0x004000c8]
|
||||
X"00000000", -- [0x004000cc]
|
||||
X"00000000", -- [0x004000d0]
|
||||
X"00000000", -- [0x004000d4]
|
||||
X"00000000", -- [0x004000d8]
|
||||
X"00000000", -- [0x004000dc]
|
||||
X"00000000", -- [0x004000e0]
|
||||
X"00000000", -- [0x004000e4]
|
||||
X"00000000", -- [0x004000e8]
|
||||
X"00000000", -- [0x004000ec]
|
||||
X"00000000", -- [0x004000f0]
|
||||
X"00000000", -- [0x004000f4]
|
||||
X"00000000", -- [0x004000f8]
|
||||
X"00000000" -- [0x004000fc]
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,122 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
|
||||
X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main
|
||||
X"00000000", -- [0x00400004] nop ; 7: sll $0, $0, 0
|
||||
X"3c011000", -- [0x00400008] lui $1, 4096 ; 8: lui $1, 0x1000
|
||||
X"20220000", -- [0x0040000c] addi $2, $1, 0 ; 9: addi $2, $1, 0
|
||||
X"3c071234", -- [0x00400010] lui $7, 4660 ; 10: lui $7, 0x1234
|
||||
X"3c050001", -- [0x00400014] lui $5, 1 ; 11: lui $5, 0x0001
|
||||
X"ac270000", -- [0x00400018] sw $7, 0($1) ; 12: sw $7, 0($1)
|
||||
X"8c430000", -- [0x0040001c] lw $3, 0($2) ; 13: lw $3, 0($2)
|
||||
X"00654020", -- [0x00400020] add $8, $3, $5 ; 14: add $8, $3, $5
|
||||
X"00654820", -- [0x00400024] add $9, $3, $5 ; 15: add $9, $3, $5
|
||||
X"00655020", -- [0x00400028] add $10, $3, $5 ; 16: add $10, $3, $5
|
||||
X"00655820", -- [0x0040002c] add $11, $3, $5 ; 17: add $11, $3, $5
|
||||
X"00000000", -- [0x00400030] nop ; 18: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0
|
||||
X"08100001", -- [0x00400038] j 0x00400004 [main] ; 20: j main
|
||||
X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,122 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
|
||||
X"08100001", -- [0x00400000] j 0x00400004 [main]
|
||||
X"3c018000", -- [0x00400004] lui $1, -32768
|
||||
X"3c020000", -- [0x00400008] lui $2, 0
|
||||
X"3c030000", -- [0x0040000c] lui $3, 0
|
||||
X"34420001", -- [0x00400010] ori $2, $2, 1
|
||||
X"34630003", -- [0x00400014] ori $3, $3, 3
|
||||
X"00010842", -- [0x00400018] srl $1, $1, 1
|
||||
X"00010840", -- [0x0040001c] sll $1, $1, 1
|
||||
X"00010843", -- [0x00400020] sra $1, $1, 1
|
||||
X"000108c3", -- [0x00400024] sra $1, $1, 3
|
||||
X"00612004", -- [0x00400028] sllv $4, $1, $3
|
||||
X"00412807", -- [0x0040002c] srav $5, $1, $2
|
||||
X"00613007", -- [0x00400030] srav $6, $1, $3
|
||||
X"3c1f0040", -- [0x00400034] lui $31, 64
|
||||
X"03e00008", -- [0x00400038] jr $31
|
||||
X"00000000", -- [0x0040003c] nop
|
||||
X"00000000", -- [0x00400040] nop
|
||||
X"00000000", -- [0x00400044] nop
|
||||
X"00000000", -- [0x00400048] nop
|
||||
X"00000000", -- [0x0040004c] nop
|
||||
X"00000000", -- [0x00400050] nop
|
||||
X"00000000", -- [0x00400054] nop
|
||||
X"00000000", -- [0x00400058] nop
|
||||
X"00000000", -- [0x0040005c] nop
|
||||
X"00000000", -- [0x00400060] nop
|
||||
X"00000000", -- [0x00400064] nop
|
||||
X"00000000", -- [0x00400068] nop
|
||||
X"00000000", -- [0x0040006c] nop
|
||||
X"00000000", -- [0x00400070] nop
|
||||
X"00000000", -- [0x00400074] nop
|
||||
X"00000000", -- [0x00400078] nop
|
||||
X"00000000", -- [0x0040007c] nop
|
||||
X"00000000", -- [0x00400080] nop
|
||||
X"00000000", -- [0x00400084] nop
|
||||
X"00000000", -- [0x00400088] nop
|
||||
X"00000000", -- [0x0040008c] nop
|
||||
X"00000000", -- [0x00400090] nop
|
||||
X"00000000", -- [0x00400094] nop
|
||||
X"00000000", -- [0x00400098] nop
|
||||
X"00000000", -- [0x0040009c] nop
|
||||
X"00000000", -- [0x004000a0] nop
|
||||
X"00000000", -- [0x004000a4] nop
|
||||
X"00000000", -- [0x004000a8] nop
|
||||
X"00000000", -- [0x004000ac] nop
|
||||
X"00000000", -- [0x004000b0] nop
|
||||
X"00000000", -- [0x004000b4] nop
|
||||
X"00000000", -- [0x004000b8] nop
|
||||
X"00000000", -- [0x004000bc] nop
|
||||
X"00000000", -- [0x004000c0] nop
|
||||
X"00000000", -- [0x004000c4] nop
|
||||
X"00000000", -- [0x004000c8] nop
|
||||
X"00000000", -- [0x004000cc] nop
|
||||
X"00000000", -- [0x004000d0] nop
|
||||
X"00000000", -- [0x004000d4] nop
|
||||
X"00000000", -- [0x004000d8] nop
|
||||
X"00000000", -- [0x004000dc] nop
|
||||
X"00000000", -- [0x004000e0] nop
|
||||
X"00000000", -- [0x004000e4] nop
|
||||
X"00000000", -- [0x004000e8] nop
|
||||
X"00000000", -- [0x004000ec] nop
|
||||
X"00000000", -- [0x004000f0] nop
|
||||
X"00000000", -- [0x004000f4] nop
|
||||
X"00000000", -- [0x004000f8] nop
|
||||
X"00000000" -- [0x004000fc] nop
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,121 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main
|
||||
X"3c080000", -- [0x00400004] lui $8, 0 ; 7: lui $8, 0
|
||||
X"00000000", -- [0x00400008] nop ; 8: sll $0, $0, 0
|
||||
X"0c100009", -- [0x0040000c] jal 0x00400024 [subr1] ; 9: jal subr1
|
||||
X"3c010040", -- [0x00400010] lui $1, 64 [subr2] ; 10: la $2, subr2
|
||||
X"34220030", -- [0x00400014] ori $2, $1, 48 [subr2]
|
||||
X"00407809", -- [0x00400018] jalr $15, $2 ; 11: jalr $15, $2
|
||||
X"00000000", -- [0x0040001c] nop ; 12: sll $0, $0, 0
|
||||
X"08100002", -- [0x00400020] j 0x00400008 [loop] ; 13: j loop
|
||||
X"21080001", -- [0x00400024] addi $8, $8, 1 ; 15: addi $8, 1
|
||||
X"00000000", -- [0x00400028] nop ; 16: sll $0, $0, 0
|
||||
X"03e00008", -- [0x0040002c] jr $31 ; 17: jr $31
|
||||
X"21080010", -- [0x00400030] addi $8, $8, 16 ; 18: addi $8, 16
|
||||
X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0
|
||||
X"01e00008", -- [0x00400038] jr $15 ; 20: jr $15
|
||||
X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0
|
||||
X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0
|
||||
X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,121 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
X"3c011234", -- [0x00400000] lui $1, 4660
|
||||
X"34225678", -- [0x00400004] ori $2, $1, 22136
|
||||
X"3c012345", -- [0x00400008] lui $1, 9029
|
||||
X"34236789", -- [0x0040000c] ori $3, $1, 26505
|
||||
X"3c018765", -- [0x00400010] lui $1, -30875
|
||||
X"34244321", -- [0x00400014] ori $4, $1, 17185
|
||||
X"3c019876", -- [0x00400018] lui $1, -26506
|
||||
X"34255432", -- [0x0040001c] ori $5, $1, 21554
|
||||
X"00000000", -- [0x00400020] nop
|
||||
X"00427823", -- [0x00400024] subu $15, $2, $2
|
||||
X"00437823", -- [0x00400028] subu $15, $2, $3
|
||||
X"00447823", -- [0x0040002c] subu $15, $2, $4
|
||||
X"00457823", -- [0x00400030] subu $15, $2, $5
|
||||
X"00627823", -- [0x00400034] subu $15, $3, $2
|
||||
X"00637823", -- [0x00400038] subu $15, $3, $3
|
||||
X"00647823", -- [0x0040003c] subu $15, $3, $4
|
||||
X"00657823", -- [0x00400040] subu $15, $3, $5
|
||||
X"00827823", -- [0x00400044] subu $15, $4, $2
|
||||
X"00837823", -- [0x00400048] subu $15, $4, $3
|
||||
X"00847823", -- [0x0040004c] subu $15, $4, $4
|
||||
X"00857823", -- [0x00400050] subu $15, $4, $5
|
||||
X"00a27823", -- [0x00400054] subu $15, $5, $2
|
||||
X"00a37823", -- [0x00400058] subu $15, $5, $3
|
||||
X"00a47823", -- [0x0040005c] subu $15, $5, $4
|
||||
X"00a57823", -- [0x00400060] subu $15, $5, $5
|
||||
X"00000000", -- [0x00400064] nop
|
||||
X"00427822", -- [0x00400068] sub $15, $2, $2
|
||||
X"00437822", -- [0x0040006c] sub $15, $2, $3
|
||||
X"00447822", -- [0x00400070] sub $15, $2, $4
|
||||
X"00457822", -- [0x00400074] sub $15, $2, $5
|
||||
X"00627822", -- [0x00400078] sub $15, $3, $2
|
||||
X"00637822", -- [0x0040007c] sub $15, $3, $3
|
||||
X"00647822", -- [0x00400080] sub $15, $3, $4
|
||||
X"00657822", -- [0x00400084] sub $15, $3, $5
|
||||
X"00827822", -- [0x00400088] sub $15, $4, $2
|
||||
X"00837822", -- [0x0040008c] sub $15, $4, $3
|
||||
X"00847822", -- [0x00400090] sub $15, $4, $4
|
||||
X"00857822", -- [0x00400094] sub $15, $4, $5
|
||||
X"00a27822", -- [0x00400098] sub $15, $5, $2
|
||||
X"00a37822", -- [0x0040009c] sub $15, $5, $3
|
||||
X"00a47822", -- [0x004000a0] sub $15, $5, $4
|
||||
X"00a57822", -- [0x004000a4] sub $15, $5, $5
|
||||
X"00000000", -- [0x004000a8] nop
|
||||
X"08104000", -- [0x004000ac] j 0x00410000 [main]
|
||||
X"00000000", -- [0x004000b0] nop
|
||||
X"00000000", -- [0x004000b4]
|
||||
X"00000000", -- [0x004000b8]
|
||||
X"00000000", -- [0x004000bc]
|
||||
X"00000000", -- [0x004000c0]
|
||||
X"00000000", -- [0x004000c4]
|
||||
X"00000000", -- [0x004000c8]
|
||||
X"00000000", -- [0x004000cc]
|
||||
X"00000000", -- [0x004000d0]
|
||||
X"00000000", -- [0x004000d4]
|
||||
X"00000000", -- [0x004000d8]
|
||||
X"00000000", -- [0x004000dc]
|
||||
X"00000000", -- [0x004000e0]
|
||||
X"00000000", -- [0x004000e4]
|
||||
X"00000000", -- [0x004000e8]
|
||||
X"00000000", -- [0x004000ec]
|
||||
X"00000000", -- [0x004000f0]
|
||||
X"00000000", -- [0x004000f4]
|
||||
X"00000000", -- [0x004000f8]
|
||||
X"00000000" -- [0x004000fc]
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,121 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
X"3c011234", -- [0x00400000] lui $1, 4660
|
||||
X"34225678", -- [0x00400004] ori $2, $1, 22136
|
||||
X"3c012345", -- [0x00400008] lui $1, 9029
|
||||
X"34236789", -- [0x0040000c] ori $3, $1, 26505
|
||||
X"3c018765", -- [0x00400010] lui $1, -30875
|
||||
X"34244321", -- [0x00400014] ori $4, $1, 17185
|
||||
X"3c019876", -- [0x00400018] lui $1, -26506
|
||||
X"34255432", -- [0x0040001c] ori $5, $1, 21554
|
||||
X"3c081000", -- [0x00400020] lui $8, 4096
|
||||
X"00000000", -- [0x00400024] nop
|
||||
X"0042782b", -- [0x00400028] sltu $15, $2, $2
|
||||
X"0043782b", -- [0x0040002c] sltu $15, $2, $3
|
||||
X"0044782b", -- [0x00400030] sltu $15, $2, $4
|
||||
X"0045782b", -- [0x00400034] sltu $15, $2, $5
|
||||
X"0062782b", -- [0x00400038] sltu $15, $3, $2
|
||||
X"0063782b", -- [0x0040003c] sltu $15, $3, $3
|
||||
X"0064782b", -- [0x00400040] sltu $15, $3, $4
|
||||
X"0065782b", -- [0x00400044] sltu $15, $3, $5
|
||||
X"0082782b", -- [0x00400048] sltu $15, $4, $2
|
||||
X"0083782b", -- [0x0040004c] sltu $15, $4, $3
|
||||
X"0084782b", -- [0x00400050] sltu $15, $4, $4
|
||||
X"0085782b", -- [0x00400054] sltu $15, $4, $5
|
||||
X"00a2782b", -- [0x00400058] sltu $15, $5, $2
|
||||
X"00a3782b", -- [0x0040005c] sltu $15, $5, $3
|
||||
X"00a4782b", -- [0x00400060] sltu $15, $5, $4
|
||||
X"00a5782b", -- [0x00400064] sltu $15, $5, $5
|
||||
X"00000000", -- [0x00400068] nop
|
||||
X"0042782a", -- [0x0040006c] slt $15, $2, $2
|
||||
X"0043782a", -- [0x00400070] slt $15, $2, $3
|
||||
X"0044782a", -- [0x00400074] slt $15, $2, $4
|
||||
X"0045782a", -- [0x00400078] slt $15, $2, $5
|
||||
X"0062782a", -- [0x0040007c] slt $15, $3, $2
|
||||
X"0063782a", -- [0x00400080] slt $15, $3, $3
|
||||
X"0064782a", -- [0x00400084] slt $15, $3, $4
|
||||
X"0065782a", -- [0x00400088] slt $15, $3, $5
|
||||
X"0082782a", -- [0x0040008c] slt $15, $4, $2
|
||||
X"0083782a", -- [0x00400090] slt $15, $4, $3
|
||||
X"0084782a", -- [0x00400094] slt $15, $4, $4
|
||||
X"0085782a", -- [0x00400098] slt $15, $4, $5
|
||||
X"00a2782a", -- [0x0040009c] slt $15, $5, $2
|
||||
X"00a3782a", -- [0x004000a0] slt $15, $5, $3
|
||||
X"00a4782a", -- [0x004000a4] slt $15, $5, $4
|
||||
X"00a5782a", -- [0x004000a8] slt $15, $5, $5
|
||||
X"00000000", -- [0x004000ac] nop
|
||||
X"08104000", -- [0x004000b0] j 0x00410000 [main]
|
||||
X"00000000", -- [0x004000b4] nop
|
||||
X"00000000", -- [0x004000b8]
|
||||
X"00000000", -- [0x004000bc]
|
||||
X"00000000", -- [0x004000c0]
|
||||
X"00000000", -- [0x004000c4]
|
||||
X"00000000", -- [0x004000c8]
|
||||
X"00000000", -- [0x004000cc]
|
||||
X"00000000", -- [0x004000d0]
|
||||
X"00000000", -- [0x004000d4]
|
||||
X"00000000", -- [0x004000d8]
|
||||
X"00000000", -- [0x004000dc]
|
||||
X"00000000", -- [0x004000e0]
|
||||
X"00000000", -- [0x004000e4]
|
||||
X"00000000", -- [0x004000e8]
|
||||
X"00000000", -- [0x004000ec]
|
||||
X"00000000", -- [0x004000f0]
|
||||
X"00000000", -- [0x004000f4]
|
||||
X"00000000", -- [0x004000f8]
|
||||
X"00000000" -- [0x004000fc]
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,121 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
X"3c011234", -- [0x00400000] lui $1, 4660
|
||||
X"34225678", -- [0x00400004] ori $2, $1, 22136
|
||||
X"3c012345", -- [0x00400008] lui $1, 9029
|
||||
X"34236789", -- [0x0040000c] ori $3, $1, 26505
|
||||
X"3c018765", -- [0x00400010] lui $1, -30875
|
||||
X"34244321", -- [0x00400014] ori $4, $1, 17185
|
||||
X"3c019876", -- [0x00400018] lui $1, -26506
|
||||
X"34255432", -- [0x0040001c] ori $5, $1, 21554
|
||||
X"3c081000", -- [0x00400020] lui $8, 4096
|
||||
X"00000000", -- [0x00400024] nop
|
||||
X"2c4f1234", -- [0x00400028] sltiu $15, $2, 4660
|
||||
X"2c4f2345", -- [0x0040002c] sltiu $15, $2, 9029
|
||||
X"2c4fedcc", -- [0x00400030] sltiu $15, $2, -4660
|
||||
X"2c4fdcbb", -- [0x00400034] sltiu $15, $2, -9029
|
||||
X"2c6f1234", -- [0x00400038] sltiu $15, $3, 4660
|
||||
X"2c6f2345", -- [0x0040003c] sltiu $15, $3, 9029
|
||||
X"2c6fedcc", -- [0x00400040] sltiu $15, $3, -4660
|
||||
X"2c6fdcbb", -- [0x00400044] sltiu $15, $3, -9029
|
||||
X"2c8f1234", -- [0x00400048] sltiu $15, $4, 4660
|
||||
X"2c8f2345", -- [0x0040004c] sltiu $15, $4, 9029
|
||||
X"2c8fedcc", -- [0x00400050] sltiu $15, $4, -4660
|
||||
X"2c8fdcbb", -- [0x00400054] sltiu $15, $4, -9029
|
||||
X"2caf1234", -- [0x00400058] sltiu $15, $5, 4660
|
||||
X"2caf2345", -- [0x0040005c] sltiu $15, $5, 9029
|
||||
X"2cafedcc", -- [0x00400060] sltiu $15, $5, -4660
|
||||
X"2cafdcbb", -- [0x00400064] sltiu $15, $5, -9029
|
||||
X"00000000", -- [0x00400068] nop
|
||||
X"284f1234", -- [0x0040006c] slti $15, $2, 4660
|
||||
X"284f2345", -- [0x00400070] slti $15, $2, 9029
|
||||
X"284fedcc", -- [0x00400074] slti $15, $2, -4660
|
||||
X"284fdcbb", -- [0x00400078] slti $15, $2, -9029
|
||||
X"286f1234", -- [0x0040007c] slti $15, $3, 4660
|
||||
X"286f2345", -- [0x00400080] slti $15, $3, 9029
|
||||
X"286fedcc", -- [0x00400084] slti $15, $3, -4660
|
||||
X"286fdcbb", -- [0x00400088] slti $15, $3, -9029
|
||||
X"288f1234", -- [0x0040008c] slti $15, $4, 4660
|
||||
X"288f2345", -- [0x00400090] slti $15, $4, 9029
|
||||
X"288fedcc", -- [0x00400094] slti $15, $4, -4660
|
||||
X"288fdcbb", -- [0x00400098] slti $15, $4, -9029
|
||||
X"28af1234", -- [0x0040009c] slti $15, $5, 4660
|
||||
X"28af2345", -- [0x004000a0] slti $15, $5, 9029
|
||||
X"28afedcc", -- [0x004000a4] slti $15, $5, -4660
|
||||
X"28afdcbb", -- [0x004000a8] slti $15, $5, -9029
|
||||
X"00000000", -- [0x004000ac] nop
|
||||
X"08104000", -- [0x004000b0] j 0x00410000 [main]
|
||||
X"00000000", -- [0x004000b4] nop
|
||||
X"00000000", -- [0x004000b8]
|
||||
X"00000000", -- [0x004000bc]
|
||||
X"00000000", -- [0x004000c0]
|
||||
X"00000000", -- [0x004000c4]
|
||||
X"00000000", -- [0x004000c8]
|
||||
X"00000000", -- [0x004000cc]
|
||||
X"00000000", -- [0x004000d0]
|
||||
X"00000000", -- [0x004000d4]
|
||||
X"00000000", -- [0x004000d8]
|
||||
X"00000000", -- [0x004000dc]
|
||||
X"00000000", -- [0x004000e0]
|
||||
X"00000000", -- [0x004000e4]
|
||||
X"00000000", -- [0x004000e8]
|
||||
X"00000000", -- [0x004000ec]
|
||||
X"00000000", -- [0x004000f0]
|
||||
X"00000000", -- [0x004000f4]
|
||||
X"00000000", -- [0x004000f8]
|
||||
X"00000000" -- [0x004000fc]
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,121 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY rom IS
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 2;
|
||||
data_width : integer := 32
|
||||
);
|
||||
Port
|
||||
(
|
||||
addr : in unsigned(addr_width-1 downto 0);
|
||||
dout : out unsigned(data_width-1 downto 0)
|
||||
);
|
||||
END rom;
|
||||
|
||||
ARCHITECTURE itest OF rom IS
|
||||
|
||||
subtype word_t is unsigned(data_width-1 downto 0);
|
||||
type word_array_t is array (0 to 2**addr_width-1) of word_t;
|
||||
|
||||
-- Assembled from itest.jsm
|
||||
constant word_array : word_array_t :=
|
||||
(
|
||||
X"3c011234", -- [0x00400000] lui $1, 4660
|
||||
X"34225678", -- [0x00400004] ori $2, $1, 22136
|
||||
X"3c012345", -- [0x00400008] lui $1, 9029
|
||||
X"34236789", -- [0x0040000c] ori $3, $1, 26505
|
||||
X"3c018765", -- [0x00400010] lui $1, -30875
|
||||
X"34244321", -- [0x00400014] ori $4, $1, 17185
|
||||
X"3c019876", -- [0x00400018] lui $1, -26506
|
||||
X"34255432", -- [0x0040001c] ori $5, $1, 21554
|
||||
X"00000000", -- [0x00400020] nop
|
||||
X"00427823", -- [0x00400024] subu $15, $2, $2
|
||||
X"00437823", -- [0x00400028] subu $15, $2, $3
|
||||
X"00447823", -- [0x0040002c] subu $15, $2, $4
|
||||
X"00457823", -- [0x00400030] subu $15, $2, $5
|
||||
X"00627823", -- [0x00400034] subu $15, $3, $2
|
||||
X"00637823", -- [0x00400038] subu $15, $3, $3
|
||||
X"00647823", -- [0x0040003c] subu $15, $3, $4
|
||||
X"00657823", -- [0x00400040] subu $15, $3, $5
|
||||
X"00827823", -- [0x00400044] subu $15, $4, $2
|
||||
X"00837823", -- [0x00400048] subu $15, $4, $3
|
||||
X"00847823", -- [0x0040004c] subu $15, $4, $4
|
||||
X"00857823", -- [0x00400050] subu $15, $4, $5
|
||||
X"00a27823", -- [0x00400054] subu $15, $5, $2
|
||||
X"00a37823", -- [0x00400058] subu $15, $5, $3
|
||||
X"00a47823", -- [0x0040005c] subu $15, $5, $4
|
||||
X"00a57823", -- [0x00400060] subu $15, $5, $5
|
||||
X"00000000", -- [0x00400064] nop
|
||||
X"00427822", -- [0x00400068] sub $15, $2, $2
|
||||
X"00437822", -- [0x0040006c] sub $15, $2, $3
|
||||
X"00447822", -- [0x00400070] sub $15, $2, $4
|
||||
X"00457822", -- [0x00400074] sub $15, $2, $5
|
||||
X"00627822", -- [0x00400078] sub $15, $3, $2
|
||||
X"00637822", -- [0x0040007c] sub $15, $3, $3
|
||||
X"00647822", -- [0x00400080] sub $15, $3, $4
|
||||
X"00657822", -- [0x00400084] sub $15, $3, $5
|
||||
X"00827822", -- [0x00400088] sub $15, $4, $2
|
||||
X"00837822", -- [0x0040008c] sub $15, $4, $3
|
||||
X"00847822", -- [0x00400090] sub $15, $4, $4
|
||||
X"00857822", -- [0x00400094] sub $15, $4, $5
|
||||
X"00a27822", -- [0x00400098] sub $15, $5, $2
|
||||
X"00a37822", -- [0x0040009c] sub $15, $5, $3
|
||||
X"00a47822", -- [0x004000a0] sub $15, $5, $4
|
||||
X"00a57822", -- [0x004000a4] sub $15, $5, $5
|
||||
X"00000000", -- [0x004000a8] nop
|
||||
X"08104000", -- [0x004000ac] j 0x00410000 [main]
|
||||
X"00000000", -- [0x004000b0] nop
|
||||
X"00000000", -- [0x004000b4]
|
||||
X"00000000", -- [0x004000b8]
|
||||
X"00000000", -- [0x004000bc]
|
||||
X"00000000", -- [0x004000c0]
|
||||
X"00000000", -- [0x004000c4]
|
||||
X"00000000", -- [0x004000c8]
|
||||
X"00000000", -- [0x004000cc]
|
||||
X"00000000", -- [0x004000d0]
|
||||
X"00000000", -- [0x004000d4]
|
||||
X"00000000", -- [0x004000d8]
|
||||
X"00000000", -- [0x004000dc]
|
||||
X"00000000", -- [0x004000e0]
|
||||
X"00000000", -- [0x004000e4]
|
||||
X"00000000", -- [0x004000e8]
|
||||
X"00000000", -- [0x004000ec]
|
||||
X"00000000", -- [0x004000f0]
|
||||
X"00000000", -- [0x004000f4]
|
||||
X"00000000", -- [0x004000f8]
|
||||
X"00000000" -- [0x004000fc]
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
dout <= word_array(to_integer(addr));
|
||||
|
||||
end itest;
|
||||
@@ -1,332 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
|
||||
entity mips_embedded is
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
halt : in STD_LOGIC;
|
||||
int : in unsigned(5 downto 0);
|
||||
rxd : in STD_LOGIC;
|
||||
txd : out STD_LOGIC;
|
||||
dout : out word_t
|
||||
);
|
||||
end mips_embedded;
|
||||
|
||||
architecture rtl of mips_embedded is
|
||||
|
||||
COMPONENT mips_top
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
int : in unsigned(5 downto 0);
|
||||
mem_rdy : in STD_LOGIC;
|
||||
mem_re : out STD_LOGIC;
|
||||
mem_en : out STD_LOGIC;
|
||||
mem_we : out unsigned(3 downto 0);
|
||||
mem_din : in word_t;
|
||||
mem_dout : out word_t;
|
||||
mem_addr : out word_t
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal mem_din : word_t;
|
||||
signal mem_dout : word_t;
|
||||
signal mem_addr : word_t;
|
||||
signal mem_re : std_logic;
|
||||
signal mem_en : std_logic;
|
||||
signal mem_we : unsigned(3 downto 0);
|
||||
signal mem_rdy : std_logic;
|
||||
|
||||
subtype tick_usec_t is natural range 0 to 99;
|
||||
signal tick_usec : tick_usec_t;
|
||||
signal cnt_usec : word_t;
|
||||
signal cnt_sec : word_t;
|
||||
signal cnt_usec_preset : word_t;
|
||||
signal cnt_sec_preset : word_t;
|
||||
signal cnt_usec_en : std_logic;
|
||||
signal cnt_usec_we : std_logic;
|
||||
signal cnt_sec_en : std_logic;
|
||||
signal cnt_sec_we : std_logic;
|
||||
|
||||
COMPONENT uart_tx
|
||||
Port
|
||||
(
|
||||
data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT uart_rx
|
||||
Port
|
||||
(
|
||||
serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal baud_count : unsigned(7 downto 0);
|
||||
signal en_16_x_baud : std_logic;
|
||||
signal reg_we_uart_tx : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
signal reg_uart_tx : unsigned(7 downto 0);
|
||||
signal reg_re_uart_rx : std_logic;
|
||||
signal reg_uart_rx : std_logic_vector(7 downto 0);
|
||||
signal rx_data_present : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
signal uart_status_port : unsigned(7 downto 0);
|
||||
signal reg_uart_ctrl : unsigned(7 downto 0);
|
||||
signal reg_uart_baud : unsigned(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
registers_write:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
reg_we_uart_tx <= '0';
|
||||
cnt_usec_we <= '0';
|
||||
cnt_sec_we <= '0';
|
||||
if rst = '1' then
|
||||
dout <= (others => '0');
|
||||
reg_uart_baud <= to_unsigned(53, 8);
|
||||
reg_uart_ctrl <= to_unsigned(0, 8);
|
||||
elsif mem_en = '1' then
|
||||
case mem_addr(5 downto 2) is
|
||||
|
||||
when "0000" =>
|
||||
if mem_we(0) = '1' then
|
||||
dout(7 downto 0) <= mem_dout(7 downto 0);
|
||||
end if;
|
||||
if mem_we(1) = '1' then
|
||||
dout(15 downto 8) <= mem_dout(15 downto 8);
|
||||
end if;
|
||||
if mem_we(2) = '1' then
|
||||
dout(23 downto 16) <= mem_dout(23 downto 16);
|
||||
end if;
|
||||
if mem_we(3) = '1' then
|
||||
dout(31 downto 24) <= mem_dout(31 downto 24);
|
||||
end if;
|
||||
|
||||
when "0001" =>
|
||||
if mem_we(0) = '1' then
|
||||
reg_we_uart_tx <= '1';
|
||||
reg_uart_tx <= mem_dout(7 downto 0);
|
||||
end if;
|
||||
|
||||
when "0010" =>
|
||||
if mem_we(0) = '1' then
|
||||
reg_uart_ctrl <= mem_dout(7 downto 0);
|
||||
end if;
|
||||
if mem_we(1) = '1' then
|
||||
reg_uart_baud <= mem_dout(15 downto 8);
|
||||
end if;
|
||||
|
||||
when "0100" =>
|
||||
if mem_we(3) = '1' then
|
||||
cnt_usec_we <= '1';
|
||||
cnt_usec_preset <= mem_dout;
|
||||
end if;
|
||||
|
||||
when "0101" =>
|
||||
if mem_we(3) = '1' then
|
||||
cnt_sec_we <= '1';
|
||||
cnt_sec_preset <= mem_dout;
|
||||
end if;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
registers_read:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
reg_re_uart_rx <= '0';
|
||||
if mem_en = '1' then
|
||||
mem_din <= (others => '0');
|
||||
case mem_addr(5 downto 2) is
|
||||
|
||||
when "0000" => null;
|
||||
|
||||
when "0001" =>
|
||||
reg_re_uart_rx <= '1';
|
||||
mem_din(7 downto 0) <= unsigned(reg_uart_rx);
|
||||
|
||||
when "0010" =>
|
||||
mem_din(7 downto 0) <= uart_status_port;
|
||||
mem_din(15 downto 8) <= reg_uart_baud;
|
||||
|
||||
when "0100" =>
|
||||
mem_din <= cnt_usec;
|
||||
|
||||
when "0101" =>
|
||||
mem_din <= cnt_sec;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mem_rdy <= not halt;
|
||||
|
||||
inst_mips_top: mips_top
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
int => int,
|
||||
mem_rdy => mem_rdy,
|
||||
mem_en => mem_en,
|
||||
mem_we => mem_we,
|
||||
mem_din => mem_din,
|
||||
mem_dout => mem_dout,
|
||||
mem_addr => mem_addr
|
||||
);
|
||||
|
||||
inst_uart_tx: uart_tx
|
||||
port map
|
||||
(
|
||||
data_in => std_logic_vector(reg_uart_tx),
|
||||
write_buffer => reg_we_uart_tx,
|
||||
reset_buffer => rst,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => txd,
|
||||
buffer_full => tx_full,
|
||||
buffer_half_full => tx_half_full,
|
||||
clk => clk
|
||||
);
|
||||
|
||||
inst_uart_rx: uart_rx
|
||||
port map
|
||||
(
|
||||
serial_in => rxd,
|
||||
data_out => reg_uart_rx,
|
||||
read_buffer => reg_re_uart_rx,
|
||||
reset_buffer => rst,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
buffer_data_present => rx_data_present,
|
||||
buffer_full => rx_full,
|
||||
buffer_half_full => rx_half_full,
|
||||
clk => clk
|
||||
);
|
||||
|
||||
uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
|
||||
|
||||
tick_usec_timer:
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
cnt_usec_en <= '0';
|
||||
if rst = '1' then
|
||||
tick_usec <= 0;
|
||||
cnt_usec_en <= '0';
|
||||
elsif tick_usec = tick_usec_t'high then
|
||||
tick_usec <= 0;
|
||||
cnt_usec_en <= '1';
|
||||
else
|
||||
tick_usec <= tick_usec + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cnt_usec_timer:
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
cnt_sec_en <= '0';
|
||||
if rst = '1' then
|
||||
cnt_usec <= (others => '0');
|
||||
cnt_sec_en <= '0';
|
||||
elsif cnt_usec_we = '1' then
|
||||
cnt_usec <= cnt_usec_preset;
|
||||
elsif cnt_usec_en = '1' then
|
||||
if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then
|
||||
cnt_usec <= (others => '0');
|
||||
cnt_sec_en <= '1';
|
||||
else
|
||||
cnt_usec <= cnt_usec + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cnt_sec_timer:
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
if rst = '1' then
|
||||
cnt_sec <= (others => '0');
|
||||
elsif cnt_sec_we = '1' then
|
||||
cnt_sec <= cnt_sec_preset;
|
||||
elsif cnt_sec_en = '1' then
|
||||
cnt_sec <= cnt_sec + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
baud_timer:
|
||||
process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
if rst = '1' then
|
||||
baud_count <= (others => '0');
|
||||
elsif baud_count = reg_uart_baud then
|
||||
baud_count <= (others => '0');
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
en_16_x_baud <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
@@ -1,137 +0,0 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
|
||||
entity mips_embedded_syn is
|
||||
Port
|
||||
(
|
||||
sys_rst_n_in : in STD_LOGIC;
|
||||
sys_clk_in : in STD_LOGIC;
|
||||
sys_dip : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
sys_btn : in STD_LOGIC_VECTOR (8 downto 0);
|
||||
sys_led : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
sys_rx : in STD_LOGIC;
|
||||
sys_tx : out STD_LOGIC;
|
||||
sys_error : out STD_LOGIC_VECTOR (1 downto 0)
|
||||
);
|
||||
|
||||
end mips_embedded_syn;
|
||||
|
||||
architecture struct of mips_embedded_syn is
|
||||
|
||||
COMPONENT mips_embedded
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
halt : in STD_LOGIC;
|
||||
int : in unsigned(5 downto 0);
|
||||
rxd : in STD_LOGIC;
|
||||
txd : out STD_LOGIC;
|
||||
dout : out word_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal dout : word_t;
|
||||
signal rst : STD_LOGIC;
|
||||
signal clk : STD_LOGIC;
|
||||
signal halt : STD_LOGIC;
|
||||
signal int : unsigned(5 downto 0);
|
||||
signal btn_r : unsigned (8 downto 0);
|
||||
signal dip_r : unsigned (7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-------------------------------------------------------------------
|
||||
inst_mips_embedded: mips_embedded
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
halt => halt,
|
||||
int => int,
|
||||
rxd => sys_rx,
|
||||
txd => sys_tx,
|
||||
dout => dout
|
||||
);
|
||||
|
||||
clk <= sys_clk_in;
|
||||
rst <= not sys_rst_n_in;
|
||||
|
||||
ERR_LED_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
sys_error <= (others => '1');
|
||||
elsif rising_edge(clk) then
|
||||
sys_error <= STD_LOGIC_VECTOR(dout(31 downto 30));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
LED_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
sys_led <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
sys_led <= STD_LOGIC_VECTOR(dout(7 downto 0));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DIP_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
dip_r <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
dip_r <= unsigned(sys_dip);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
BTN_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
btn_r <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
btn_r <= unsigned(sys_btn);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
halt <= btn_r(4) after 6.5 ns;
|
||||
int(0) <= dip_r(0) and btn_r(3) after 1 ns;
|
||||
int(1) <= dip_r(1) and btn_r(3) after 1 ns;
|
||||
int(2) <= dip_r(2) and btn_r(3) after 1 ns;
|
||||
int(3) <= dip_r(3) and btn_r(3) after 1 ns;
|
||||
int(4) <= dip_r(4) and btn_r(3) after 1 ns;
|
||||
int(5) <= dip_r(5) and btn_r(3) after 1 ns;
|
||||
|
||||
-------------------------------------------------------------------
|
||||
|
||||
end struct;
|
||||
@@ -1,115 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY ram IS
|
||||
Generic
|
||||
(
|
||||
word_addr_width : integer := 6
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
we : in unsigned(3 downto 0);
|
||||
ce : in STD_LOGIC;
|
||||
addr : in unsigned(31 downto 0);
|
||||
din : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END ram;
|
||||
|
||||
ARCHITECTURE behavior OF ram IS
|
||||
|
||||
constant depth : natural := 2**word_addr_width;
|
||||
|
||||
type sram_t is array (0 to depth-1) of unsigned(7 downto 0);
|
||||
|
||||
function sram_clear return sram_t is
|
||||
|
||||
variable result : sram_t;
|
||||
begin
|
||||
for i in 0 to sram_t'length-1 loop
|
||||
result(i) := (others => '0');
|
||||
end loop;
|
||||
return result;
|
||||
end sram_clear;
|
||||
|
||||
signal sram0, sram1, sram2, sram3 : sram_t := sram_clear;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
SRAM_RW:
|
||||
process(clk)
|
||||
variable index : natural range 0 to depth-1;
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||
if we(0) = '1' then
|
||||
sram0(index)<= din(7 downto 0);
|
||||
end if;
|
||||
dout(7 downto 0) <= sram0(index);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
variable index : natural range 0 to depth-1;
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||
if we(1) = '1' then
|
||||
sram1(index)<= din(15 downto 8);
|
||||
end if;
|
||||
dout(15 downto 8) <= sram1(index);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
variable index : natural range 0 to depth-1;
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||
if we(2) = '1' then
|
||||
sram2(index)<= din(23 downto 16);
|
||||
end if;
|
||||
dout(23 downto 16) <= sram2(index);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
variable index : natural range 0 to depth-1;
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||
if we(3) = '1' then
|
||||
sram3(index)<= din(31 downto 24);
|
||||
end if;
|
||||
dout(31 downto 24) <= sram3(index);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -1,177 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
ENTITY ram IS
|
||||
Generic
|
||||
(
|
||||
word_addr_width : integer := 6
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
we : in unsigned(3 downto 0);
|
||||
addr : in unsigned(31 downto 0);
|
||||
din : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END ram;
|
||||
|
||||
ARCHITECTURE behavior OF ram IS
|
||||
|
||||
COMPONENT dpram_2w2r
|
||||
Generic
|
||||
(
|
||||
addr_width : integer;
|
||||
data_width : integer
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal jtag_clk : STD_LOGIC;
|
||||
signal jtag_we : unsigned(3 downto 0);
|
||||
signal jtag_addr : unsigned (15 downto 0);
|
||||
signal jtag_dout : unsigned (31 downto 0);
|
||||
signal jtag_din : unsigned (31 downto 0);
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (47 downto 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
gen_sram:
|
||||
for i in 0 to 3 generate
|
||||
begin
|
||||
inst_dpram_2w2r : dpram_2w2r
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => word_addr_width,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
en_a => ce,
|
||||
we_a => we(i),
|
||||
addr_a => addr(word_addr_width+1 downto 2),
|
||||
din_a => din((i+1)*8-1 downto i*8),
|
||||
dout_a => dout((i+1)*8-1 downto i*8),
|
||||
|
||||
clk_b => jtag_clk,
|
||||
en_b => jtag_we(i),
|
||||
we_b => jtag_we(i),
|
||||
addr_b => jtag_addr(word_addr_width-1 downto 0),
|
||||
din_b => jtag_din((i+1)*8-1 downto i*8),
|
||||
dout_b => jtag_dout((i+1)*8-1 downto i*8)
|
||||
);
|
||||
end generate;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_addr <= user_regi(user_regi'left downto jtag_dout'length);
|
||||
jtag_din <= user_regi(jtag_dout'length-1 downto 0);
|
||||
jtag_clk <= bs_update1;
|
||||
jtag_we <= (3 downto 0 => bs_sel);
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -1,88 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY ram IS
|
||||
Generic
|
||||
(
|
||||
word_addr_width : integer := 6
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
we : in unsigned(3 downto 0);
|
||||
addr : in unsigned(31 downto 0);
|
||||
din : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END ram;
|
||||
|
||||
ARCHITECTURE behavior OF ram IS
|
||||
|
||||
constant depth : natural := 2**word_addr_width;
|
||||
|
||||
type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
|
||||
|
||||
function sram_clear return sram_t is
|
||||
|
||||
variable result : sram_t;
|
||||
begin
|
||||
for i in 0 to sram_t'length-1 loop
|
||||
result(i) := (others => '0');
|
||||
end loop;
|
||||
return result;
|
||||
end sram_clear;
|
||||
|
||||
signal sram : sram_t := sram_clear;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
SRAM_RW:
|
||||
process(clk)
|
||||
variable index : natural range 0 to depth-1;
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||
if we(0) = '1' then
|
||||
sram(index)(7 downto 0) <= din(7 downto 0);
|
||||
end if;
|
||||
if we(1) = '1' then
|
||||
sram(index)(15 downto 8) <= din(15 downto 8);
|
||||
end if;
|
||||
if we(2) = '1' then
|
||||
sram(index)(23 downto 16) <= din(23 downto 16);
|
||||
end if;
|
||||
if we(3) = '1' then
|
||||
sram(index)(31 downto 24) <= din(31 downto 24);
|
||||
end if;
|
||||
dout <= sram(index);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,82 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: Testbench for JCPU
|
||||
-- also writes 'opc.lst' for JASM-assembler
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
|
||||
ENTITY tb_mips_embedded IS
|
||||
END tb_mips_embedded;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mips_embedded IS
|
||||
|
||||
COMPONENT mips_embedded
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
halt : in STD_LOGIC;
|
||||
dout : out word_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '1';
|
||||
signal halt : std_logic := '0';
|
||||
signal dout : word_t;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: mips_embedded
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
halt => halt,
|
||||
dout => dout
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
rst <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -1,123 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: Testbench for JCPU
|
||||
-- also writes 'opc.lst' for JASM-assembler
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY tb_mips_embedded_syn IS
|
||||
END tb_mips_embedded_syn;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mips_embedded_syn IS
|
||||
|
||||
COMPONENT mips_embedded_syn
|
||||
Port
|
||||
(
|
||||
sys_rst_n_in : in STD_LOGIC;
|
||||
sys_clk_in : in STD_LOGIC;
|
||||
sys_dip : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
sys_btn : in STD_LOGIC_VECTOR (8 downto 0);
|
||||
sys_led : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
sys_rx : in STD_LOGIC;
|
||||
sys_tx : out STD_LOGIC;
|
||||
sys_error : out STD_LOGIC_VECTOR (1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant CLK_PERIOD : time := 10.0 ns;
|
||||
|
||||
signal sys_rst_n_in : std_logic := '0';
|
||||
signal sys_clk_in : std_logic := '1';
|
||||
signal sys_led : STD_LOGIC_VECTOR (7 downto 0);
|
||||
signal sys_btn : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
|
||||
signal sys_dip : STD_LOGIC_VECTOR (7 downto 0) := "10001001";
|
||||
signal sys_error : STD_LOGIC_VECTOR (1 downto 0);
|
||||
signal sys_rx : std_logic := '1';
|
||||
signal sys_tx : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: mips_embedded_syn
|
||||
PORT MAP
|
||||
(
|
||||
sys_rst_n_in => sys_rst_n_in,
|
||||
sys_clk_in => sys_clk_in,
|
||||
sys_btn => sys_btn,
|
||||
sys_dip => sys_dip,
|
||||
sys_led => sys_led,
|
||||
sys_rx => sys_rx,
|
||||
sys_tx => sys_tx,
|
||||
sys_error => sys_error
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
sys_clk_in <= not sys_clk_in;
|
||||
end process;
|
||||
|
||||
STIMULUS1: process
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(sys_clk_in);
|
||||
sys_rst_n_in <= '1';
|
||||
|
||||
|
||||
|
||||
-- wait for 9994999*CLK_PERIOD;
|
||||
-- for i in 1 to 10000 loop
|
||||
-- wait for 100*CLK_PERIOD;
|
||||
-- sys_btn(3) <= '1';
|
||||
-- wait for 10*CLK_PERIOD;
|
||||
-- sys_btn(3) <= '0';
|
||||
-- end loop;
|
||||
|
||||
wait until rising_edge(sys_clk_in) and now = 38980 ns;
|
||||
sys_btn <= "000001000";
|
||||
wait until rising_edge(sys_clk_in);
|
||||
sys_btn <= "000000000";
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
STIMULUS2: process
|
||||
begin
|
||||
|
||||
|
||||
wait for 9999999*CLK_PERIOD;
|
||||
for i in 1 to 10000 loop
|
||||
wait for 137*CLK_PERIOD;
|
||||
sys_btn(4) <= '1';
|
||||
wait for 21*CLK_PERIOD;
|
||||
sys_btn(4) <= '0';
|
||||
end loop;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user