jens 08e85b7e8f - modified input rdy logic to avoid multi cycle ready after idle ...

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git-svn-id: http://moon:8086/svn/vhdl/trunk@826 cc03376c-175c-47c8-b038-4cd826a8556b

2010-03-25 21:34:10 +00:00

Common

- Intital revision

2008-10-26 23:52:49 +00:00

lib

- modified input rdy logic to avoid multi cycle ready after idle

2010-03-25 21:34:10 +00:00

projects/mips_sys

- made GPIO 0 bidirectional (added GPIO_DIR register)

2010-03-13 16:46:21 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%