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- Added VGA component

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git-svn-id: http://moon:8086/svn/vhdl/trunk@61 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-15 21:55:34 +00:00
parent f960a13953
commit 225e0d5eeb
1 changed files with 103 additions and 11 deletions
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projects/mips_sys/src/mips_sys.vhd
+103 -11
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@@ -35,6 +35,7 @@ use work.mips_types.all;
--use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
use work.vga_types.all;
use work.sys_types.all;
@@ -81,14 +82,14 @@ PORT
sys_sdr_clk_fb : in std_logic;
-- VGA
-- sys_vga_red : out unsigned(7 downto 0);
-- sys_vga_green : out unsigned(7 downto 0);
-- sys_vga_blue : out unsigned(7 downto 0);
-- sys_vga_blank_n : out std_logic;
-- sys_vga_sync_n : out std_logic;
-- sys_vga_hsync : out std_logic;
-- sys_vga_vsync : out std_logic;
-- sys_vga_clk : out std_logic;
sys_vga_clk : out std_logic;
sys_vga_red : out unsigned(7 downto 0);
sys_vga_green : out unsigned(7 downto 0);
sys_vga_blue : out unsigned(7 downto 0);
sys_vga_blank_n : out std_logic;
sys_vga_sync_n : out std_logic;
sys_vga_hsync : out std_logic;
sys_vga_vsync : out std_logic;
sys_usb_d : inout unsigned(15 downto 0);
sys_usb_a : out unsigned(1 downto 0);
@@ -259,6 +260,46 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
COMPONENT vga_frontend
GENERIC
(
sys_freq : integer;
fifo_depth : integer;
fifo_almost_full_thresh : natural;
fifo_almost_empty_thresh : natural;
tsvga : vga_timespec_t
);
PORT
(
-- System signals
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
-- JBUS Slave signals
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
-- JBUS common signals
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_out : out std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
vga_blank_n : out std_logic;
vga_sync_n : out std_logic;
vga_hsync : out std_logic;
vga_vsync : out std_logic
);
END COMPONENT;
signal rst : std_logic;
signal clk : std_logic;
signal clk270 : std_logic;
@@ -322,6 +363,11 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_I_uart : std_logic;
signal DAT_I_uart : unsigned(31 downto 0);
signal CYC_O_vga : std_logic;
signal ACK_I_vga : std_logic;
signal SRDY_I_vga : std_logic;
signal DAT_I_vga : unsigned(31 downto 0);
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0);
@@ -338,7 +384,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram);
type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
signal mem_area : mem_area_t;
BEGIN
@@ -377,6 +423,8 @@ mem_mux:
mem_area <= mem_uart;
elsif ADDR_O(17 downto 16) = "10" then
mem_area <= mem_usb;
elsif ADDR_O(17 downto 16) = "11" then
mem_area <= mem_vga;
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
@@ -399,6 +447,7 @@ signal_mux:
CYC_O_rom <= '0';
CYC_O_ram <= '0';
CYC_O_sdram <= '0';
CYC_O_vga <= '0';
case mem_area is
@@ -426,6 +475,9 @@ signal_mux:
when mem_sdram =>
CYC_O_sdram <= CYC_O;
when mem_vga =>
CYC_O_vga <= CYC_O;
when others => null;
end case;
@@ -447,8 +499,8 @@ urom_ack_register:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_I_flash or SRDY_I_usb or SRDY_I_sdram or SRDY_I_ram or SRDY_I_rom or SRDY_I_urom or SRDY_I_uart or SRDY_I_gpio;
ACK_I <= ACK_I_flash or ACK_I_usb or ACK_I_sdram or ACK_I_ram or ACK_I_rom or ACK_I_urom or ACK_I_uart or ACK_I_gpio;
SRDY_I <= SRDY_I_flash or SRDY_I_usb or SRDY_I_sdram or SRDY_I_ram or SRDY_I_rom or SRDY_I_urom or SRDY_I_uart or SRDY_I_gpio or SRDY_I_vga;
ACK_I <= ACK_I_flash or ACK_I_usb or ACK_I_sdram or ACK_I_ram or ACK_I_rom or ACK_I_urom or ACK_I_uart or ACK_I_gpio or ACK_I_vga;
DAT_I <= DAT_I_sdram when CYC_O_sdram = '1' else
DAT_I_ram when CYC_O_ram = '1' else
DAT_I_rom when CYC_O_rom = '1' else
@@ -456,6 +508,7 @@ urom_ack_register:
DAT_I_flash when CYC_O_flash = '1' else
DAT_I_usb when CYC_O_usb = '1' else
DAT_I_uart when CYC_O_uart = '1' else
DAT_I_vga when CYC_O_vga = '1' else
DAT_I_gpio when CYC_O_gpio = '1' else X"DEADBEEF";
------------------------------------------------------------------
@@ -686,5 +739,44 @@ inst_clockgen : entity work.clockgen
error_out => open
);
inst_vga_frontend : vga_frontend
GENERIC MAP
(
sys_freq => 100E6,
fifo_depth => 2048,
fifo_almost_full_thresh => 2000,
fifo_almost_empty_thresh => 48,
tsvga => ts_vga_800_600_72
)
PORT MAP
(
-- System signals
RST_I => rst,
CLK_I => clk,
-- JBUS Slave signals
CYC_I => CYC_O_vga,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_I_vga,
SRDY_O => SRDY_I_vga,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
-- JBUS common signals
DAT_I => DAT_O,
DAT_O => DAT_I_vga,
-- VGA signals
vga_clk_out => sys_vga_clk,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,
vga_blank_n => sys_vga_blank_n,
vga_sync_n => sys_vga_sync_n,
vga_hsync => sys_vga_hsync,
vga_vsync => sys_vga_vsync
);
------------------------------------------------------------------
END;