- added RAM-based architecture
git-svn-id: http://moon:8086/svn/vhdl/trunk@207 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -40,6 +40,7 @@ Generic
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);
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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ce : in std_logic;
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shift_en : in std_logic;
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@@ -49,7 +50,7 @@ Port
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);
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end delay_line;
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architecture Behavioral of delay_line is
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architecture reg_based of delay_line is
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-------------------------------------------------------------------------------
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subtype word_t is sfixed(shi(nbits, nbits_frac) downto slo(nbits, nbits_frac));
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@@ -79,4 +80,65 @@ shift_register:
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-- Finished instantiation
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----------------------------------------
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end Behavioral;
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end reg_based;
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architecture ram_based of delay_line is
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-------------------------------------------------------------------------------
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signal count : natural range 0 to ntaps-1;
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signal addr_w : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
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signal addr_r : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
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signal ram_w : unsigned(nbits-1 downto 0);
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signal ram_r : unsigned(nbits-1 downto 0);
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-------------------------------------------------------------------------------
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begin
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addr_w <= to_unsigned(count, addr_w'length);
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addr_r <= addr_w + not to_unsigned(delay, addr_w'length);
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ram_w <= unsigned(din);
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dout <= sfixed(ram_r);
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counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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count <= 0;
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elsif ce = '1' then
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if shift_en = '1' then
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if count /= ntaps-1 then
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count <= count + 1;
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else
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count <= 0;
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end if;
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end if;
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end if;
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end if;
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end process;
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inst_dpram_1w1r: entity work.dpram_1w1r
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GENERIC MAP
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(
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addr_width => NextExpBaseTwo(ntaps),
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data_width => nbits
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)
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PORT MAP (
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clka => clk,
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clkb => clk,
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en_a => ce,
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en_b => ce,
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we_a => shift_en,
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addr_a => addr_w,
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addr_b => addr_r,
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din_a => ram_w,
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dout_b => ram_r
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);
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----------------------------------------
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-- Finished instantiation
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----------------------------------------
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end ram_based;
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