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- added force TX-interrupt register bit (0x200)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@530 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-18 18:46:06 +00:00
parent 65404dbba8
commit ddeccf3a34
1 changed files with 6 additions and 1 deletions
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lib/uart/uart_wb.vhd
+6 -1
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@@ -78,6 +78,7 @@ ARCHITECTURE behavior OF uart_wb IS
signal tx_complete : std_logic;
signal tx_empty : std_logic;
signal tx_busy : std_logic;
signal force_irq_tx : std_logic;
begin
@@ -90,6 +91,7 @@ registers_write:
if rising_edge(CLK_I) then
reg_we_uart_tx <= '0';
irq_tx_ack <= '0';
force_irq_tx <= '0';
if RST_I = '1' then
reg_uart_baud <= to_unsigned(53, 16);
rx_int_en <= '0';
@@ -105,6 +107,7 @@ registers_write:
rx_int_en <= DAT_I(6);
tx_int_en <= DAT_I(5);
irq_tx_ack <= DAT_I(8);
force_irq_tx <= DAT_I(9);
when "0010" =>
reg_uart_baud <= DAT_I(15 downto 0);
@@ -168,7 +171,9 @@ tx_interrupt:
elsif irq_tx_ack = '1' then
irq_tx <= '0';
else
if tx_empty = '0' then
if force_irq_tx = '1' then
irq_tx <= tx_int_en;
elsif tx_empty = '0' then
tx_busy <= '1';
elsif tx_busy = '1' then
irq_tx <= tx_int_en;