- removed reference to fifo_sync_dist.

Use fifo_sync instead and specified ditributed ram_style
  in XCF-file during synthesis

Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
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git-svn-id: http://moon:8086/svn/vhdl/trunk@472 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/core/mips_bui.vhd

@@ -285,7 +285,7 @@ inst_dcache : dcache
 	dcache_en		<= cpu_dmem_en; -- and not (CYC_O_dmem_rd or write_busy);-- and not busy;
 	
 -- Instantiate synchronous FIFO
-inst_bout_fifo: entity work.fifo_sync_dist
+inst_bout_fifo: entity work.fifo_sync
 	GENERIC MAP
 	(
 		addr_width	=> 4,
@@ -322,7 +322,7 @@ inst_bout_fifo: entity work.fifo_sync_dist
 	bout_fifo_we_in		<= '1' when dmem_mem_wr_gnt = '1' else '0';
 
 -- Instantiate synchronous FIFO
-inst_write_fifo: entity work.fifo_sync_dist
+inst_write_fifo: entity work.fifo_sync
 	GENERIC MAP
 	(
 		addr_width			=> 4,

lib/CPUs/MIPS/syn/ise101/mips_top.prj

@@ -1,20 +1,18 @@
-vhdl work "../../src/core/mips_types.vhd"
 vhdl work "../../../../misc/dpram_2w2r.vhd"
-vhdl work "../../../../misc/dpram_1w1r_dist.vhd"
 vhdl work "../../../../misc/dpram_1w1r.vhd"
 vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
 vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../src/core/mips_instr.vhd"
-vhdl work "../../../../FIFO/src/fifo_sync_dist.vhd"
+vhdl work "../../src/core/mips_types.vhd"
+vhdl work "../../../../FIFO/src/fifo_sync.vhd"
 vhdl work "../../src/core/mips_shifter.vhd"
 vhdl work "../../src/core/mips_reg.vhd"
 vhdl work "../../src/core/mips_muldiv.vhd"
-vhdl work "../../src/core/mips_idecode_rom.vhd"
+vhdl work "../../src/core/mips_instr.vhd"
 vhdl work "../../src/core/mips_icache.vhd"
 vhdl work "../../src/core/mips_dcache.vhd"
-vhdl work "../../src/core/mips_cop.vhd"
 vhdl work "../../src/core/mips_bcu.vhd"
 vhdl work "../../src/core/mips_alu.vhd"
 vhdl work "../../src/core/mips_pipeline.vhd"
+vhdl work "../../src/core/mips_cop.vhd"
 vhdl work "../../src/core/mips_biu.vhd"
 vhdl work "../../src/core/mips_top.vhd"

lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj

@@ -1,20 +1,18 @@
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"