jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- new revision 10

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@313 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-06 10:17:45 +00:00
parent 9e43596a76
commit ec84f598aa
3 changed files with 27 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/dist/mdist
Vendored
+1 -1
View File
@@ -2,7 +2,7 @@
PROJECT="mips_top"
DIST_FILE="./files.dist"
DIST_DIR="./release/mips.r9"
DIST_DIR="./release/mips.r10"
# ---------------------------------------------------------------
mkdir -p $DIST_DIR/src
lib/CPUs/MIPS/doc/J-MIPS.txt
+25 -2
View File
@@ -13,7 +13,7 @@ J-MIPS Features
- Direct-mapped Instruction Cache mit variabler Größe, 8-words per Line
- Direct-mapped Data Cache mit variabler Größe, 8-words per Line
- J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen)
- 1,15 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3)
- 1,2 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3)
-----------------------------------------------------------------
Known Limitations
@@ -22,6 +22,9 @@ Known Limitations
- z.Zt. nur Little-endian.
- keine Unterstützung für Bus exceptions IBE und DBE
- kein externes Coprocessor interface (COP1..3) für z.B. FPU
- Befehle für Cop1..3 nicht implementiert:
CFCz, CTCz, COPz, MFCz, MTCz, LWCz, SWCz
Benutzung dieser Befehle führt zur Exception 'RI' (Reserved Instruction)
- nicht alle COP0 Register/Bits vorhanden.
-----------------------------------------------------------------
@@ -44,7 +47,7 @@ Known Optimizations
Known ToDos
-----------------------------------------------------------------
- Unterstützung für Bus exceptions IBE und DBE
- Externes COP1..3 interface
- Externes COP1..3 interface, fehlende COP-Befehle implementieren
- Optimierungen evaluieren und ggf. durchführen
-----------------------------------------------------------------
@@ -75,6 +78,8 @@ Speed: 30MHz nach Synthesis
-----------------------------------------------------------------
Performance bei 100MHz
- GCC ohne Small-data section
- MIPS Rev. 9
-----------------------------------------------------------------
I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12)
1k 32 DMIPS 5 Mbit/s 345 kwhets/s 47/767 2,135s
@@ -84,3 +89,21 @@ I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12)
16k 115 DMIPS 17 Mbit/s 1234 kwhets/s 23/225 1,938s
32k 115 DMIPS 17 Mbit/s 1285 kwhets/s 24/218 1,938s
64k 115 DMIPS 17 Mbit/s 1285 kwhets/s 20/221 1,938s
-----------------------------------------------------------------
Performance bei 100MHz
- GCC mit Small-data section
- MIPS Rev. 9
-----------------------------------------------------------------
I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12)
16k 117 DMIPS 17 Mbit/s 1236 kwhets/s 24/230 1,811s
-----------------------------------------------------------------
Performance bei 100MHz
- GCC mit Small-data section
- MIPS Rev. 10
-----------------------------------------------------------------
I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12)
16k 120 DMIPS 17 Mbit/s 1242 kwhets/s 25/219 1,803s
lib/CPUs/MIPS/src/core/mips_types.vhd
+1 -1
View File
@@ -30,7 +30,7 @@ use IEEE.numeric_std.ALL;
package mips_types is
-- Revision of the CPU
constant REVISION : integer := 9;
constant REVISION : integer := 10;
constant WORD_WIDTH : integer := 32;
--Types