jens 4c309f1eef - SR(7 .. 0) are not writable in user-mode ...

- registered 'ctrl_out.int' for better timing
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git-svn-id: http://moon:8086/svn/vhdl/trunk@458 cc03376c-175c-47c8-b038-4cd826a8556b

2009-04-27 08:23:08 +00:00

Common

- Intital revision

2008-10-26 23:52:49 +00:00

lib

- SR(7 .. 0) are not writable in user-mode

2009-04-27 08:23:08 +00:00

projects/mips_sys

- added port 'eb' for Endian-big selection

2009-04-15 13:23:30 +00:00

S

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23 MiB

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VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%