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- made time specs in nano seconds, thus independent of clock

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git-svn-id: http://moon:8086/svn/vhdl/trunk@784 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-13 11:06:43 +00:00
parent ce9ff6339d
commit 0a601d2dd2
1 changed files with 10 additions and 9 deletions
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lib/misc/flash_port_wb.vhd
+10 -9
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@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.1 2010-03-13 11:03:12 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010-03-13 11:06:43 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -10,6 +10,7 @@ use work.async_types.all;
entity flash_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
@@ -105,7 +106,7 @@ architecture Behavioral of flash_port_wb is
process(s, cycle_cnt, en, we_reg, port_bsyi)
begin
cycle_reload <= async_timespec.ncyc_pulse_rst;
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
@@ -138,7 +139,7 @@ architecture Behavioral of flash_port_wb is
if port_bsyi = '0' then
as.cs <= '1';
cc_rst <= '1';
cycle_reload <= async_timespec.ncyc_leadin;
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
if we_reg = '0' then
sn <= leadin_rd;
else
@@ -149,7 +150,7 @@ architecture Behavioral of flash_port_wb is
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= async_timespec.ncyc_pulse_rd-1;
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
as.rd <= '1';
sn <= read;
end if;
@@ -158,7 +159,7 @@ architecture Behavioral of flash_port_wb is
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= async_timespec.ncyc_pulse_wr-1;
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
as.wr <= '1';
as.drive_d <= '1';
sn <= write;
@@ -169,7 +170,7 @@ architecture Behavioral of flash_port_wb is
as.rd <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= async_timespec.ncyc_leadout-1;
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
-- as.rd <= '0';
sn <= leadout_rd;
ack <= '1';
@@ -182,7 +183,7 @@ architecture Behavioral of flash_port_wb is
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
cycle_reload <= async_timespec.ncyc_leadout-1;
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
sn <= leadout_wr;
-- ack <= '1';
end if;
@@ -191,7 +192,7 @@ architecture Behavioral of flash_port_wb is
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= async_timespec.ncyc_release-1;
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
@@ -201,7 +202,7 @@ architecture Behavioral of flash_port_wb is
as.drive_d <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= async_timespec.ncyc_release-1;
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;