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- added dedicated sys_clk_out frequency synthesis

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- SDRAM clocks use sys_clk_out for clock generation
- added cpu_clk_out which is the same as sys_clk_in

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git-svn-id: http://moon:8086/svn/vhdl/trunk@727 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 19:16:11 +00:00
parent c42c0ba5b8
commit 023b7e42a3
5 changed files with 251 additions and 175 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
+4
View File
@@ -31,6 +31,10 @@ NET "vga_clk" TNM_NET = "vga_clk";
TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %;
TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
NET "cpu_clk" TNM_NET = "cpu_clk";
TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
TIMESPEC "TS_unrelate_CPU" = FROM sys_clk TO cpu_clk TIG;
NET "sys_clk_in" LOC = "AE14";
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET "sys_rst_n_in" LOC = "D6";
projects/mips_sys/src/clockgen_virtex4.vhd
+193 -140
View File
@@ -34,89 +34,61 @@ entity clockgen is
generic
(
clk_in_freq_hz : integer := 100E6;
vga_clk_out_freq_hz : integer := 0;
sdr_clk0_out_phaseshift : integer := 0;
sdr_clk1_out_phaseshift : integer := 0
vga_clk_out_freq_hz : integer := 100E6;
sys_clk_out_freq_hz : integer := 100E6;
sdr0_clk_out_phaseshift : integer := 0;
sdr1_clk_out_phaseshift : integer := 0
);
port
(
-- Clocks and Reset
rst : in std_logic; -- external async reset, low active
rst_in : in std_logic; -- external async reset, low active
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
sys_clk_out : out std_logic;
cpu_clk_out : out std_logic;
vga_clk_out : out std_logic;
sdr_clk0_fb_in : in std_logic; -- feedback clock
sdr_clk0_0_out : out std_logic; -- System clock #0, dcm#0 output 0°
sdr_clk0_270_out : out std_logic; -- System clock #0, dcm#0 output 270°
sdr_clk1_0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr_clk1_270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out : out std_logic; -- DCM locked status
error_out : out std_logic -- indicates DCM Errors
sdr0_clk_fb_in : in std_logic; -- feedback clock
sdr0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0°
sdr0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270°
sdr1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys_rst_out : out std_logic -- DCM locked status
);
end;
architecture tech of clockgen is
signal locked : unsigned(2 downto 0);
signal dcm_rst : unsigned(2 downto 0);
signal dcm0_clk0 : std_logic;
signal dcm0_clk0_bufg : std_logic;
signal dcm0_clkfx : std_logic;
signal dcm1_clk0 : std_logic;
signal dcm1_clk270 : std_logic;
signal dcm1_clk0_bufg : std_logic;
signal dcm1_clk270_bufg : std_logic;
signal dcm2_clk0 : std_logic;
signal dcm2_clk270 : std_logic;
signal dcm2_clk0_bufg : std_logic;
signal dcm2_clk270_bufg : std_logic;
signal dcm0_locked : unsigned(2 downto 0);
signal dcm1_locked : unsigned(2 downto 0);
signal dcm2_locked : unsigned(2 downto 0);
signal cnt_q : unsigned(4 downto 0);
signal vga_clk0 : std_logic;
signal vga_clkfx : std_logic;
signal vga_clk0_bufg : std_logic;
signal sys_clk0 : std_logic;
signal sys_clkfx : std_logic;
signal sys_clk0_bufg : std_logic;
signal sys_clkfx_bufg : std_logic;
signal sdr0_clk0 : std_logic;
signal sdr0_clk270 : std_logic;
signal sdr1_clk0 : std_logic;
signal sdr1_clk270 : std_logic;
signal sdr1_clk0_bufg : std_logic;
signal reset_cnt : unsigned(4 downto 0);
signal reset_pipe0 : unsigned(19 downto 0);
signal reset_pipe1 : unsigned(19 downto 0);
signal reset_pipe2 : unsigned(19 downto 0);
signal vga_fx_lock : std_logic;
signal sys_fx_lock : std_logic;
signal sdr0_lock : std_logic;
signal sdr1_lock : std_logic;
type STATE_TYPE is (s0, s1, s2, s3, s4);
signal state_q : STATE_TYPE;
begin
sdr_clk0_0_out <= dcm1_clk0_bufg;
sdr_clk0_270_out <= dcm1_clk270_bufg;
sdr_clk1_0_out <= dcm2_clk0_bufg;
sdr_clk1_270_out <= dcm2_clk270_bufg;
bufg11: bufg
port map
(
o => dcm1_clk0_bufg,
i => dcm1_clk0
);
bufg12: bufg
port map (
o => dcm1_clk270_bufg,
i => dcm1_clk270
);
bufg13: bufg
port map
(
o => dcm2_clk0_bufg,
i => dcm2_clk0
);
bufg14: bufg
port map (
o => dcm2_clk270_bufg,
i => dcm2_clk270
);
-------------------------------------------------------------------------------------------------------
-- Clock generation
-------------------------------------------------------------------------------------------------------
-- Compnent instantiation
inst_DCM_BASE_0 : DCM_BASE
inst_DCM_VGA_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
@@ -128,7 +100,7 @@ bufg14: bufg
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
@@ -139,38 +111,92 @@ bufg14: bufg
)
port map
(
CLK0 => dcm0_clk0, -- 0 degree DCM CLK ouptput
CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcm0_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => locked(0), -- DCM LOCK status output
CLKFB => dcm0_clk0_bufg, -- DCM clock feedback
LOCKED => vga_fx_lock, -- DCM LOCK status output
CLKFB => vga_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(0) -- DCM asynchronous reset input
);
BUFG_dcm_clk_fb : BUFG
BUFG_vga_clk0 : BUFG
port map
(
O => dcm0_clk0_bufg, -- Clock buffer output
I => dcm0_clk0 -- Clock buffer input
O => vga_clk0_bufg, -- Clock buffer output
I => vga_clk0 -- Clock buffer input
);
BUFG_clk_out : BUFG
BUFG_vga_clkfx : BUFG
port map
(
O => vga_clk_out, -- Clock buffer output
I => dcm0_clkfx -- Clock buffer input
I => vga_clkfx -- Clock buffer input
);
sys_clk_out <= dcm0_clk0_bufg;
inst_DCM_BASE_1 : DCM_BASE
-- Compnent instantiation
inst_DCM_SYS_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, sys_clk_out_freq_hz), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, sys_clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => sys_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sys_fx_lock, -- DCM LOCK status output
CLKFB => sys_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(0) -- DCM asynchronous reset input
);
BUFG_sys_clk0 : BUFG
port map
(
O => sys_clk0_bufg, -- Clock buffer output
I => sys_clk0 -- Clock buffer input
);
BUFG_sys_clkfx : BUFG
port map
(
O => sys_clkfx_bufg, -- Clock buffer output
I => sys_clkfx -- Clock buffer input
);
cpu_clk_out <= sys_clk0_bufg;
sys_clk_out <= sys_clkfx_bufg;
inst_DCM_SDRCLK_0 : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
@@ -178,7 +204,7 @@ inst_DCM_BASE_1 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -189,29 +215,40 @@ inst_DCM_BASE_1 : DCM_BASE
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => sdr_clk0_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
PHASE_SHIFT => sdr0_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => dcm1_clk0, -- 0 degree DCM CLK ouptput
CLK0 => sdr0_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => dcm1_clk270, -- 270 degree DCM CLK output
CLK270 => sdr0_clk270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => locked(1), -- DCM LOCK status output
CLKFB => sdr_clk0_fb_in, -- DCM clock feedback
CLKIN => dcm0_clk0_bufg, -- Clock input (from IBUFG, BUFG or DCM)
LOCKED => sdr0_lock, -- DCM LOCK status output
CLKFB => sdr0_clk_fb_in, -- DCM clock feedback
CLKIN => sys_clkfx_bufg, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(1) -- DCM asynchronous reset input
);
dcm_rst(1) <= not locked(0);
inst_DCM_BASE_2 : DCM_BASE
bufg_sdr0_clk0: bufg
port map
(
o => sdr0_clk0_out,
i => sdr0_clk0
);
bufg_sdr0_clk270: bufg
port map (
o => sdr0_clk270_out,
i => sdr0_clk270
);
inst_DCM_SDRCLK_1 : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
@@ -219,7 +256,7 @@ inst_DCM_BASE_1 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -230,79 +267,95 @@ inst_DCM_BASE_1 : DCM_BASE
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => sdr_clk1_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
PHASE_SHIFT => sdr1_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => dcm2_clk0, -- 0 degree DCM CLK ouptput
CLK0 => sdr1_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => dcm2_clk270, -- 270 degree DCM CLK output
CLK270 => sdr1_clk270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => locked(2), -- DCM LOCK status output
CLKFB => dcm2_clk0_bufg, -- DCM clock feedback
CLKIN => sdr_clk0_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
LOCKED => sdr1_lock, -- DCM LOCK status output
CLKFB => sdr1_clk0_bufg, -- DCM clock feedback
CLKIN => sdr0_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(2) -- DCM asynchronous reset input
);
dcm_rst(2) <= not locked(1);
sdr1_clk0_out <= sdr1_clk0_bufg;
bufg_sdr1_clk0: bufg
port map
(
o => sdr1_clk0_bufg,
i => sdr1_clk0
);
dcm_fsm:
process(rst, clk_in)
bufg_sdr1_clk270: bufg
port map (
o => sdr1_clk270_out,
i => sdr1_clk270
);
dcm_rst(0) <= reset_pipe0(reset_pipe0'left);
dcm_reset0:
process(rst_in, clk_in)
begin
if rst = '1' then
state_q <= s0;
dcm_rst(0) <= '0';
cnt_q <= "11111";
error_out <= '0';
locked_out <= '0';
dcm0_locked <= (others => '0');
dcm1_locked <= (others => '0');
dcm2_locked <= (others => '0');
if rst_in = '1' then
reset_pipe0 <= (others => '1');
elsif rising_edge(clk_in) then
case state_q is
when s0 =>
state_q <= s1;
when s1 =>
cnt_q <= cnt_q - 1;
if cnt_q = 0 then
dcm_rst(0) <= '1';
state_q <= s2;
end if;
when s2 =>
cnt_q <= cnt_q - 1;
if cnt_q = 0 then
dcm_rst(0) <= '0';
state_q <= s3;
end if;
when s3 =>
if dcm0_locked(2)='1' and dcm1_locked(2)='1' and dcm2_locked(2)='1' then
state_q <= s4;
error_out <= '0';
end if;
when s4 =>
if dcm0_locked(2)='1' and dcm1_locked(2)='1' and dcm2_locked(2)='1' then
locked_out <= '1';
else
error_out <= '1';
end if;
end case;
-- synchronize 'dcm1_locked'
dcm0_locked <= dcm0_locked(1 downto 0) & locked(0);
dcm1_locked <= dcm1_locked(1 downto 0) & locked(1);
dcm2_locked <= dcm2_locked(1 downto 0) & locked(2);
reset_pipe0 <= reset_pipe0(reset_pipe0'left-1 downto 0) & '0';
end if;
end process;
dcm_rst(1) <= reset_pipe1(reset_pipe1'left);
dcm_reset1:
process(vga_fx_lock, clk_in)
begin
if vga_fx_lock = '0' then
reset_pipe1 <= (others => '1');
elsif rising_edge(clk_in) then
reset_pipe1 <= reset_pipe1(reset_pipe1'left-1 downto 0) & '0';
end if;
end process;
dcm_rst(2) <= reset_pipe2(reset_pipe2'left);
dcm_reset2:
process(sdr0_lock, clk_in)
begin
if sdr0_lock = '0' then
reset_pipe2 <= (others => '1');
elsif rising_edge(clk_in) then
reset_pipe2 <= reset_pipe2(reset_pipe2'left-1 downto 0) & '0';
end if;
end process;
reset_out_logic:
process(rst_in, clk_in)
begin
if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then
sys_rst_out <= '1';
reset_cnt <= (reset_cnt'left downto reset_cnt'right => '1');
elsif rising_edge(clk_in) then
if reset_cnt /= (reset_cnt'left downto reset_cnt'right => '0') then
reset_cnt <= reset_cnt - 1;
else
sys_rst_out <= '0';
end if;
end if;
end process;
end architecture tech;
projects/mips_sys/src/mips_sys.vhd
+26 -16
View File
@@ -42,9 +42,10 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : integer := 100E6;
sys_freq : integer := 100E6;
ddr_phaseshift : integer := 0;
ddr_frequency_hz : integer := 100E6;
ddr_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_60
);
@@ -143,6 +144,7 @@ ARCHITECTURE behavior OF mips_sys IS
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
@@ -193,6 +195,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk_hz : natural := 100E6;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
@@ -320,13 +323,14 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
signal cpu_clk : std_logic;
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal dcm_lock : std_logic;
signal vga_ce : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
@@ -473,6 +477,9 @@ ARCHITECTURE behavior OF mips_sys IS
attribute KEEP : string;
attribute KEEP of vga_clk : signal is "TRUE";
attribute KEEP of sdram_clk0 : signal is "TRUE";
attribute KEEP of cpu_clk : signal is "TRUE";
attribute KEEP of CLK_O : signal is "TRUE";
attribute KEEP of RST_O : signal is "TRUE";
BEGIN
@@ -496,8 +503,6 @@ BEGIN
sys_flash_a <= '0' & flash_addr(24 downto 2) & '0';
flash_page_mode_en <= not mem_mapped_io;
RST_O <= not dcm_lock;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_uart1_tx <= uart1_tx;
sys_uart2_tx <= uart1_tx;
@@ -505,6 +510,7 @@ BEGIN
sys_uart3_tx <= sys_uart3_rx;
sys_vga_clk <= vga_clk;
vga_ce <= not RST_O;
---------------------------------------------------------------
-- Arbiter
@@ -671,6 +677,7 @@ inst_mips_top: mips_top
debug => debug,
eb => eb,
nmi => nmi,
cpu_clk => cpu_clk,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
@@ -741,6 +748,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
addr_width => 25,
data_width => 32,
byte_sel_width => 1,
@@ -773,6 +781,7 @@ inst_flash_port : async_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
addr_width => 4,
data_width => 16,
byte_sel_width => 1,
@@ -846,25 +855,26 @@ inst_uart_wb_1 : uart_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq,
clk_in_freq_hz => sys_freq_in,
sys_clk_out_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
sdr_clk0_out_phaseshift => 0,
sdr_clk1_out_phaseshift => 0
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst => rst_in, -- external async reset, low active
rst_in => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O,
sys_clk_out => CLK_O,
vga_clk_out => vga_clk,
sdr_clk0_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr_clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr_clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr_clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr_clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => dcm_lock, -- DCM locked status
error_out => open
cpu_clk_out => cpu_clk,
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
@@ -952,7 +962,7 @@ inst_vga_frontend : vga_frontend64
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => dcm_lock,
vga_clk_ce => vga_ce,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,
projects/mips_sys/src/mips_sys_sim.vhd
+27 -18
View File
@@ -43,9 +43,10 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq : integer := 100E6;
sys_freq_in : integer := 100E6;
sys_freq : integer := 125E6;
ddr_frequency_hz : integer := 125E6;
ddr_phaseshift : integer := 0;
ddr_frequency_hz : integer := 100E6;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
@@ -149,6 +150,7 @@ ARCHITECTURE behavior OF mips_sys IS
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
@@ -199,6 +201,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk_hz : natural := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
@@ -232,6 +235,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT flash_port_wb
GENERIC
(
f_sysclk_hz : natural := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
@@ -358,13 +362,14 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
signal cpu_clk : std_logic;
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal dcm_lock : std_logic;
signal vga_ce : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
@@ -540,7 +545,7 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
RST_O <= not dcm_lock;
vga_ce <= not RST_O;
sys_flash_ssram_out:
process(CLK_O)
@@ -734,6 +739,7 @@ inst_mips_top: mips_top
debug => debug,
eb => eb,
nmi => nmi,
cpu_clk => cpu_clk,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
@@ -804,6 +810,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : flash_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
addr_width => 25,
data_width => 32,
async_timespec => ts_flash
@@ -836,6 +843,7 @@ inst_flash_port : flash_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
addr_width => 2,
data_width => 16,
byte_sel_width => 1,
@@ -970,25 +978,26 @@ inst_ssram_port_wb : entity work.ssram_port_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq,
clk_in_freq_hz => sys_freq_in,
sys_clk_out_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
sdr_clk0_out_phaseshift => 0,
sdr_clk1_out_phaseshift => 0
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst => rst_in, -- external async reset, low active
rst_in => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O,
sys_clk_out => CLK_O,
vga_clk_out => vga_clk,
sdr_clk0_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr_clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr_clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr_clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr_clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => dcm_lock, -- DCM locked status
error_out => open
cpu_clk_out => cpu_clk,
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
);
@@ -996,8 +1005,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => ddr_frequency_hz,
f_sdrclk_hz => sys_freq,
f_sysclk_hz => sys_freq,
f_sdrclk_hz => ddr_frequency_hz,
fifo_depth => 5
)
PORT MAP
@@ -1076,7 +1085,7 @@ inst_vga_frontend : vga_frontend64
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => dcm_lock,
vga_clk_ce => vga_ce,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,
projects/mips_sys/src/tb_mips_sys.vhd
+1 -1
View File
@@ -254,7 +254,7 @@ i_mt46v16m16_1 : entity work.mt46v16m16
dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
);
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
sys_sdr_clk_fb <= sys_sdr_clk_p after 1300 ps;
sys_ssram_clk_fb <= sys_ssram_clk after 0.5 ns;
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;