Intital revision
git-svn-id: http://moon:8086/svn/vhdl/trunk@41 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,259 @@
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-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.1 2008-10-10 21:25:46 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.sys_types.all;
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------------------------------------------------------------------
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entity async_port_wb is
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Generic
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(
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addr_width : natural := 32;
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data_width : natural := 32;
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async_timespec : async_timespec_t
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);
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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async_a : out unsigned(addr_width-1 downto 0);
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async_d : inout unsigned(data_width-1 downto 0);
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async_cs : out std_logic;
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async_wr : out std_logic;
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async_rd : out std_logic;
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async_rst : out std_logic
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);
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end async_port_wb;
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architecture Behavioral of async_port_wb is
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type async_t is record
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cs : std_logic;
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wr : std_logic;
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rd : std_logic;
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rst : std_logic;
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drive_d : std_logic;
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end record;
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type async_state_t is (start, reset, rdy, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
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signal s, sn : async_state_t;
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signal as : async_t;
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signal ack : std_logic;
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signal cc_rst : std_logic;
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signal cycle_cnt : natural range 0 to 15;
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signal cycle_reload : natural range 0 to 15;
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------------------------------------------------------------------
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begin
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proc_cycle_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if cc_rst = '1' then
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cycle_cnt <= cycle_reload;
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elsif cycle_cnt /= 0 then
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cycle_cnt <= cycle_cnt - 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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proc_state_next:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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s <= start;
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else
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s <= sn;
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end if;
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end if;
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end process;
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proc_state:
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process(s, cycle_cnt, STB_I, CYC_I, WE_I)
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begin
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cycle_reload <= async_timespec.ncyc_pulse_rst;
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cc_rst <= '0';
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as.rst <= '0';
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as.cs <= '0';
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as.wr <= '0';
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as.rd <= '0';
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as.drive_d <= '0';
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SRDY_O <= '0';
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ack <= '0';
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sn <= s;
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case s is
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when start =>
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cc_rst <= '1';
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sn <= reset;
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when reset =>
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as.rst <= '1';
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if cycle_cnt = 0 then
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sn <= rdy;
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end if;
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when rdy =>
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SRDY_O <= CYC_I;
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if (STB_I and CYC_I) = '1' then
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as.cs <= '1';
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_access-1;
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if WE_I = '0' then
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sn <= leadin_rd;
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else
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sn <= leadin_wr;
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end if;
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end if;
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when leadin_rd =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_pulse_rd-1;
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as.rd <= '1';
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sn <= read;
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end if;
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when leadin_wr =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_pulse_wr-1;
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as.wr <= '1';
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as.drive_d <= '1';
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sn <= write;
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end if;
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when read =>
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as.cs <= '1';
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as.rd <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_cs_hold-1;
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-- as.rd <= '0';
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sn <= leadout_rd;
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ack <= '1';
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end if;
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when write =>
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as.drive_d <= '1';
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as.cs <= '1';
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as.wr <= '1';
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if cycle_cnt = 0 then
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as.wr <= '0';
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_cs_hold-1;
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sn <= leadout_wr;
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-- ack <= '1';
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end if;
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when leadout_rd =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_release-1;
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sn <= release;
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as.cs <= '0';
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end if;
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when leadout_wr =>
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as.cs <= '1';
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as.drive_d <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_release-1;
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sn <= release;
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as.cs <= '0';
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end if;
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when release =>
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if cycle_cnt = 0 then
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sn <= rdy;
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end if;
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when others =>
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sn <= rdy;
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end case;
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end process;
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------------------------------------------------------------------
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output_ctrl:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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async_cs <= (not async_timespec.pol_cs) xor as.cs;
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async_wr <= (not async_timespec.pol_we) xor as.wr;
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async_rd <= (not async_timespec.pol_oe) xor as.rd;
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async_rst <= (not async_timespec.pol_rst) xor as.rst;
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end if;
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end process;
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------------------------------------------------------------------
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din_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if as.rd = '1' then
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DAT_O(data_width-1 downto 0) <= async_d;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_addr:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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async_a <= (others => '0');
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elsif (STB_I and CYC_I) = '1' then
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async_a <= ADDR_I(addr_width-1 downto 0);
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_ACK:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ACK_O <= '0';
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else
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ACK_O <= ack;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_data:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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async_d <= (others => 'Z');
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if as.drive_d = '1' then
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async_d <= DAT_I(data_width-1 downto 0);
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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end Behavioral;
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@@ -0,0 +1,236 @@
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-------------------------------------------------------------------------
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-- Project: SDRAM controller
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-- This file: Clock generator (Virtex-4 specific)
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library ieee, work;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity clockgen is
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generic
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(
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sys1_phaseshift : integer := 0;
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frequency_hz : integer := 100E6
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);
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port
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(
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-- Clocks and Reset
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rst : in std_logic; -- external async reset, low active
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clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
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clk_fb_in : in std_logic; -- feedback clock
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sys1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
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sys1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
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sys0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0°
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sys0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270°
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locked_out : out std_logic; -- DCM locked status
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error_out : out std_logic -- indicates DCM Errors
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);
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end;
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architecture tech of clockgen is
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constant CLKIN_PER : real := real(1000E6/frequency_hz);
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signal locked : unsigned(1 downto 0);
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signal dcm_rst : unsigned(1 downto 0);
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signal sys1_clk0 : std_logic;
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signal sys1_clk270 : std_logic;
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signal sys1_clk0_bufg : std_logic;
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signal sys1_clk270_bufg : std_logic;
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signal sys0_clk0 : std_logic;
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signal sys0_clk270 : std_logic;
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signal sys0_clk0_bufg : std_logic;
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signal sys0_clk270_bufg : std_logic;
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signal dcm1_locked, dcm2_locked : unsigned(2 downto 0);
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signal cnt_q : unsigned(4 downto 0);
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type STATE_TYPE is (s0, s1, s2, s3, s4);
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signal state_q : STATE_TYPE;
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begin
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sys1_clk0_out <= sys1_clk0_bufg;
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sys1_clk270_out <= sys1_clk270_bufg;
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sys0_clk0_out <= sys0_clk0_bufg;
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sys0_clk270_out <= sys0_clk270_bufg;
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bufg11: bufg
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port map
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(
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o => sys0_clk0_bufg,
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i => sys0_clk0
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);
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bufg12: bufg
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port map (
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o => sys0_clk270_bufg,
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i => sys0_clk270
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);
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bufg13: bufg
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port map
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(
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o => sys1_clk0_bufg,
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i => sys1_clk0
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);
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bufg14: bufg
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port map (
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o => sys1_clk270_bufg,
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i => sys1_clk270
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);
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-------------------------------------------------------------------------------------------------------
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-- Clock generation
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-------------------------------------------------------------------------------------------------------
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inst_DCM_BASE_0 : DCM_BASE
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generic map (
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
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CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
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CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
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CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
|
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CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
|
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CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
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DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
|
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DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
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DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
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-- an integer from 0 to 15
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DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
port map (
|
||||
CLK0 => sys0_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => sys0_clk270, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => open, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => locked(0), -- DCM LOCK status output
|
||||
CLKFB => clk_fb_in, -- DCM clock feedback
|
||||
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => dcm_rst(0) -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
inst_DCM_BASE_1 : DCM_BASE
|
||||
generic map (
|
||||
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
||||
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
||||
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
|
||||
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
|
||||
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
||||
CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
|
||||
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
|
||||
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
||||
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
|
||||
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
||||
-- an integer from 0 to 15
|
||||
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => sys1_phaseshift, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
port map (
|
||||
CLK0 => sys1_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => sys1_clk270, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => open, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => locked(1), -- DCM LOCK status output
|
||||
CLKFB => sys1_clk0_bufg, -- DCM clock feedback
|
||||
CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => dcm_rst(1) -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
dcm_rst(1) <= not locked(0);
|
||||
|
||||
dcm_fsm:
|
||||
process(rst, clk_in)
|
||||
begin
|
||||
if rst = '1' then
|
||||
state_q <= s0;
|
||||
dcm_rst(0) <= '0';
|
||||
cnt_q <= "11111";
|
||||
error_out <= '0';
|
||||
locked_out <= '0';
|
||||
dcm1_locked <= (others => '0');
|
||||
dcm2_locked <= (others => '0');
|
||||
elsif rising_edge(clk_in) then
|
||||
case state_q is
|
||||
when s0 =>
|
||||
state_q <= s1;
|
||||
|
||||
when s1 =>
|
||||
cnt_q <= cnt_q - 1;
|
||||
if cnt_q = 0 then
|
||||
dcm_rst(0) <= '1';
|
||||
state_q <= s2;
|
||||
end if;
|
||||
|
||||
when s2 =>
|
||||
cnt_q <= cnt_q - 1;
|
||||
if cnt_q = 0 then
|
||||
dcm_rst(0) <= '0';
|
||||
state_q <= s3;
|
||||
end if;
|
||||
|
||||
when s3 =>
|
||||
if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
|
||||
state_q <= s4;
|
||||
error_out <= '0';
|
||||
end if;
|
||||
|
||||
when s4 =>
|
||||
if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
|
||||
locked_out <= '1';
|
||||
else
|
||||
error_out <= '1';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
-- synchronize 'dcm1_locked'
|
||||
dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
|
||||
dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture tech;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user