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git-svn-id: http://moon:8086/svn/vhdl/trunk@99 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-23 22:06:34 +00:00
parent 36e8cd1e00
commit 5c63d629a7
4 changed files with 0 additions and 279 deletions
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lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo
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## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/tb_eval_muldiv.vhd"
vsim -t 1ps -lib work tb_eval_muldiv
do {tb_eval_muldiv.wdo}
view wave
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_eval_muldiv/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0}
configure wave -namecolwidth 149
configure wave -valuecolwidth 171
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {2520 ns}
lib/CPUs/MIPS/src/mips_muldiv.vhd
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--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: The arithmetic logic unit
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.mips_types.all;
entity muldiv is
Port
(
rst : in std_logic;
clk : in std_logic;
din_vld_hi : in std_logic;
din_vld_lo : in std_logic;
din_hi : in word_t;
din_lo : in word_t;
hilo_sel : in std_logic;
dout : out word_t
);
end muldiv;
architecture Behavioral of muldiv is
signal reg_hi, reg_lo : word_t;
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
proc_reg_out:
process(hilo_sel, reg_hi, reg_lo)
begin
if hilo_sel = '1' then
dout <= reg_hi;
else
dout <= reg_lo;
end if;
end process;
proc_reg_in:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_hi <= (others => '0');
reg_lo <= (others => '0');
elsif din_vld_hi = '1' then
if hilo_sel = '1' then
reg_hi <= din_hi;
else
reg_lo <= din_hi;
end if;
end if;
if din_vld_lo = '1' then
reg_lo <= din_lo;
end if;
end if;
end process;
--------------------------------------------------------------------------
end Behavioral;
lib/CPUs/MIPS/src/tb_eval_muldiv.vhd
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-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: Testbench for JCPU
-- also writes 'opc.lst' for JASM-assembler
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.mips_types.all;
use work.mips_instr.all;
ENTITY tb_eval_muldiv IS
END tb_eval_muldiv;
ARCHITECTURE behavior OF tb_eval_muldiv IS
constant CLK_PERIOD : time := 10 ns;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal ce : std_logic := '0';
signal mul_divn : std_logic := '1';
signal op_valid : std_logic := '0';
signal op1_in : word_t := (others => '-');
signal op2_in : word_t := (others => '-');
signal result : unsigned (2*word_t'length-1 downto 0);
signal res_valid : std_logic;
signal busy : std_logic;
signal result_reg : unsigned (2*word_t'length-1 downto 0);
subtype pp_t is unsigned (39 downto 0);
signal pp0, pp1, pp2, pp3 : pp_t;
signal signed_mul : std_logic := '1';
signal sign1 : std_logic;
signal sign2 : std_logic;
signal cy : std_logic;
BEGIN
sign1 <= signed_mul and op1_in(op1_in'left);
sign2 <= signed_mul and op2_in(op1_in'left);
cy <= sign1;
pp0 <= op1_in * op2_in(7 downto 0);
pp1 <= op1_in * op2_in(15 downto 8);
pp2 <= op1_in * op2_in(23 downto 16);
pp3 <= op1_in * op2_in(31 downto 24);
result <= ((63 downto 40 => '0') & pp0)
+ ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0'))
+ ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0'))
+ (pp3 & (23 downto 0 => '0'));
result_reg <= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000"));
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
rst <= '0';
wait for 10*CLK_PERIOD;
wait until rising_edge(clk);
ce <= '1';
wait for 10*CLK_PERIOD;
op1_in <= X"FFFF_FFFA"; -- (-6)
op2_in <= X"0000_0005"; -- (+5)
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"0000_0006"; -- (+6)
op2_in <= X"FFFF_FFFB"; -- (-5)
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"1234_5678";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"1234_5678";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"1234_5678";
op2_in <= X"1234_5678";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"789A_BCDE";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"789A_BCDE";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait;
end process;
END;