jens 52e9decf78 - added instructions 'lwc0' and 'swc0' for testing (which are usually invalid) ...

- due to cop_reg_we in MEM_Stage, the output register is removed
  (timing is slightly degraded). The reg pointer is delayed instead by one cycle
- test-reg is now writable in user mode regardles of cop0 usability.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@406 cc03376c-175c-47c8-b038-4cd826a8556b

2009-03-18 23:30:08 +00:00

Common

- Intital revision

2008-10-26 23:52:49 +00:00

lib

- added instructions 'lwc0' and 'swc0' for testing (which are usually invalid)

2009-03-18 23:30:08 +00:00

projects/mips_sys

- FLASH alias at 0x00000000

2009-03-14 16:38:07 +00:00

S

Description

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23 MiB

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VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

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IGOR Pro 0.5%

Other 1.5%