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- redesigned :

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- din_en means stream is active
  - din_vld means shift enable
  - there also exist output versions dout_en and  dout_vld. Thus, SIPOs can be cascaded


git-svn-id: http://moon:8086/svn/vhdl/trunk@815 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-24 11:13:46 +00:00
parent d99d8e2b44
commit 869a0bd0ef
1 changed files with 44 additions and 44 deletions
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lib/emac/src/sipo.vhd
+44 -44
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@@ -16,12 +16,13 @@ ENTITY sipo IS
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
din_en : in STD_LOGIC;
din_vld : in STD_LOGIC;
din : in unsigned(data_width_in-1 downto 0);
dout_en : out STD_LOGIC;
dout_vld : out STD_LOGIC;
dout_be : out unsigned(data_width_out/data_width_in-1 downto 0);
dout : out unsigned(data_width_out-1 downto 0)
dout : out unsigned(data_width_out-1 downto 0);
dout_be : out unsigned(data_width_out/data_width_in-1 downto 0)
);
END sipo;
@@ -29,27 +30,54 @@ END sipo;
ARCHITECTURE behavior OF sipo IS
constant num_shifts : natural := data_width_out/data_width_in;
signal idle : STD_LOGIC;
signal pre_fin : STD_LOGIC;
signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
signal vld_pipe : unsigned(num_shifts-1 downto 0);
signal shift_pipe : unsigned(data_width_out-1 downto 0);
signal out_en : STD_LOGIC;
signal out_vld : STD_LOGIC;
signal din_vld_r : STD_LOGIC;
signal abort : STD_LOGIC;
--------------------------------------------------------------------------
begin
pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left);
dout_en <= out_en;
dout_vld <= out_vld;
--------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
dout_vld <= pre_fin;
if rst = '1' or pre_fin = '1' then
abort <= '0';
elsif din_vld_r = '1' and din_en = '0' then
abort <= '1';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
din_vld_r <= din_vld;
if rst = '1' then
dout_be <= (others => '0');
elsif pre_fin = '1' then
dout_be <= vld_pipe;
out_en <= '0';
elsif out_en = '0' then
out_en <= pre_fin and din_en;
elsif out_vld = '1' then
out_en <= din_vld;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
out_vld <= pre_fin;
if pre_fin = '1' then
dout <= shift_pipe;
dout_be <= shift_cnt_pipe;
end if;
end if;
end process;
@@ -57,10 +85,10 @@ end process;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' or enable = '0' then
idle <= '1';
elsif din_en = '1' then
idle <= '0';
if rst = '1' or pre_fin = '1' then
shift_cnt_pipe <= (shift_cnt_pipe'left downto 1 => '0') & din_vld;
elsif din_vld = '1' or abort = '1' then
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & din_vld;
end if;
end if;
end process;
@@ -68,39 +96,11 @@ end process;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' or pre_fin = '1' or enable = '0' then
shift_cnt_pipe <= (num_shifts-1 downto 1 => '0') & '1';
elsif idle = '0' then
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (msb_first) then
shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
else
shift_pipe <= din & shift_pipe(shift_pipe'left downto data_width_in);
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' or enable = '0' or pre_fin = '1' then
if din_vld = '1' or abort = '1' then
if (msb_first) then
vld_pipe <= (num_shifts-1 downto 1 => '0') & din_en;
shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
else
vld_pipe <= din_en & (num_shifts-2 downto 0 => '0');
end if;
else
if (msb_first) then
vld_pipe <= vld_pipe(shift_cnt_pipe'left-1 downto 0) & din_en;
else
vld_pipe <= din_en & vld_pipe(shift_cnt_pipe'left downto 1);
shift_pipe <= din & shift_pipe(shift_pipe'left downto data_width_in);
end if;
end if;
end if;