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- added busout-FIFO for future multi-sourced master capability (VGA-scan, blitter)

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Bus-out FIFO improved timing so much and leads to 300 less Slice - FIFOs are great!
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git-svn-id: http://moon:8086/svn/vhdl/trunk@666 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-19 10:37:58 +00:00
parent ffdc36ef4e
commit f7cbefef82
1 changed files with 78 additions and 19 deletions
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lib/VGA_ctrl/src/vga_frontend64.vhd
+78 -19
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@@ -142,7 +142,32 @@ architecture Behavioral of vga_frontend64 is
signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal STB_O_master : std_logic;
signal ADDR_O_master : unsigned(31 downto 0);
signal pixel_cnt : natural range 0 to MAX_REQUEST_CNT/2-1;
signal front : unsigned(31 downto 0);
signal back : unsigned(31 downto 0);
signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
-- Bus FIFO
signal bout_fifo_din : unsigned(104 downto 0);
signal bout_fifo_dout : unsigned(104 downto 0);
signal bout_fifo_re : std_logic;
signal bout_fifo_we : std_logic;
signal bout_fifo_full : std_logic;
signal bout_fifo_empty : std_logic;
signal bout_rdy : std_logic;
alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
alias bout_fifo_data_in is bout_fifo_din(95 downto 32);
alias bout_fifo_sel_in is bout_fifo_din(103 downto 96);
alias bout_fifo_we_in is bout_fifo_din(104);
alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0);
alias bout_fifo_data_out is bout_fifo_dout(95 downto 32);
alias bout_fifo_sel_out is bout_fifo_dout(103 downto 96);
alias bout_fifo_we_out is bout_fifo_dout(104);
type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
signal s, sn : vm_state_t;
@@ -242,9 +267,16 @@ inst_linefifo: entity work.fifo_async
fifo_color_in <= MDAT_I;
fifo_color_re <= stat_scan and odd_pixel(0);
fifo_color_we <= ACK_I and read_bus_en; -- TODO:
SRDY_O <= CYC_I; -- and cg_rdy;
MRDY_O <= not fifo_full;
SEL_O <= (others => '0');
WE_O <= '0';
-- SEL_O <= (others => '0');
-- WE_O <= '0';
STB_O <= not bout_fifo_empty;
ADDR_O <= bout_fifo_addr_out;
MDAT_O <= bout_fifo_data_out;
SEL_O <= bout_fifo_sel_out;
WE_O <= bout_fifo_we_out;
vga_master_next:
process(CLK_I)
@@ -263,7 +295,7 @@ vga_master:
begin
CYC_O <= '0';
STB_O <= '0';
STB_O_master <= '0';
pixel_cnt_rst <= '0';
request_cnt_rst <= '0';
request_cnt_en <= '0';
@@ -291,13 +323,13 @@ vga_master:
when bus_request =>
CYC_O <= '1';
request_cnt_rst <= '1';
if SRDY_I = '1' then
-- if SRDY_I = '1' then
sn <= bus_access;
end if;
-- end if;
when bus_access =>
CYC_O <= '1';
STB_O <= '1';
STB_O_master <= '1';
request_cnt_en <= '1';
read_bus_en <= '1';
if fifo_almost_full = '1' then
@@ -324,7 +356,7 @@ request_counter:
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= 0;
elsif request_cnt_en = '1' and SRDY_I = '1' then
elsif request_cnt_en = '1' and bout_rdy = '1' then
if request_cnt /= MAX_REQUEST_CNT-1 then
request_cnt <= request_cnt + 1;
end if;
@@ -348,30 +380,59 @@ read_counter:
pixel_counter:
process(CLK_I)
variable pixel_cnt : natural range 0 to MAX_REQUEST_CNT/2-1;
variable front : unsigned(31 downto 0);
variable back : unsigned(31 downto 0);
begin
if rising_edge(CLK_I) then
bufchg <= '0';
if pixel_cnt_rst = '1' then
pixel_cnt := 0;
front := host_fb_front;
elsif request_cnt_en = '1' and SRDY_I = '1' then
pixel_cnt <= 0;
front <= host_fb_front;
elsif request_cnt_en = '1' and bout_rdy = '1' then
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
pixel_cnt := pixel_cnt + 1;
pixel_cnt <= pixel_cnt + 1;
else
pixel_cnt := 0;
front := host_fb_back;
pixel_cnt <= 0;
front <= host_fb_back;
bufchg <= '1';
end if;
end if;
vga_fb_front <= front;
vga_fb_back <= back;
ADDR_O <= front + (to_unsigned(pixel_cnt, 29) & "000");
end if;
end process;
-- Instantiate synchronous FIFO
inst_bout_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 1,
data_width => 105
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => bout_fifo_we,
re => bout_fifo_re,
fifo_full => bout_fifo_full,
fifo_empty => bout_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => bout_fifo_din,
data_r => bout_fifo_dout
);
bout_rdy <= not bout_fifo_full;
bout_fifo_re <= not bout_fifo_empty and SRDY_I;
bout_fifo_we <= STB_O_master and request_cnt_en;
bout_fifo_data_in <= (others => '-');
bout_fifo_addr_in <= ADDR_O_master;
bout_fifo_sel_in <= (others => '1');
bout_fifo_we_in <= '0';
ADDR_O_master <= front + (to_unsigned(pixel_cnt, 29) & "000");
inst_char_gen : entity work.char_gen
GENERIC MAP
(
@@ -408,8 +469,6 @@ inst_char_gen : entity work.char_gen
csr_pos_y_out => cg_csr_pos_y,
char_draw_en => cg_draw
);
SRDY_O <= CYC_I; -- and cg_rdy;
MDAT_O <= (others => '-');
scan_rdy <= stat_hready and stat_vready;
cg_en <= stat_scan;