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- cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@577 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-03 20:38:55 +00:00
parent ee04924d42
commit 88d3bd6607
1 changed files with 38 additions and 37 deletions
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lib/misc/clockgen_virtex4.vhd
+38 -37
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@@ -25,14 +25,17 @@ library ieee, work;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.utils_pkg.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity clockgen is
generic
(
sys1_phaseshift : integer := 0;
frequency_hz : integer := 100E6
clk_in_freq_hz : integer := 100E6;
clk0_out_phaseshift : integer := 0;
clk1_out_phaseshift : integer := 0
);
port
(
@@ -40,10 +43,10 @@ entity clockgen is
rst : in std_logic; -- external async reset, low active
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
clk_fb_in : in std_logic; -- feedback clock
sys1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sys1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0°
sys0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270°
clk0_0_out : out std_logic; -- System clock #0, dcm#0 output 0°
clk0_270_out : out std_logic; -- System clock #0, dcm#0 output 270°
clk1_0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out : out std_logic; -- DCM locked status
error_out : out std_logic -- indicates DCM Errors
);
@@ -51,18 +54,16 @@ end;
architecture tech of clockgen is
constant CLKIN_PER : real := real(1000E6/frequency_hz);
signal locked : unsigned(1 downto 0);
signal dcm_rst : unsigned(1 downto 0);
signal sys1_clk0 : std_logic;
signal sys1_clk270 : std_logic;
signal sys1_clk0_bufg : std_logic;
signal sys1_clk270_bufg : std_logic;
signal sys0_clk0 : std_logic;
signal sys0_clk270 : std_logic;
signal sys0_clk0_bufg : std_logic;
signal sys0_clk270_bufg : std_logic;
signal clk1_0 : std_logic;
signal clk1_270 : std_logic;
signal clk1_0_bufg : std_logic;
signal clk1_270_bufg : std_logic;
signal clk0_0 : std_logic;
signal clk0_270 : std_logic;
signal clk0_0_bufg : std_logic;
signal clk0_270_bufg : std_logic;
signal dcm1_locked, dcm2_locked : unsigned(2 downto 0);
signal cnt_q : unsigned(4 downto 0);
@@ -71,35 +72,35 @@ architecture tech of clockgen is
begin
sys1_clk0_out <= sys1_clk0_bufg;
sys1_clk270_out <= sys1_clk270_bufg;
sys0_clk0_out <= sys0_clk0_bufg;
sys0_clk270_out <= sys0_clk270_bufg;
clk1_0_out <= clk1_0_bufg;
clk1_270_out <= clk1_270_bufg;
clk0_0_out <= clk0_0_bufg;
clk0_270_out <= clk0_270_bufg;
bufg11: bufg
port map
(
o => sys0_clk0_bufg,
i => sys0_clk0
o => clk0_0_bufg,
i => clk0_0
);
bufg12: bufg
port map (
o => sys0_clk270_bufg,
i => sys0_clk270
o => clk0_270_bufg,
i => clk0_270
);
bufg13: bufg
port map
(
o => sys1_clk0_bufg,
i => sys1_clk0
o => clk1_0_bufg,
i => clk1_0
);
bufg14: bufg
port map (
o => sys1_clk270_bufg,
i => sys1_clk270
o => clk1_270_bufg,
i => clk1_270
);
-------------------------------------------------------------------------------------------------------
@@ -113,7 +114,7 @@ inst_DCM_BASE_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -124,12 +125,12 @@ inst_DCM_BASE_0 : DCM_BASE
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
PHASE_SHIFT => clk0_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => sys0_clk0, -- 0 degree DCM CLK ouptput
CLK0 => clk0_0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => sys0_clk270, -- 270 degree DCM CLK output
CLK270 => clk0_270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
@@ -149,7 +150,7 @@ inst_DCM_BASE_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -160,12 +161,12 @@ inst_DCM_BASE_0 : DCM_BASE
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => sys1_phaseshift, -- Amount of fixed phase shift from -255 to 1023
PHASE_SHIFT => clk1_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => sys1_clk0, -- 0 degree DCM CLK ouptput
CLK0 => clk1_0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => sys1_clk270, -- 270 degree DCM CLK output
CLK270 => clk1_270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
@@ -173,7 +174,7 @@ inst_DCM_BASE_0 : DCM_BASE
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => locked(1), -- DCM LOCK status output
CLKFB => sys1_clk0_bufg, -- DCM clock feedback
CLKFB => clk1_0_bufg, -- DCM clock feedback
CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(1) -- DCM asynchronous reset input
);