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- added two addtional UARTs

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git-svn-id: http://moon:8086/svn/vhdl/trunk@503 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-08 21:32:34 +00:00
parent b288e8ee43
commit 15d9de633c
2 changed files with 112 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys_sim.vhd
+98 -25
View File
@@ -58,8 +58,12 @@ PORT
sys_led : out unsigned(8 downto 0);
-- UART
sys_rx : in std_logic;
sys_tx : out std_logic;
sys_uart0_rx : in std_logic;
sys_uart0_tx : out std_logic;
sys_uart1_rx : in std_logic;
sys_uart1_tx : out std_logic;
sys_uart2_rx : in std_logic;
sys_uart2_tx : out std_logic;
-- LCD
sys_lcd_d : inout unsigned(3 downto 0);
@@ -139,6 +143,7 @@ ARCHITECTURE behavior OF mips_sys IS
(
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
@@ -347,6 +352,7 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
signal nmi : std_logic;
signal rst : std_logic;
signal clk : std_logic;
signal eb : std_logic;
@@ -354,7 +360,9 @@ ARCHITECTURE behavior OF mips_sys IS
signal clk270var : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart : std_logic;
signal int_uart0 : std_logic;
signal int_uart1 : std_logic;
signal int_uart2 : std_logic;
signal locked : std_logic;
signal ac97_rstn : std_logic;
signal flash_rstn : std_logic;
@@ -445,10 +453,18 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_gpio : std_logic;
signal SDAT_O_gpio : unsigned(31 downto 0);
signal CYC_I_uart : std_logic;
signal ACK_O_uart : std_logic;
signal SRDY_O_uart : std_logic;
signal SDAT_O_uart : unsigned(31 downto 0);
signal CYC_I_uart0 : std_logic;
signal ACK_O_uart0 : std_logic;
signal SRDY_O_uart0 : std_logic;
signal SDAT_O_uart0 : unsigned(31 downto 0);
signal CYC_I_uart1 : std_logic;
signal ACK_O_uart1 : std_logic;
signal SRDY_O_uart1 : std_logic;
signal SDAT_O_uart1 : unsigned(31 downto 0);
signal CYC_I_uart2 : std_logic;
signal ACK_O_uart2 : std_logic;
signal SRDY_O_uart2 : std_logic;
signal SDAT_O_uart2 : unsigned(31 downto 0);
signal CYC_I_vga : std_logic;
signal ACK_O_vga : std_logic;
@@ -483,7 +499,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_uart2, mem_uart, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
BEGIN
@@ -493,7 +509,8 @@ BEGIN
gpi1(7 downto 0) <= sys_dip;
sys_led <= gpo0(8 downto 0);
sys_error <= debug;
rst_in <= not sys_rst_n_in;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
rst <= not locked;
sys_usb_rstn <= not gpo1(0);
sys_flash_byten <= '1';
@@ -574,7 +591,7 @@ int_sample:
process(clk)
begin
if rising_edge(clk) then
INT <= int_timer & '0' & INT_O_ac97 & sys_usb_int & int_uart & sys_btn(4);
INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4);
end if;
end process;
@@ -589,7 +606,13 @@ mem_mux:
if ADDR_O(18 downto 16) = "000" then
mem_area <= mem_gpio;
elsif ADDR_O(18 downto 16) = "001" then
mem_area <= mem_uart;
if ADDR_O(9 downto 8) = "00" then
mem_area <= mem_uart0;
elsif ADDR_O(9 downto 8) = "01" then
mem_area <= mem_uart1;
elsif ADDR_O(9 downto 8) = "10" then
mem_area <= mem_uart2;
end if;
elsif ADDR_O(18 downto 16) = "010" then
mem_area <= mem_usb;
elsif ADDR_O(18 downto 16) = "011" then
@@ -615,7 +638,9 @@ signal_mux:
process(mem_area, CYC_O)
begin
CYC_I_uart <= '0';
CYC_I_uart0 <= '0';
CYC_I_uart1 <= '0';
CYC_I_uart2 <= '0';
CYC_I_gpio <= '0';
CYC_I_flash <= '0';
CYC_I_usb <= '0';
@@ -630,8 +655,14 @@ signal_mux:
when mem_gpio =>
CYC_I_gpio <= CYC_O;
when mem_uart =>
CYC_I_uart <= CYC_O;
when mem_uart0 =>
CYC_I_uart0 <= CYC_O;
when mem_uart1 =>
CYC_I_uart1 <= CYC_O;
when mem_uart2 =>
CYC_I_uart2 <= CYC_O;
when mem_flash =>
CYC_I_flash <= CYC_O;
@@ -661,14 +692,16 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_uart2 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_uart2 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else
SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else
SDAT_O_usb when CYC_I_usb = '1' else
SDAT_O_uart when CYC_I_uart = '1' else
SDAT_O_uart0 when CYC_I_uart0 = '1' else
SDAT_O_uart1 when CYC_I_uart1 = '1' else
SDAT_O_uart2 when CYC_I_uart2 = '1' else
SDAT_O_vga when CYC_I_vga = '1' else
SDAT_O_ac97 when CYC_I_ac97 = '1' else
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
@@ -679,6 +712,7 @@ inst_mips_top: mips_top
(
debug => debug,
eb => eb,
nmi => nmi,
RST_I => rst,
CLK_I => clk,
ACK_I => ACK_I_cpu,
@@ -809,26 +843,65 @@ inst_usb_port : async_port_wb
async_rst => open
);
inst_uart_wb : uart_wb
inst_uart_wb_0 : uart_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_uart,
CYC_I => CYC_I_uart0,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_uart,
SRDY_O => SRDY_O_uart,
ACK_O => ACK_O_uart0,
SRDY_O => SRDY_O_uart0,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_uart,
INT_O => int_uart,
ser_rx => sys_rx,
ser_tx => sys_tx
DAT_O => SDAT_O_uart0,
INT_O => int_uart0,
ser_rx => sys_uart0_rx,
ser_tx => sys_uart0_tx
);
inst_uart_wb_1 : uart_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_uart1,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_uart1,
SRDY_O => SRDY_O_uart1,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_uart1,
INT_O => int_uart1,
ser_rx => sys_uart1_rx,
ser_tx => sys_uart1_tx
);
inst_uart_wb_2 : uart_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_uart2,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_uart2,
SRDY_O => SRDY_O_uart2,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_uart2,
INT_O => int_uart2,
ser_rx => sys_uart2_rx,
ser_tx => sys_uart2_tx
);
inst_ssram_port_wb : entity work.ssram_port_wb
GENERIC MAP
(
projects/mips_sys/src/tb_mips_sys.vhd
+14 -2
View File
@@ -46,6 +46,10 @@ ARCHITECTURE behavior OF tb_mips_sys IS
signal led : unsigned(8 downto 0);
signal sys_rx : std_logic := '1';
signal sys_tx : std_logic;
signal sys_rx1 : std_logic := '1';
signal sys_tx1 : std_logic;
signal sys_rx2 : std_logic := '1';
signal sys_tx2 : std_logic;
signal sys_lcd_d : unsigned(3 downto 0);
signal sys_lcd_e : std_logic;
@@ -128,8 +132,12 @@ uut: entity work.mips_sys
sys_dip => dip,
sys_led => led,
sys_rx => sys_rx,
sys_tx => sys_tx,
sys_uart0_rx => sys_rx,
sys_uart0_tx => sys_tx,
sys_uart1_rx => sys_rx1,
sys_uart1_tx => sys_tx1,
sys_uart2_rx => sys_rx2,
sys_uart2_tx => sys_tx2,
sys_lcd_d => sys_lcd_d,
sys_lcd_e => sys_lcd_e,
@@ -322,8 +330,12 @@ STIMULUS: process
begin
btn(0) <= '1';
btn(2) <= '1';
wait for 3*CLK_PERIOD;
sys_rst_n_in <= '1';
btn(0) <= '0';
btn(2) <= '0';
wait for 200000*CLK_PERIOD;
loop