jens 989fe72ddb - read-page cycle is minimum 2 cycles ...

- change assertion check: Read page pulse length must be greater than one

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git-svn-id: http://moon:8086/svn/vhdl/trunk@563 cc03376c-175c-47c8-b038-4cd826a8556b

2009-10-30 10:49:15 +00:00

Common

- Intital revision

2008-10-26 23:52:49 +00:00

lib

- read-page cycle is minimum 2 cycles

2009-10-30 10:49:15 +00:00

projects/mips_sys

- now 30 ns

2009-10-29 22:57:11 +00:00

S

Description

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23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%