- modified input rdy logic to avoid multi cycle ready after idle

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git-svn-id: http://moon:8086/svn/vhdl/trunk@826 cc03376c-175c-47c8-b038-4cd826a8556b

lib/emac/src/piso.vhd

@@ -57,7 +57,7 @@ begin
 		elsif pre_fin = '1' and rdy = '0' then
 			rdy		<= '1';
 		elsif din_vld = '1' then
-			rdy			<= not din_vld_reg;
+			rdy			<= '0';
 		end if;
 	end if;
 end process;
@@ -89,7 +89,7 @@ begin
 		if rst = '1' then
 			shift_cnt_pipe	<= (others => '1');
 		elsif dout_en = '1' then
-			if pre_fin = '1' and din_vld_reg = '1' then
+			if (pre_fin = '1' and din_vld_reg = '1') or (din_vld = '1' and din_vld_reg = '0') then
 				shift_cnt_pipe	<= (others => '0');
 			else
 				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';