Refactored filenames

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git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1032 cc03376c-175c-47c8-b038-4cd826a8556b

Common/sim/compile_simprim.do

@@ -1,8 +0,0 @@
-vlib simprim
-
-set XILINX C:/Programme/Xilinx101/ISE
-
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd

Common/sim/compile_unisim.do

@@ -1,8 +0,0 @@
-vlib unisim
-
-set XILINX C:/Programme/Xilinx101/ISE
-
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vpkg.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vcomp.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_smodel.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vital.vhd

Common/ucf/ml402.ucf

@@ -1,675 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#     
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-# Bus clock nets
-NET "sys_clk"  TNM_NET = "sys_clk";
-NET "tft_clk"  TNM_NET = "tft_clk";
-NET sys_clk_in TNM_NET = "sys_clk_in";
-TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
-
-NET sys_clk_in LOC = AE14;
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET sys_rst_in LOC = D6;
-NET sys_rst_in PULLUP;
-NET sys_rst_in TIG;
-
-NET uart_RX LOC = W2;
-NET uart_RX IOSTANDARD = LVCMOS33;
-NET uart_RX TIG;
-NET uart_TX LOC = W1;
-NET uart_TX IOSTANDARD = LVCMOS33;
-NET uart_TX TIG;
-
-NET ext_irq TIG;
-
-# Reset timing ignore - treat as async paths
-NET sys_rst TIG;
-NET opb_v20_0_OPB_Rst TIG;
-NET lmb_v10_1_OPB_Rst TIG;
-NET lmb_v10_0_OPB_Rst TIG;
-NET opb_v20_0_Debug_SYS_Rst TIG;
-NET Debug_Rst TIG;
-NET plb_v34_0_PLB_Rst TIG;
-NET dcm_locked TIG;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
-INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
-INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
-
-INST dcm_0/dcm_0/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y0;
-INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
-INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
-
-INST dcm_1/dcm_1/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y31;
-INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches 
-////////////////////////////////////////////////////////////////////////////
-
-# GPLED 0-3
-NET gpio<0>  LOC = G5;  #GPLED0
-NET gpio<1>  LOC = G6;  #GPLED1
-NET gpio<2>  LOC = A11; #GPLED2
-NET gpio<3>  LOC = A12; #GPLED3
-# North-East-South-West-Center LEDs
-NET gpio<4>  LOC = C6;  # C LED
-NET gpio<5>  LOC = F9;  # W LED
-NET gpio<6>  LOC = A5;  # S LED
-NET gpio<7>  LOC = E10; # E LED
-NET gpio<8>  LOC = E2;  # N LED
-# North-East-South-West-Center Buttons
-NET gpio<9>  LOC = B6;  # C Button
-NET gpio<10> LOC = E9;  # W Button
-NET gpio<11> LOC = A6;  # S Button
-NET gpio<12> LOC = F10; # E Button
-NET gpio<13> LOC = E7;  # N Button
-# Dip Switches 1-8
-NET gpio<14> LOC = U24; # DIP SW 8
-NET gpio<15> LOC = U25; # DIP SW 7
-NET gpio<16> LOC = V23; # DIP SW 6
-NET gpio<17> LOC = U23; # DIP SW 5
-NET gpio<18> LOC = U26; # DIP SW 4
-NET gpio<19> LOC = T26; # DIP SW 3
-NET gpio<20> LOC = R19; # DIP SW 2
-NET gpio<21> LOC = R20; # DIP SW 1
-NET gpio<14> IOSTANDARD = LVCMOS33;
-NET gpio<15> IOSTANDARD = LVCMOS33;
-NET gpio<16> IOSTANDARD = LVCMOS33;
-NET gpio<17> IOSTANDARD = LVCMOS33;
-NET gpio<18> IOSTANDARD = LVCMOS33;
-NET gpio<19> IOSTANDARD = LVCMOS33;
-NET gpio<20> IOSTANDARD = LVCMOS33;
-NET gpio<21> IOSTANDARD = LVCMOS33;
-#SMA Connectors
-NET gpio<22> LOC = C12; # SMA_IN_N
-NET gpio<23> LOC = C13; # SMA_IN_P
-NET gpio<24> LOC = D7;  # SMA_OUT_N
-NET gpio<25> LOC = D8;  # SMA_OUT_P
-NET gpio<26> LOC = AD12;# USERCLK
-NET gpio<26> IOSTANDARD = LVCMOS33;
-
-NET "gpio<*>" PULLDOWN;
-NET "gpio<*>" TIG;
-NET "gpio<*>" SLEW = SLOW;
-NET "gpio<*>" DRIVE = 2;
-
-NET "gpio<22>" SLEW = FAST;
-NET "gpio<22>" DRIVE = 12;
-NET "gpio<23>" SLEW = FAST;
-NET "gpio<23>" DRIVE = 12;
-NET "gpio<24>" SLEW = FAST;
-NET "gpio<24>" DRIVE = 12;
-NET "gpio<25>" SLEW = FAST;
-NET "gpio<25>" DRIVE = 12;
-
-NET  "gpio2_d_out<*>" TIG;
-NET  "gpio2_t_out<*>" TIG;
-NET  "gpio2_in<*>" TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for PS/2 Ports
-#------------------------------------------------------------------------------
-
-#Keyboard
-NET ps2_keyb_clk  LOC = D2;
-NET ps2_keyb_clk  SLEW = SLOW;
-NET ps2_keyb_clk  DRIVE = 2;
-NET ps2_keyb_clk  TIG;
-NET ps2_keyb_data LOC = G9;
-NET ps2_keyb_data SLEW = SLOW;
-NET ps2_keyb_data DRIVE = 2;
-NET ps2_keyb_data TIG;
-
-#Mouse
-NET ps2_mouse_clk  LOC = B14;
-NET ps2_mouse_clk  SLEW = SLOW;
-NET ps2_mouse_clk  DRIVE = 2;
-NET ps2_mouse_clk  TIG;
-NET ps2_mouse_data LOC = C14;
-NET ps2_mouse_data SLEW = SLOW;
-NET ps2_mouse_data DRIVE = 2;
-NET ps2_mouse_data TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for IIC Controller
-#------------------------------------------------------------------------------
-
-NET iic_scl    LOC = A17;
-NET iic_sda    LOC = B17;
-NET iic_scl    SLEW = SLOW;
-NET iic_scl    DRIVE = 6;
-NET iic_scl    TIG;
-NET iic_sda    SLEW = SLOW;
-NET iic_sda    DRIVE = 6;
-NET iic_sda    TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for AC97 Sound Controller
-#------------------------------------------------------------------------------
-
-NET ac97_bit_clk   LOC = AE10;
-NET ac97_bit_clk   IOSTANDARD = LVCMOS33;
-NET ac97_bit_clk   PERIOD = 80;
-NET ac97_sdata_in  LOC = AD16;
-NET ac97_sdata_in  IOSTANDARD = LVCMOS33;
-NET ac97_reset_n   LOC = AD10;
-NET ac97_reset_n   IOSTANDARD = LVCMOS33;
-NET ac97_reset_n   TIG;
-NET ac97_sdata_out LOC = C8;
-NET ac97_sync      LOC = D9;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for System ACE MPU / USB
-#------------------------------------------------------------------------------
-
-NET sysace_clk_in   LOC        = AF11;
-NET sysace_clk_in   IOSTANDARD = LVCMOS33;
-NET sysace_clk_in   TNM_NET    = "sysace_clk_in";
-# Leave 1 ns margin
-TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
-
-NET sace_usb_a<0>   LOC        = U22;
-NET sace_usb_a<1>   LOC        = Y10;
-NET sace_usb_a<2>   LOC        = AA10;
-NET sace_usb_a<3>   LOC        = AC7;
-NET sace_usb_a<4>   LOC        = Y7;
-NET sace_usb_a<5>   LOC        = AA9;
-NET sace_usb_a<6>   LOC        = Y9;
-NET sace_usb_a<*>   IOSTANDARD = LVCMOS33;
-NET sace_usb_a<*>   SLEW       = FAST;
-NET sace_usb_a<*>   DRIVE      = 8;
-NET sace_mpce       LOC        = AD5;
-NET sace_mpce       IOSTANDARD = LVCMOS33;
-NET sace_mpce       SLEW       = FAST;
-NET sace_mpce       DRIVE      = 8;
-NET sace_usb_d<0>   LOC        = AB7;
-NET sace_usb_d<1>   LOC        = AC9;
-NET sace_usb_d<2>   LOC        = AB9;
-NET sace_usb_d<3>   LOC        = AE6;
-NET sace_usb_d<4>   LOC        = AD6;
-NET sace_usb_d<5>   LOC        = AF9;
-NET sace_usb_d<6>   LOC        = AE9;
-NET sace_usb_d<7>   LOC        = AD8;
-NET sace_usb_d<8>   LOC        = AC8;
-NET sace_usb_d<9>   LOC        = AF4;
-NET sace_usb_d<10>  LOC        = AE4;
-NET sace_usb_d<11>  LOC        = AD3;
-NET sace_usb_d<12>  LOC        = AC3;
-NET sace_usb_d<13>  LOC        = AF6;
-NET sace_usb_d<14>  LOC        = AF5;
-NET sace_usb_d<15>  LOC        = AA7;
-NET sace_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sace_usb_d<*>   SLEW       = FAST;
-NET sace_usb_d<*>   DRIVE      = 8;
-NET sace_usb_d<*>   PULLDOWN;
-NET sace_usb_oen    LOC        = AA8;
-NET sace_usb_oen    IOSTANDARD = LVCMOS33;
-NET sace_usb_oen    SLEW       = FAST;
-NET sace_usb_oen    DRIVE      = 8;
-NET sace_usb_wen    LOC        = Y8;
-NET sace_usb_wen    IOSTANDARD = LVCMOS33;
-NET sace_usb_wen    SLEW       = FAST;
-NET sace_usb_wen    DRIVE      = 8;
-NET sysace_mpirq    LOC        = AD4;
-NET sysace_mpirq    IOSTANDARD = LVCMOS33;
-NET sysace_mpirq    TIG;
-NET sysace_mpirq    PULLDOWN;
-
-NET usb_csn         LOC        = AF10;
-NET usb_csn         IOSTANDARD = LVCMOS33;
-NET usb_csn         SLEW       = FAST;
-NET usb_csn         DRIVE      = 8;
-NET usb_hpi_reset_n LOC        = A7;
-NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
-NET usb_hpi_reset_n TIG;
-NET usb_hpi_int     LOC        = V5;
-NET usb_hpi_int     IOSTANDARD = LVCMOS33;
-NET usb_hpi_int     TIG;
-NET usb_hpi_int     PULLDOWN;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET ddr_ad<0>  LOC = C26; # DDR_A0
-NET ddr_ad<1>  LOC = E17; # DDR_A1
-NET ddr_ad<2>  LOC = D18; # DDR_A2
-NET ddr_ad<3>  LOC = C19; # DDR_A3
-NET ddr_ad<4>  LOC = F17; # DDR_A4
-NET ddr_ad<5>  LOC = B18; # DDR_A5
-NET ddr_ad<6>  LOC = B20; # DDR_A6
-NET ddr_ad<7>  LOC = C20; # DDR_A7
-NET ddr_ad<8>  LOC = D20; # DDR_A8
-NET ddr_ad<9>  LOC = C21; # DDR_A9
-NET ddr_ad<10> LOC = A18; # DDR_A10
-NET ddr_ad<11> LOC = B21; # DDR_A11
-NET ddr_ad<12> LOC = A24; # DDR_A12
-NET ddr_ba<0>  LOC = B12; # DDR_BA0
-NET ddr_ba<1>  LOC = A16; # DDR_BA1
-NET ddr_casb   LOC = F23; # DDR_CAS_N
-NET ddr_cke    LOC = G22; # DDR_CKE
-NET ddr_csb    LOC = G21; # DDR_CS_N
-NET ddr_rasb   LOC = F24; # DDR_RAS_N
-NET ddr_web    LOC = A23; # DDR_WE_N
-
-NET ddr_clk    LOC = A10; # DDR_CK1_P
-NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET ddr_clkb   LOC = B10; # DDR_CK1_N
-
-NET ddr_dm<0>  LOC = G19; # DDR_DM0
-NET ddr_dm<1>  LOC = G24; # DDR_DM1
-NET ddr_dm<2>  LOC = G20; # DDR_DM2
-NET ddr_dm<3>  LOC = C22; # DDR_DM3
-
-NET ddr_dqs<0> LOC = D25; # DDR_DQS0
-NET ddr_dqs<1> LOC = G18; # DDR_DQS1
-NET ddr_dqs<2> LOC = G17; # DDR_DQS2
-NET ddr_dqs<3> LOC = D26; # DDR_DQS3
-
-NET ddr_dq<0> LOC = H20; # DDR_D0
-NET ddr_dq<1> LOC = E23; # DDR_D1
-NET ddr_dq<2> LOC = H26; # DDR_D2
-NET ddr_dq<3> LOC = H22; # DDR_D3
-NET ddr_dq<4> LOC = E25; # DDR_D4
-NET ddr_dq<5> LOC = E26; # DDR_D5
-NET ddr_dq<6> LOC = F26; # DDR_D6
-NET ddr_dq<7> LOC = E24; # DDR_D7
-NET ddr_dq<8> LOC = E20; # DDR_D8
-NET ddr_dq<9> LOC = A22; # DDR_D9
-NET ddr_dq<10> LOC = C23; # DDR_D10
-NET ddr_dq<11> LOC = C24; # DDR_D11
-NET ddr_dq<12> LOC = A20; # DDR_D12
-NET ddr_dq<13> LOC = A21; # DDR_D13
-NET ddr_dq<14> LOC = D24; # DDR_D14
-NET ddr_dq<15> LOC = E18; # DDR_D15
-NET ddr_dq<16> LOC = F18; # DDR_D16
-NET ddr_dq<17> LOC = A19; # DDR_D17
-NET ddr_dq<18> LOC = F19; # DDR_D18
-NET ddr_dq<19> LOC = B23; # DDR_D19
-NET ddr_dq<20> LOC = E21; # DDR_D20
-NET ddr_dq<21> LOC = D22; # DDR_D21
-NET ddr_dq<22> LOC = D23; # DDR_D22
-NET ddr_dq<23> LOC = B24; # DDR_D23
-NET ddr_dq<24> LOC = E22; # DDR_D24
-NET ddr_dq<25> LOC = F20; # DDR_D25
-NET ddr_dq<26> LOC = H23; # DDR_D26
-NET ddr_dq<27> LOC = G25; # DDR_D27
-NET ddr_dq<28> LOC = G26; # DDR_D28
-NET ddr_dq<29> LOC = H25; # DDR_D29
-NET ddr_dq<30> LOC = H24; # DDR_D30
-NET ddr_dq<31> LOC = H21; # DDR_D31
-
-NET ddr_ad<*>  IOSTANDARD = SSTL2_I;
-NET ddr_ba<*>  IOSTANDARD = SSTL2_I;
-NET ddr_casb   IOSTANDARD = SSTL2_I;
-NET ddr_cke    IOSTANDARD = SSTL2_I;
-NET ddr_clk    IOSTANDARD = SSTL2_I;
-NET ddr_clk_fb IOSTANDARD = LVCMOS25;
-NET ddr_clkb   IOSTANDARD = SSTL2_I;
-NET ddr_casb   IOSTANDARD = SSTL2_I;
-NET ddr_csb    IOSTANDARD = SSTL2_I;
-NET ddr_rasb   IOSTANDARD = SSTL2_I;
-NET ddr_web    IOSTANDARD = SSTL2_I;
-
-NET ddr_dqs<*> IOSTANDARD = SSTL2_II;
-NET ddr_dm<*>  IOSTANDARD = SSTL2_II;
-NET ddr_dq<*>  IOSTANDARD = SSTL2_II;
-
-// Timing Constraint for DDR Feedback Clock
-NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
-TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
-#------------------------------------------------------------------------------
-
-NET tft_lcd_b<0> LOC = L26; # VGA_B2
-NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_b<1> LOC = C5;  # VGA_B3
-NET tft_lcd_b<2> LOC = C7;  # VGA_B4
-NET tft_lcd_b<3> LOC = B7;  # VGA_B5
-NET tft_lcd_b<4> LOC = G8;  # VGA_B6
-NET tft_lcd_b<5> LOC = F8;  # VGA_B7
-NET tft_lcd_b<*> SLEW = FAST;
-NET tft_lcd_b<*> DRIVE = 8;
-
-NET tft_lcd_clk  LOC = AF8;
-NET tft_lcd_clk  IOSTANDARD = LVDCI_33;
-NET tft_lcd_clk  SLEW = FAST;
-NET tft_lcd_clk  DRIVE = 8;
-
-NET tft_lcd_g<0> LOC = M20; # VGA_G2
-NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_g<1> LOC = E4;  # VGA_G3
-NET tft_lcd_g<2> LOC = D3;  # VGA_G4
-NET tft_lcd_g<3> LOC = H7;  # VGA_G5
-NET tft_lcd_g<4> LOC = H8;  # VGA_G6
-NET tft_lcd_g<5> LOC = C1;  # VGA_G7
-NET tft_lcd_g<*> SLEW = FAST;
-NET tft_lcd_g<*> DRIVE = 8;
-
-NET tft_lcd_hsync LOC = C10;
-NET tft_lcd_hsync SLEW = FAST;
-NET tft_lcd_hsync DRIVE = 8;
-
-NET tft_lcd_r<0> LOC = N25; #VGA_R2
-NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_r<1> LOC = C2; #VGA_R3
-NET tft_lcd_r<2> LOC = G7; #VGA_R4
-NET tft_lcd_r<3> LOC = F7; #VGA_R5
-NET tft_lcd_r<4> LOC = E5; #VGA_R6
-NET tft_lcd_r<5> LOC = E6; #VGA_R7
-NET tft_lcd_r<*> SLEW = FAST;
-NET tft_lcd_r<*> DRIVE = 8;
-
-NET tft_lcd_vsync LOC = A8;
-NET tft_lcd_vsync SLEW = FAST;
-NET tft_lcd_vsync DRIVE = 8;
-
-TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
-TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET plb_error LOC = L24;
-NET plb_error IOSTANDARD = LVCMOS33;
-NET plb_error TIG;
-NET opb_error LOC = V6;
-NET opb_error IOSTANDARD = LVCMOS33;
-NET opb_error TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Ethernet
-#------------------------------------------------------------------------------
-
-NET phy_col        LOC = E3;
-NET phy_crs        LOC = D5;
-NET phy_dv         LOC = A9;
-NET phy_rx_clk     LOC = B15;
-NET phy_rx_data<3> LOC = C4;
-NET phy_rx_data<2> LOC = D4;
-NET phy_rx_data<1> LOC = E1;
-NET phy_rx_data<0> LOC = F1;
-
-NET phy_rx_er      LOC = B9;
-NET phy_tx_clk     LOC = C15;
-NET phy_mii_clk    LOC = D1;
-NET phy_mii_int_n  LOC = H4;
-NET phy_rst_n      LOC = D10;
-NET phy_tx_data<3> LOC = G1;
-NET phy_tx_data<2> LOC = H3;
-NET phy_tx_data<1> LOC = H2;
-NET phy_tx_data<0> LOC = H1;
-NET phy_tx_en      LOC = F4;
-NET phy_tx_er      LOC = F3;
-NET phy_mii_data   LOC = G4;
-
-NET phy_mii_int_n  PULLUP;
-
-NET phy_mii_int_n  TIG;
-NET phy_rst_n      TIG;
-
-# Timing Constraints (these are recommended in documentation and
-# are unaltered except for the TIG)
-NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
-NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
-TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
-TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
-
-NET "phy_tx_clk" MAXSKEW= 1.0 ns;
-NET "phy_rx_clk" MAXSKEW= 1.0 ns;
-NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
-NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
-
-NET "phy_rx_data<3>" IOBDELAY=NONE;
-NET "phy_rx_data<2>" IOBDELAY=NONE;
-NET "phy_rx_data<1>" IOBDELAY=NONE;
-NET "phy_rx_data<0>" IOBDELAY=NONE;
-NET "phy_dv" IOBDELAY=NONE;
-NET "phy_rx_er" IOBDELAY=NONE;
-NET "phy_crs" IOBDELAY=NONE;
-NET "phy_col" IOBDELAY=NONE;
-
-# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/DVD_FF"   IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RER_FF"   IOB=FALSE;
-
-# Timing ignores (to specify unconstrained paths)
-TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
-TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
-TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
-TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for SRAM/FLASH
-#------------------------------------------------------------------------------
-
-NET sram_clk            LOC = AF7;
-NET sram_clk_fb         LOC = AD17;
-NET flash_a23           LOC = T21;
-NET sram_flash_addr<22> LOC = U20;
-NET sram_flash_addr<21> LOC = T19;
-NET sram_flash_addr<20> LOC = AC5;
-NET sram_flash_addr<19> LOC = AB5;
-NET sram_flash_addr<18> LOC = AC4;
-NET sram_flash_addr<17> LOC = AB4;
-
-NET sram_flash_addr<16> LOC = AB3;
-NET sram_flash_addr<15> LOC = AA4;
-NET sram_flash_addr<14> LOC = AA3;
-NET sram_flash_addr<13> LOC = W5;
-NET sram_flash_addr<12> LOC = W6;
-NET sram_flash_addr<11> LOC = W3;
-NET sram_flash_addr<10> LOC = AF3;
-NET sram_flash_addr<9>  LOC = AE3;
-NET sram_flash_addr<8>  LOC = AD2;
-NET sram_flash_addr<7>  LOC = AD1;
-NET sram_flash_addr<6>  LOC = AC2;
-NET sram_flash_addr<5>  LOC = AC1;
-NET sram_flash_addr<4>  LOC = AB2;
-NET sram_flash_addr<3>  LOC = AB1;
-NET sram_flash_addr<2>  LOC = AA1;
-NET sram_flash_addr<1>  LOC = Y2;
-NET sram_flash_addr<0>  LOC = Y1;
-NET sram_flash_data<31> LOC = F14;
-NET sram_flash_data<30> LOC = F13;
-NET sram_flash_data<29> LOC = F12;
-NET sram_flash_data<28> LOC = F11;
-NET sram_flash_data<27> LOC = F16;
-NET sram_flash_data<26> LOC = F15;
-NET sram_flash_data<25> LOC = D14;
-NET sram_flash_data<24> LOC = D13;
-NET sram_flash_data<23> LOC = D15;
-NET sram_flash_data<22> LOC = E14;
-NET sram_flash_data<21> LOC = C11;
-NET sram_flash_data<20> LOC = D11;
-NET sram_flash_data<19> LOC = D16;
-NET sram_flash_data<18> LOC = C16;
-NET sram_flash_data<17> LOC = E13;
-NET sram_flash_data<16> LOC = D12;
-NET sram_flash_data<15> LOC = AA14;
-NET sram_flash_data<14> LOC = AB14;
-NET sram_flash_data<13> LOC = AC12;
-NET sram_flash_data<12> LOC = AC11;
-NET sram_flash_data<11> LOC = AA16;
-NET sram_flash_data<10> LOC = AA15;
-NET sram_flash_data<9>  LOC = AB13;
-NET sram_flash_data<8>  LOC = AA13;
-NET sram_flash_data<7>  LOC = AC14;
-NET sram_flash_data<6>  LOC = AD14;
-NET sram_flash_data<5>  LOC = AA12;
-NET sram_flash_data<4>  LOC = AA11;
-NET sram_flash_data<3>  LOC = AC16;
-NET sram_flash_data<2>  LOC = AC15;
-NET sram_flash_data<1>  LOC = AC13;
-NET sram_flash_data<0>  LOC = AD13;
-NET sram_cen            LOC = V7;
-NET sram_flash_oe_n     LOC = AC6;
-NET sram_flash_we_n     LOC = AB6;
-NET sram_bw<3>          LOC = Y3; #Y4; 
-NET sram_bw<2>          LOC = Y4; #Y3;
-NET sram_bw<1>          LOC = Y5; #Y6;
-NET sram_bw<0>          LOC = Y6; #Y5;
-NET flash_ce            LOC = W7;
-NET sram_adv_ld_n       LOC = W4;
-NET sram_mode           LOC = V26;
-
-NET sram_clk           IOSTANDARD = LVCMOS33;
-NET sram_clk           DRIVE = 16;
-NET sram_clk           SLEW = FAST;
-NET sram_clk_fb        IOSTANDARD = LVCMOS33;
-
-NET flash_a23          IOSTANDARD = LVDCI_33;
-NET flash_a23  SLEW = FAST;
-NET flash_a23  DRIVE = 8;
-
-NET sram_mode          IOSTANDARD = LVDCI_33;
-NET sram_mode SLEW = FAST;
-NET sram_mode DRIVE = 8;
-
-NET sram_flash_addr<*> IOSTANDARD = LVDCI_33;
-NET sram_flash_addr<*>  SLEW = FAST;
-NET sram_flash_addr<*>  DRIVE = 8;
-
-NET sram_flash_data<*> IOSTANDARD = LVCMOS33;
-NET sram_flash_data<*> DRIVE = 12;
-NET sram_flash_data<*> SLEW = FAST;
-NET sram_flash_data<*> PULLDOWN;
-
-NET sram_flash_oe_n    IOSTANDARD = LVDCI_33;
-NET sram_flash_oe_n SLEW = FAST;
-NET sram_flash_oe_n DRIVE = 8;
-
-NET sram_flash_we_n    IOSTANDARD = LVDCI_33;
-NET sram_flash_we_n SLEW = FAST;
-NET sram_flash_we_n DRIVE = 8;
-
-NET sram_bw<*>         IOSTANDARD = LVDCI_33;
-NET sram_bw<*> SLEW = FAST;
-NET sram_bw<*> DRIVE = 8;
-
-NET flash_ce           IOSTANDARD = LVDCI_33;
-NET flash_ce SLEW = FAST;
-NET flash_ce DRIVE = 8;
-
-NET sram_cen           IOSTANDARD = LVDCI_33;
-NET sram_cen SLEW = FAST;
-NET sram_cen DRIVE = 8;
-
-NET sram_adv_ld_n      IOSTANDARD = LVDCI_33;
-NET sram_adv_ld_n SLEW = FAST;
-NET sram_adv_ld_n DRIVE = 8;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Expansion Header GPIO
-#------------------------------------------------------------------------------
-
-NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64
-NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62
-NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8
-NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58
-NET gpio_exp_hdr1<27> LOC = W20;  # HDR1_44
-NET gpio_exp_hdr1<26> LOC = W21;  # HDR1_48
-NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14
-NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20
-NET gpio_exp_hdr1<23> LOC = W22;  # HDR1_46
-NET gpio_exp_hdr1<22> LOC = V21;  # HDR1_56
-NET gpio_exp_hdr1<21> LOC = V22;  # HDR1_54
-NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16
-NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18
-NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34
-NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6
-NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30
-NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4
-NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24
-NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60
-NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10
-NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22
-NET gpio_exp_hdr1<10> LOC = Y25;  # HDR1_40
-NET gpio_exp_hdr1<9>  LOC = Y26;  # HDR1_38
-NET gpio_exp_hdr1<8>  LOC = W26;  # HDR1_50
-NET gpio_exp_hdr1<7>  LOC = AB23; # HDR1_12
-NET gpio_exp_hdr1<6>  LOC = Y24;  # HDR1_26
-NET gpio_exp_hdr1<5>  LOC = AB24; # HDR1_32
-NET gpio_exp_hdr1<4>  LOC = W25;  # HDR1_52
-NET gpio_exp_hdr1<3>  LOC = AC24; # HDR1_2
-NET gpio_exp_hdr1<2>  LOC = AC25; # HDR1_36
-NET gpio_exp_hdr1<1>  LOC = V20;  # HDR1_42
-NET gpio_exp_hdr1<0>  LOC = AA24; # HDR1_28
-NET gpio_exp_hdr1<*> TIG;
-NET gpio_exp_hdr1<*> PULLDOWN;
-
-NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40
-NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38
-NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32
-NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30
-NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44
-NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42
-NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24
-NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22
-NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48
-NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46
-NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64
-NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62
-NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16
-NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14
-NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36
-NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34
-NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52
-NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50
-NET gpio_exp_hdr2<13> LOC = Y17;  # HDR2_56
-NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54
-NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60
-NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58
-NET gpio_exp_hdr2<9>  LOC = Y22;  # HDR2_8
-NET gpio_exp_hdr2<8>  LOC = Y23;  # HDR2_6
-NET gpio_exp_hdr2<7>  LOC = W23;  # HDR2_12
-NET gpio_exp_hdr2<6>  LOC = W24;  # HDR2_10
-NET gpio_exp_hdr2<5>  LOC = Y20;  # HDR2_20
-NET gpio_exp_hdr2<4>  LOC = Y21;  # HDR2_18
-NET gpio_exp_hdr2<3>  LOC = Y19;  # HDR2_28
-NET gpio_exp_hdr2<2>  LOC = W19;  # HDR2_26
-NET gpio_exp_hdr2<1>  LOC = AA18; # HDR2_4
-NET gpio_exp_hdr2<0>  LOC = Y18;  # HDR2_2
-NET gpio_exp_hdr2<*> TIG;
-NET gpio_exp_hdr2<*> PULLDOWN;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Character LCD GPIO
-#------------------------------------------------------------------------------
-
-NET gpio_char_lcd<6> LOC = AE13; # LCD_E
-NET gpio_char_lcd<5> LOC = AC17; # LCD_RS
-NET gpio_char_lcd<4> LOC = AB17; # LCD_RW
-NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7
-NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6
-NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5
-NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4
-NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
-NET gpio_char_lcd<*> TIG;
-NET gpio_char_lcd<*> PULLDOWN;

lib/CPUs/JCpu/asm/dctest.jsm

@@ -1,56 +0,0 @@
-; -------------------------------------------------	
-;			PROJECT	"dctest"
-; -------------------------------------------------	
-
-include "../../../jasm/cregs.inc.jsm"
-
-; -------------------------------------------------	
-				xmem
-				org		4
-konst:			dc		0x01, 0x12,"A"
-gap1:			db		16
-mesg:			dc		"Hallo", 13,0x0A, 0
-name:			dc		"Jens",0
-msg1:			dc		"Welcome to JASM CPU",0
-msg2:			dc		"Ready",0
-msg3:			dc		"Testing",0
-msg4:			dc		"Passed",0
-msg5:			dc		"Error",0
-crlf:			dc		0x0D, 0x0A
-
-				org		0x00
-shit:			db		4	
-
-				cmem	0
-				org		8
-cram1:			db		16
-cram2:			db		6
-cram3:			db		4
-
-				cmem	1
-cram4:			db		8
-cram5:			db		8
-				org		0x20
-cram6:			db		8
-cram7:			db		4
-
-reg_revision:	equ		0x00			
-reg_testid:		equ		0x01			
-
-; -------------------------------------------------	
-				code
-				org		0x000
-reset:			jmp		start
-
-; -------------------------------------------------	
-				org		0x001
-int_vec:		jmp		isr
-
-; -------------------------------------------------	
-				org		0x010
-			
-start:			jmp		start
-
-; -------------------------------------------------	
-isr:			reti
-

lib/CPUs/JCpu/asm/dctest.tcl

@@ -1,212 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-# Assembled from dctest.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
-# User 1
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
-
-# 0x000: JMP 0x010
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
-
-# 0x001: JMP 0x011
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011"
-
-# 0x002:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
-
-# 0x003:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
-
-# 0x004:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
-
-# 0x005:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
-
-# 0x006:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
-
-# 0x007:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
-
-# 0x008:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
-
-# 0x009:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
-
-# 0x00A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
-
-# 0x00B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
-
-# 0x00C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
-
-# 0x00D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
-
-# 0x00E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
-
-# 0x00F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
-
-# 0x010: JMP 0x010
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010"
-
-# 0x011: RETI
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000"
-
-# Assembled from dctest.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
-# User 2
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
-
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A"
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit

lib/CPUs/JCpu/asm/itest.jsm

@@ -1,858 +0,0 @@
-; -------------------------------------------------	
-;			PROJECT	"itest"
-; -------------------------------------------------	
-
-include "../../../jasm/cregs.inc.jsm"
-
-; -------------------------------------------------	
-				xmem
-msg:			dc		"Hallo", 0
-xram:			db		256
-
-				cmem	0
-cram:			db		256
-
-reg_revision:	equ		0x00			
-reg_testid:		equ		0x01			
-
-; -------------------------------------------------	
-			code
-			org		0x000
-reset:		jmp		start
-
-; -------------------------------------------------	
-			org		0x001
-int_vec:	jmp		isr
-
-; -------------------------------------------------	
-			org		0x010
-			
-start:		call	init
-			cin		R0, (cpu_revision)
-			xout	(reg_revision), R0
-			
-			; Test 0
-			call	test0
-			
-			; Test 1
-			mov		R0, 1
-			xout	(reg_testid), R0
-			call	test1
-			
-			; Test 2
-			mov		R0, 2
-			xout	(reg_testid), R0
-			call	test2
-
-			; Test 3
-			mov		R0, 3
-			xout	(reg_testid), R0
-			call	test3
-
-			; Test 4
-			mov		R0, 4
-			xout	(reg_testid), R0
-			call	test4
-
-			; Test 5
-			mov		R0, 5
-			xout	(reg_testid), R0
-			call	test5
-
-			; Test 6
-			mov		R0, 6
-			xout	(reg_testid), R0
-			call	test6
-
-			; Test 7
-			mov		R0, 7
-			xout	(reg_testid), R0
-			call	test7
-
-			; Test 8
-			mov		R0, 8
-			xout	(reg_testid), R0
-			call	test8
-
-			; Test 9
-			mov		R0, 9
-			xout	(reg_testid), R0
-			call	test9
-			
-			; Test 10
-			mov		R0, 10
-			xout	(reg_testid), R0
-			call	test10
-
-			; Test 11
-			mov		R0, 11
-			xout	(reg_testid), R0
-			call	test11
-
-			; Test 12
-			mov		R0, 12
-			xout	(reg_testid), R0
-			call	test12
-
-			; End of test
-			mov		R0, 0xFF
-			xout	(reg_testid), R0
-			
-			jmp		ok
-
-; -------------------------------------------------	
-init:		mov		R0, 0
-			mov		R1, 0
-			mov		R2, 0
-			mov		R3, 0
-			mov		R4, 0
-			mov		R5, 0
-			mov		R6, 0
-			mov		R7, 0
-			mov		R8, 0
-			mov		R9, 0
-			mov		R10, 0
-			mov		R11, 0
-			mov		R12, 0
-			mov		R13, 0
-			mov		R14, 0
-			mov		R15, 0
-			ret
-
-; -------------------------------------------------	
-; MOV|R|K
-; MOV|R|R
-test0:		mov		R0, 0x10
-			cmp		R0, 0x10
-			jne		error
-			add		R0, 1
-
-			mov		R1, R0
-			cmp		R1, 0x11
-			jne		error
-			add		R1, 1
-
-			mov		R2, R1
-			cmp		R2, 0x12
-			jne		error
-			add		R2, 1
-
-			mov		R3, R2
-			cmp		R3, 0x13
-			jne		error
-			add		R3, 1
-
-			mov		R4, R3
-			cmp		R4, 0x14
-			jne		error
-			add		R4, 1
-
-			mov		R5, R4
-			cmp		R5, 0x15
-			jne		error
-			add		R5, 1
-
-			mov		R6, R5
-			cmp		R6, 0x16
-			jne		error
-			add		R6, 1
-
-			mov		R7, R6
-			cmp		R7, 0x17
-			jne		error
-			add		R7, 1
-
-			mov		R8, R7
-			cmp		R8, 0x18
-			jne		error
-			add		R8, 1
-
-			mov		R9, R8
-			cmp		R9, 0x19
-			jne		error
-			add		R9, 1
-
-			mov		R10, R9
-			cmp		R10, 0x1A
-			jne		error
-			add		R10, 1
-
-			mov		R11, R10
-			cmp		R11, 0x1B
-			jne		error
-			add		R11, 1
-
-			mov		R12, R11
-			cmp		R12, 0x1C
-			jne		error
-			add		R12, 1
-
-			mov		R13, R12
-			cmp		R13, 0x1D
-			jne		error
-			add		R13, 1
-
-			mov		R14, R13
-			cmp		R14, 0x1E
-			jne		error
-			add		R14, 1
-
-			mov		R15, R14
-			cmp		R15, 0x1F
-			jne		error
-			add		R15, 1
-			
-			ret
-
-; -------------------------------------------------	
-; Instruction test
-; TST|R
-; CMP|R|K
-; JNZ|K
-; JC|K
-; JNE|K
-; JLT|K
-; JGT|K
-; JLE|K
-; JGE|K
-; JMP|K
-test1:		mov		R0, 0			; R0 <= 0
-			tst		R0
-			jnz		error	
-			jc		error	
-			cmp		R0, 0	
-			jne		error	
-			jlt		error	
-			jgt		error
-			jle		t1_ok10
-			jmp		error
-
-t1_ok10:	jeq		t1_ok20
-			jmp		error
-			
-t1_ok20:	jge		t1_ok30
-			jmp		error
-			
-t1_ok30:	cmp		R0, 0x55
-			jeq		error	
-			jlt		t1_ok40
-			jmp		error
-			
-t1_ok40:	jle		t1_ok50
-			jmp		error
-			
-t1_ok50:	jge		error
-			jgt		error
-			
-			mov		R0, 0x55		; R0 <= 0xAA
-			tst		R0
-			jz		error	
-			jc		error	
-			
-			cmp		R0, 0xAA
-			jeq		error	
-			jne		t1_ok60
-			jmp		error
-
-t1_ok60:	jlt		t1_ok70	
-			jmp		error
-
-t1_ok70:	jle		t1_ok80
-			jmp		error
-
-t1_ok80:	jgt		error
-
-			cmp		R0, 0x55
-			jeq		t1_ok90
-			jmp		error
-			
-t1_ok90:	jne		error
-			jlt		error
-			
-			jle		t1_ok100
-			jmp		error
-
-t1_ok100:	jgt		error
-			jge		t1_ok110
-			jmp		error
-			
-t1_ok110:	mov		R0, 0xAA		; R0 <= 0x55
-			tst		R0
-			jz		error	
-			jc		error	
-			
-			cmp		R0, 0x55
-			jeq		error	
-			jne		t1_ok120
-			jmp		error
-
-t1_ok120:	jgt		t1_ok130	
-			jmp		error
-
-t1_ok130:	jge		t1_ok140
-			jmp		error
-
-t1_ok140:	jlt		error
-			jle		error
-
-			ret
-			
-; -------------------------------------------------	
-; ADD|R|K
-; ADDC|R|K
-; ToDo: ADD|R|R
-; ToDo: ADDC|R|R
-; CMP|R|R
-test2:		mov		R0, 0
-			mov		R1, 0
-			mov		R2, R0
-			mov		R3, R1
-
-t2_loop:	add		R0, 0x01
-			addc	R1, 0x00
-			add		R2, 1
-			cmp		R2, 0
-			jne		t2_L1
-			add		R3, 1
-			cmp		R3, 0x02
-t2_L1:		jne		t2_loop
-			cmp		R0, R2
-			jne		error
-			cmp		R1, R3
-			jne		error
-			mov		R0, 0
-
-			ret
-
-; -------------------------------------------------	
-; SUB|R|K
-; SUBC|R|K
-; ToDo: SUB|R|R
-; ToDo: SUBC|R|R
-; CMP|R|R
-test3:		mov		R0, 0x00
-			mov		R1, 0x03
-			mov		R2, R0
-			mov		R3, R1
-
-t3_loop:	sub		R0, 0x01
-			subc	R1, 0x00
-			sub		R2, 1
-			cmp		R2, 0xFF
-			jne		t3_L1
-			sub		R3, 1
-			cmp		R3, 0x00
-t3_L1:		jne		t3_loop
-			cmp		R0, R2
-			jne		error
-			cmp		R1, R3
-			jne		error
-			mov		R0, 0
-
-			ret
-; -------------------------------------------------	
-; SUB|K|R
-; SUB|R|R
-; SUBC|R|R
-; SUBC|K|R
-; CMP|R|R
-test4:		mov		R0, 0x03
-			mov		R1, 0x05
-			sub		0x05, R0
-			sub		R1, 0x03
-			cmp		R0, R1
-			jne		error
-			mov		R0, 0x03
-			mov		R1, 0x05
-			sub		R0, R1
-			subc	0, R0
-			cmp		R0, 0x01
-			jne		error
-			add		R0, 0	
-			subc	R1, R0
-			cmp		R1, 0x04
-			jne		error
-			mov		R0, 0
-
-			ret
-						
-; -------------------------------------------------	
-; MOVC|R|Ri
-; MOVC|R|Ki
-; MOVC|Ri|R
-; MOVC|Ri|K
-; MOVC|Ki|R
-test5:		mov		R0, 1
-			movc	(cram+0x5A), R0
-			dec		R0			
-			movc	(cram+0), R0
-			movc	R1, (cram+0x5A)
-			movc	(R1), 0xA5
-			movc	R0, (R1)
-			movc	R1, (R1)
-			add		R1, 0xFF-0xA5
-			movc	R0, (R1)
-t5_loop1:	movc	(R0), R0
-			movc	R2, (R0)
-			cmp		R2, R0
-			jne		error
-			movc	(R2), R1
-			movc	R2, (R2)
-			cmp		R2, R1
-			jne		error
-			dec		R1
-			inc		R0
-			jnz		t5_loop1
-			
-			ret
-
-; -------------------------------------------------	
-; MOVX|R|Ri
-; MOVX|R|Ki
-; MOVX|Ri|R
-; MOVX|Ri|K
-; MOVX|Ki|R
-test6:		mov		R0, 1
-			movx	(xram+0x5A), R0
-			dec		R0			
-			movx	(xram+0), R0
-			movx	R1, (xram+0x5A)
-			movx	(R1), 0xA5
-			movx	R0, (R1)
-			movx	R1, (R1)
-			add		R1, 0xFF-0xA5
-			movx	R0, (R1)
-t6_loop1:	movx	(R0), R0
-			movx	R2, (R0)
-			cmp		R2, R0
-			jne		error
-			movx	(R2), R1
-			movx	R2, (R2)
-			cmp		R2, R1
-			jne		error
-			dec		R1
-			inc		R0
-			jnz		t6_loop1
-			
-			ret
-
-; -------------------------------------------------	
-; PUSH|R
-; POP|R
-test7:		mov		R0, 0xAA
-			mov		R1, 0
-t7_loop1:	push	R0
-			inc		R0
-			dec		R1
-			jnz		t7_loop1
-t7_loop2:	pop		R0
-			dec		R1
-			jnz		t7_loop2
-			cmp		R0, 0xAA
-			jne		error
-			
-			ret
-
-; -------------------------------------------------	
-; JMP|K
-; CALL|K
-; RET
-test8:		mov		R0, 0x55
-			push	R0
-			mov		R0, 0
-			mov		R1, 0xFF
-			call	t8_rec
-			pop		R0
-			cmp		R0, 0x55
-			jne		error
-
-			; Stack manipulations 1
-			mov		R0, return1'high
-			mov		R1, return1'low
-			cout	(cpu_stack_high), R0
-			push	R1
-
-			mov		R0, init'high
-			mov		R1, init'low
-			cout	(cpu_stack_high), R0
-			push	R1
-			ret
-			
-			; Stack manipulations 2
-return1:	mov		R0, return2'high
-			mov		R1, return2'low
-			cout	(cpu_stack_high), R0
-			push	R1
-
-			mov		R0, init'high
-			mov		R1, init'low
-			cout	(cpu_stack_high), R0
-			push	R1
-return2:	ret
-
-t8_rec:		cmp		R0, R1
-			jeq		ex_t8_rec
-			inc		R0
-			jmp		t8_rstub
-ex_t8_rec:	dec		R0
-			dec		R1
-			ret
-
-t8_rstub:	call	t8_rec
-			jmp		ex_t8_rec
-
-; -------------------------------------------------	
-; SWAP|R
-; SHL|R  
-; SHR|R  
-; ROL|R  
-; ROR|R  
-; ROLC|R 
-; RORC|R 
-test9:		mov		R0, 0xA5	; SWAP test
-			mov		R1, 0x5A
-			swap	R0
-			cmp		R0, 0x5A
-			jne		error
-			swap	R0
-			cmp		R0, 0xA5
-			jne		error
-			mov		R0, 0xD2
-			swap	R0
-			cmp		R0, 0x2D
-			jne		error
-			swap	R1
-			cmp		R0, 0x2D
-			jne		error
-			cmp		R1, 0xA5
-			jne		error
-			
-			mov		R0, 0x2D
-			shl		R0			; SHL test
-			cmp		R0, 0x5A
-			jne		error
-			shl		R0
-			cmp		R0, 0xB4
-			jne		error
-			shl		R0
-			cmp		R0, 0x68
-			jne		error
-			shl		R0
-			cmp		R0, 0xD0
-			jne		error
-			shl		R0
-			cmp		R0, 0xA0
-			jne		error
-			shl		R0
-			cmp		R0, 0x40
-			jne		error
-			shl		R0
-			cmp		R0, 0x80
-			jne		error
-			shl		R0
-			cmp		R0, 0x00
-			jne		error
-
-			mov		R1, 0x84
-			shr		R1			; SHR test
-			cmp		R1, 0x42
-			jne		error
-			shr		R1
-			cmp		R1, 0x21
-			jne		error
-			shr		R1
-			cmp		R1, 0x10
-			jne		error
-			shr		R1
-			cmp		R1, 0x08
-			jne		error
-			shr		R1
-			cmp		R1, 0x04
-			jne		error
-			shr		R1
-			cmp		R1, 0x02
-			jne		error
-			shr		R1
-			cmp		R1, 0x01
-			jne		error
-			shr		R1
-			cmp		R1, 0x00
-			jne		error
-
-			mov		R0, 0xC5	; ROL test
-			rol		R0			
-			cmp		R0, 0x8B
-			jne		error
-			rol		R0			
-			cmp		R0, 0x17
-			jne		error
-			rol		R0			
-			cmp		R0, 0x2E
-			jne		error
-			rol		R0			
-			cmp		R0, 0x5C
-			jne		error
-			rol		R0			
-			cmp		R0, 0xB8
-			jne		error
-			rol		R0			
-			cmp		R0, 0x71
-			jne		error
-			rol		R0			
-			cmp		R0, 0xE2
-			jne		error
-			rol		R0			
-			cmp		R0, 0xC5
-			jne		error
-
-			mov		R1, 0x63	; ROR test
-			ror		R1
-			cmp		R1, 0xB1
-			jne		error
-			ror		R1
-			cmp		R1, 0xD8
-			jne		error
-			ror		R1
-			cmp		R1, 0x6C
-			jne		error
-			ror		R1
-			cmp		R1, 0x36
-			jne		error
-			ror		R1
-			cmp		R1, 0x1B
-			jne		error
-			ror		R1
-			cmp		R1, 0x8D
-			jne		error
-			ror		R1
-			cmp		R1, 0xC6
-			jne		error
-			ror		R1
-			cmp		R1, 0x63
-			jne		error
-
-
-			xor		R0, R0		; ROLC generate
-			mov		R0, 0xC5	
-			rolc	R0		
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-
-			cmp		R0, 0xC5	; ROLC verify
-			jne		error
-			pop		R0
-			cmp		R0, 0x62
-			jne		error
-			pop		R0
-			cmp		R0, 0xB1
-			jne		error
-			pop		R0
-			cmp		R0, 0x58
-			jne		error
-			pop		R0
-			cmp		R0, 0xAC
-			jne		error
-			pop		R0
-			cmp		R0, 0x56
-			jne		error
-			pop		R0
-			cmp		R0, 0x2B
-			jne		error
-			pop		R0
-			cmp		R0, 0x15
-			jne		error
-			pop		R0
-			cmp		R0, 0x8A
-			jne		error
-
-			xor		R1, R1		; RORC generate
-			mov		R1, 0x63
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-
-			cmp		R1, 0x63	; RORC verify
-			jne		error
-			pop		R1
-			cmp		R1, 0xC6
-			jne		error
-			pop		R1
-			cmp		R1, 0x8C
-			jne		error
-			pop		R1
-			cmp		R1, 0x19
-			jne		error
-			pop		R1
-			cmp		R1, 0x33
-			jne		error
-			pop		R1
-			cmp		R1, 0x66
-			jne		error
-			pop		R1
-			cmp		R1, 0xCC
-			jne		error
-			pop		R1
-			cmp		R1, 0x98
-			jne		error
-			pop		R1
-			cmp		R1, 0x31
-			jne		error
-
-			ret
-			
-; -------------------------------------------------
-; AND|R|R
-; AND|R|K
-; OR|R|R 
-; OR|R|K 
-; XOR|R|R
-; XOR|R|K
-test10:		mov		R0, 0xA5	; AND
-			swap	R0
-			push	R0
-			and		R0, 0x0F
-			cmp		R0, 0x0A
-			jne		error
-			pop		R0
-			push	R0
-			and		R0, 0x0F
-			cmp		R0, 0x0A
-			pop		R1
-			jne		error
-			swap	R1
-			mov		R2, 0x0F
-			and		R1, R2
-			cmp		R1, 0x05
-			jne		error
-			
-			mov		R0, 0x05	; OR
-			mov		R2, 0xA0
-			swap	R0
-			or		R2, R0
-			cmp		R2, 0xF0
-			jne		error
-			swap	R0
-			or		R0, 0x50
-			cmp		R0, 0x55
-			jne		error
-			
-			mov		R1, 0x01
-			mov		R0, 0x01
-			xor		R0, 0x01
-			jnz		error
-			xor		R0, R1
-			cmp		R0, 0x01
-			jne		error
-			
-			ret
-			
-; -------------------------------------------------	
-test11:
-			mov		R0, 0x03
-			cout	(cpu_int_ctrl), R0
-			
-			xin		R0, (2)
-			or		R0, 1
-			xout	(2), R0
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			xin		R0, (2)
-			and		R0, 0xFE
-			xout	(2), R0
-			nop
-			nop
-			nop
-			nop
-			
-			cin		R0, (cpu_int_ctrl)
-			or		R0, 0x80
-			cout	(cpu_int_ctrl), R0
-			nop
-			cin		R0, (cpu_int_ctrl)
-			or		R0, 0x80
-			cout	(cpu_int_ctrl), R0
-			nop
-			cin		R0, (cpu_int_ctrl)
-			or		R0, 0x80
-			cout	(cpu_int_ctrl), R0
-			nop
-			cin		R0, (cpu_int_ctrl)
-			or		R0, 0x80
-			cout	(cpu_int_ctrl), R0
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			ret
-
-; -------------------------------------------------	
-; Tests clrc, setc
-test12:		sub		R0, 0
-			jc		error
-			setc
-			jnc		error
-			nop
-			sub		R0, 0
-			jc		error
-			
-			mov		R0, 0
-			clrc
-			jc		error
-			setc
-			jnc		error
-			nop
-			clrc
-			jc		error
-			ret
-
-; -------------------------------------------------	
-isr:		inc		R14
-			reti
-
-; -------------------------------------------------	
-			org		0x3FF
-error:		jmp		error
-
-; -------------------------------------------------	
-			org		0x2FF
-ok:			jmp		ok
-
-; -------------------------------------------------	
-			

lib/CPUs/JCpu/asm/make

@@ -1,50 +0,0 @@
-#!/bin/sh
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: rom-file generation for cpu_core
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-TARGET=$2
-DSTDIR=$1
-
-JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
-
-$JASM_HOME/jasm.rb $TARGET.jsm
-
-irom_tcl_snippet="$TARGET.irom.tcl.snip"
-irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
-irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
-xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
-xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
-xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
-
-$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
-$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
-
-$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
-$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
-
-cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
-cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
-$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
-
-rm -f *.snip

lib/CPUs/JCpu/asm/mul8x8.jsm

@@ -1,29 +0,0 @@
-; -------------------------------------------------
-; Constants
-; -------------------------------------------------
-
-; Chip register
-include "../../../jasm/cregs.inc.jsm"
-
-; -------------------------------------------------
-; Program
-; -------------------------------------------------
-				code
-				org		0x000
-reset:			jmp		init
-						
-; -------------------------------------------------
-; Main
-; -------------------------------------------------
-init:			mov		R0, 0x45
-				mov		R1, 0xF5
-				
-				call	mul8x8
-stop:			jmp		stop
-
-
-; -------------------------------------------------
-include "../../../jasm/mul8x8.inc.jsm"
-				
-				
-				

lib/CPUs/JCpu/asm/mul8x8.tcl

@@ -1,154 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-# Assembled from mul8x8.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
-# User 1
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
-
-# 0x000: JMP 0x001
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001"
-
-# 0x001: MOV R00, 0x45
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450"
-
-# 0x002: MOV R01, 0xF5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51"
-
-# 0x003: CALL 0x005
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005"
-
-# 0x004: JMP 0x004
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004"
-
-# 0x005: PUSH R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002"
-
-# 0x006: PUSH R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003"
-
-# 0x007: PUSH R04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004"
-
-# 0x008: MOV R04, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014"
-
-# 0x009: MOV R01, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001"
-
-# 0x00A: MOV R02, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002"
-
-# 0x00B: MOV R03, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003"
-
-# 0x00C: CMP R04, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014"
-
-# 0x00D: JEQ 0x015
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015"
-
-# 0x00E: SHR R04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004"
-
-# 0x00F: JNC 0x012
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012"
-
-# 0x010: ADD R02, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002"
-
-# 0x011: ADDC R03, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013"
-
-# 0x012: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000"
-
-# 0x013: ROLC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001"
-
-# 0x014: JMP 0x00C
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C"
-
-# 0x015: ADD R00, R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020"
-
-# 0x016: ADDC R01, R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031"
-
-# 0x017: POP R04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004"
-
-# 0x018: POP R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
-
-# 0x019: POP R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002"
-
-# 0x01A: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000"
-
-# Assembled from mul8x8.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
-# User 2
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
-
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit

lib/CPUs/JCpu/asm/reti_issue.jsm

@@ -1,50 +0,0 @@
-; -------------------------------------------------
-; Constants
-; -------------------------------------------------
-
-; Chip register
-cpu_revision:	equ		0x00	; RO
-cpu_control:	equ		0x01	; R/W
-cpu_status:		equ		0x02	; RO
-cpu_int_ctrl:	equ		0x03	; R/W
-
-; -------------------------------------------------
-; Program
-; -------------------------------------------------
-				code
-reset:			jmp		init
-		
-				org		0x001
-;				nop
-				reti
-				
-; -------------------------------------------------
-; Main
-; -------------------------------------------------
-init:			mov		R0, 0x05
-				cout	(cpu_int_ctrl), R0
-				mov		R0, 0x00
-loop:			nop
-				inc		R0
-				nop
-				call	subr
-				nop
-				push	R3
-				nop
-				push	R2
-				nop
-				push	R1
-				nop
-				push	R0
-				nop
-				pop		R0
-				nop
-				pop		R1
-				nop
-				pop		R2
-				nop
-				pop		R3
-				nop
-				jmp		loop
-
-subr:			ret				

lib/CPUs/JCpu/asm/reti_issue.tcl

@@ -1,157 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-# Assembled from reti_issue.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
-# User 1
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
-
-# 0x000: JMP 0x002
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
-
-# 0x001: RETI
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
-
-# 0x002: MOV R00, 0x05
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050"
-
-# 0x003: COUT (0x03), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030"
-
-# 0x004: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000"
-
-# 0x005: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
-
-# 0x006: INC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010"
-
-# 0x007: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
-
-# 0x008: CALL 0x01B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B"
-
-# 0x009: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
-
-# 0x00A: PUSH R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003"
-
-# 0x00B: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
-
-# 0x00C: PUSH R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002"
-
-# 0x00D: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
-
-# 0x00E: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001"
-
-# 0x00F: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
-
-# 0x010: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000"
-
-# 0x011: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000"
-
-# 0x012: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000"
-
-# 0x013: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000"
-
-# 0x014: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001"
-
-# 0x015: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000"
-
-# 0x016: POP R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002"
-
-# 0x017: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000"
-
-# 0x018: POP R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
-
-# 0x019: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000"
-
-# 0x01A: JMP 0x005
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005"
-
-# 0x01B: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000"
-
-# Assembled from reti_issue.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
-# User 2
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
-
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit

lib/CPUs/JCpu/sim/tb_cpu.fdo

@@ -1,22 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/chipreg.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/itest_irom.vhdl"
-vcom -explicit  -93 "../src/tb_cpu_itest.vhd"
-vsim -t 1ps   -lib work tb_cpu
-do {tb_cpu.wdo}
-view wave
-view structure
-view signals
-run 50us

lib/CPUs/JCpu/sim/tb_cpu.wdo

@@ -1,107 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cpu/rst
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Logic /tb_cpu/ce
-add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
-add wave -noupdate -format Logic /tb_cpu/int_in
-add wave -noupdate -format Logic /tb_cpu/int_ack
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
-add wave -noupdate -format Logic /tb_cpu/xmem_we
-add wave -noupdate -format Logic /tb_cpu/xmem_re
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
-add wave -noupdate -format Logic /tb_cpu/uut/io_sel
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -divider CPU
-add wave -noupdate -format Literal /tb_cpu/reg
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
-add wave -noupdate -format Literal /tb_cpu/uut/status_reg
-add wave -noupdate -format Literal /tb_cpu/uut/ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
-add wave -noupdate -format Literal /tb_cpu/uut/alu_status
-add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
-add wave -noupdate -format Logic /tb_cpu/uut/pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/stk_we
-add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
-add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
-add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
-add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
-add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
-add wave -noupdate -format Logic /tb_cpu/uut/status_save
-add wave -noupdate -format Logic /tb_cpu/uut/status_restore
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
-add wave -noupdate -divider Stack
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
-add wave -noupdate -divider Chipram
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
-add wave -noupdate -divider Sequencer
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
-add wave -noupdate -divider {Chip register}
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
-add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {136355 ps} 0}
-configure wave -namecolwidth 166
-configure wave -valuecolwidth 101
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {93532 ps} {206468 ps}

lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo

@@ -1,21 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/cpu_embedded.vhd"
-vcom -explicit  -93 "../src/tb_cpu_embedded.vhd"
-vcom -explicit  -93 "../src/itest_irom.vhdl"
-vsim -t 1ps   -lib work tb_cpu_embedded
-do {tb_cpu_embedded.wdo}
-view wave
-view structure
-view signals
-run 10us

lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo

@@ -1,26 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cpu_embedded/rst
-add wave -noupdate -format Logic /tb_cpu_embedded/clk
-add wave -noupdate -format Logic /tb_cpu_embedded/ce
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram
-add wave -noupdate -format Logic /tb_cpu_embedded/int_in
-add wave -noupdate -format Logic /tb_cpu_embedded/int_ack
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_data
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {2168142 ps} 0}
-configure wave -namecolwidth 143
-configure wave -valuecolwidth 101
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {10500 ns}

lib/CPUs/JCpu/sim/tb_cpu_itest.fdo

@@ -1,22 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/chipreg.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/itest_irom.vhdl"
-vcom -explicit  -93 "../src/tb_cpu_itest.vhd"
-vsim -t 1ps   -lib work tb_cpu
-do {tb_cpu_itest.wdo}
-view wave
-view structure
-view signals
-run 400us

lib/CPUs/JCpu/sim/tb_cpu_itest.wdo

@@ -1,123 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cpu/rst
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Logic /tb_cpu/ce
-add wave -noupdate -format Logic /tb_cpu/int_in
-add wave -noupdate -format Logic /tb_cpu/int_ack
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
-add wave -noupdate -format Logic /tb_cpu/xmem_we
-add wave -noupdate -format Logic /tb_cpu/xmem_re
-add wave -noupdate -format Logic /tb_cpu/xmem_wait
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg
-add wave -noupdate -format Logic /tb_cpu/uut/io_sel
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr
-add wave -noupdate -divider CPU
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
-add wave -noupdate -format Literal /tb_cpu/uut/status_reg
-add wave -noupdate -format Literal /tb_cpu/uut/ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
-add wave -noupdate -format Literal /tb_cpu/uut/alu_status
-add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
-add wave -noupdate -format Logic /tb_cpu/uut/pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
-add wave -noupdate -format Logic /tb_cpu/uut/stk_we
-add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
-add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
-add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
-add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
-add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
-add wave -noupdate -format Logic /tb_cpu/uut/status_save
-add wave -noupdate -format Logic /tb_cpu/uut/status_restore
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
-add wave -noupdate -divider Stack
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
-add wave -noupdate -divider Chipram
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
-add wave -noupdate -divider Sequencer
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
-add wave -noupdate -divider {Chip register}
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
-add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -divider {Interrup Ctrl.}
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
-add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_sampled
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {53866171 ps} 0}
-configure wave -namecolwidth 166
-configure wave -valuecolwidth 101
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {420 us}

lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo

@@ -1,22 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/chipreg.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/irom_reti_issue.vhdl"
-vcom -explicit  -93 "../src/core/tb_cpu.vhd"
-vsim -t 1ps   -lib work tb_cpu
-do {tb_cpu_reti_issue.wdo}
-view wave
-view structure
-view signals
-run 50us

lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo

@@ -1,82 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
-add wave -noupdate -divider {Chip RAM}
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
-add wave -noupdate -divider {Interrupt controller}
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_reg
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request_clr
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
-add wave -noupdate -divider PC
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst
-add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk
-add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc
-add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next
-add wave -noupdate -divider {Stack controller}
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {8115990 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {8048536 ps} {8340629 ps}

lib/CPUs/JCpu/sim/tb_mul8x8.fdo

@@ -1,21 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/cpu_embedded.vhd"
-vcom -explicit  -93 "../src/tb_cpu_embedded.vhd"
-vcom -explicit  -93 "../src/mul8x8_irom.vhdl"
-vsim -t 1ps   -lib work tb_cpu_embedded
-do {tb_mul8x8.wdo}
-view wave
-view structure
-view signals
-run 10us

lib/CPUs/JCpu/sim/tb_mul8x8.wdo

@@ -1,31 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst
-add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk
-add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr
-add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status
-add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result
-add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status
-add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {529679 ps} 0}
-configure wave -namecolwidth 143
-configure wave -valuecolwidth 101
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {9002500 ps} {10052500 ps}

lib/CPUs/JCpu/src/core/alu.vhd

@@ -1,236 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The arithmetic logic unit
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity alu is
-	Generic (
-		data_width : integer := 8
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		op_en		: in  STD_LOGIC;
-		cy_in		: in  STD_LOGIC;
-		op1_in		: in  unsigned (data_width-1 downto 0);
-		op2_in		: in  unsigned (data_width-1 downto 0);
-		opsel		: in  alu_op_t;
-		res_out		: out unsigned (data_width-1 downto 0);
-		stat_load	: in  STD_LOGIC;
-		stat_in		: in  alu_status_t;
-		stat_out	: out alu_status_t
-	);
-end alu;
-
-architecture Behavioral of alu is
-
-	signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC;
-	signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0);
-	signal status, stat_reg : alu_status_t;
-	
-	--------------------------------------------------------------------------
-	function test_zero(arg : unsigned) return STD_LOGIC is
-	variable result : STD_LOGIC;
-	begin
-			result := '0';
-			for i in arg'range loop
-				result := result or To_X01(arg(i));
-			end loop;
-
-			return not result;
-	end test_zero;
-
---------------------------------------------------------------------------
-begin
-
---------------------------------------------------------------------------
-proc_logic_func: 
-	process (op1_in, op2_in, opsel)
-	begin
-		
-		case opsel is
-		when op1_and_op2 =>
-			lf_res <= op1_in and op2_in;
-		when op1_or_op2 =>
-			lf_res <= op1_in or op2_in;
-		when op1_xor_op2 =>
-			lf_res <= op1_in xor op2_in;
-		when others =>
-			lf_res <= (others => '-');
-		end case;
-
-	end process;	
-
---------------------------------------------------------------------------
-proc_shift_func: 
-	process (op1_in, left_shift, sh_cy_in)
-	begin
-		if left_shift = '1' then
-			sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in;
-			sh_cy <= op1_in(op1_in'left);
-		else	
-			sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1);
-			sh_cy <= op1_in(op1_in'right);
-		end if;	
-		
-	end process;	
-
---------------------------------------------------------------------------
-proc_alu_out:
-	process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in)
-
-	begin
-		
-		case opsel is
-		
-		when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 =>
-			status.zero <= test_zero(res_reg);
-			status.carry <= sum_cy;
-			result <= sum_res;
-		when op1_and_op2 | op1_or_op2 | op1_xor_op2 =>
-			status.zero <= test_zero(res_reg);
-			status.carry <= stat_reg.carry;
-			result <= lf_res;
-		when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op =>
-			status.zero <= test_zero(res_reg);
-			status.carry <= sh_cy;
-			result <= sh_res;
-		when swap_op =>
-			result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2);
-			status <= stat_reg;
-		when others =>
-			result <= op2_in;
-			status.zero <= stat_reg.zero;
-			status.carry <= stat_reg.carry or cy_in;
-		end case;
-		
-	end process;
-
---------------------------------------------------------------------------
-proc_alu_in:
-	process(opsel, op1_in, stat_reg)
-
-	begin
-		
-		add_subn <= '-';
-		sum_cy_in <= '-';
-		sh_cy_in <= '-';
-		left_shift <= '-';
-
-		case opsel is
-		
-		when op1_add_op2 =>
-			sum_cy_in <= '0';
-			add_subn <= '1';
-
-		when op1_sub_op2 =>
-			sum_cy_in <= '0';
-			add_subn <= '0';
-	
-		when op1_addc_op2 => 
-			sum_cy_in <= stat_reg.carry;
-			add_subn <= '1';
-
-		when op1_subc_op2 => 
-			sum_cy_in <= stat_reg.carry;
-			add_subn <= '0';
-
-		when shl_op =>
-			sh_cy_in <= '0';
-			left_shift <= '1';
-			
-		when shr_op =>
-			sh_cy_in <= '0';
-			left_shift <= '0';
-
-		when rol_op =>
-			sh_cy_in <= op1_in(op1_in'left);
-			left_shift <= '1';
-
-		when ror_op =>
-			sh_cy_in <= op1_in(op1_in'right);
-			left_shift <= '0';
-
-		when rolc_op =>
-			sh_cy_in <= stat_reg.carry;
-			left_shift <= '1';
-
-		when rorc_op =>
-			sh_cy_in <= stat_reg.carry;
-			left_shift <= '0';
-
-		when others => null;
-
-		end case;
-		
-	end process;
-
---------------------------------------------------------------------------
-proc_res_reg:
-	process(clk, rst, op_en, stat_load, res_reg, stat_reg)
-	begin
-		if rst = '1' then
-			res_reg <= (others => '0');
-			stat_reg <= (others => '0');
-		elsif rising_edge(clk) then
-			if op_en = '1' then
-				res_reg <= result;
-				stat_reg <= status;
-			elsif stat_load = '1' then
-				stat_reg  <= stat_in;
-			end if;	
-		end if;
-		res_out <= res_reg;
-		stat_out <= stat_reg;
-
-	end process;
-
---------------------------------------------------------------------------
-alu_addsub:
-	process(op1_in, op2_in, sum_cy_in, add_subn)
-	variable sum  : unsigned(data_width+1 downto 0);
-	variable op1, op2 : unsigned(data_width+1 downto 0);
-	begin
-		if add_subn = '1' then
-			op1 := '0' & op1_in & '1';
-			op2 := '0' & op2_in & sum_cy_in;
-			sum := op1 + op2; 
-		else
-			op1 := '0' & op1_in & not sum_cy_in;
-			op2 := '0' & op2_in & '1';
-			sum := op1 - op2; 
-		end if;
-
-		-- Form sum + carry
-		sum_res <= sum(data_width downto 1);
-		sum_cy <= sum(sum'left);
-		
-	end process;	
-
---------------------------------------------------------------------------
-end Behavioral;
-

lib/CPUs/JCpu/src/core/chipram.vhd

@@ -1,85 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: On-chip RAM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity chipram is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end chipram;
-
-architecture Behavioral of chipram is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-process (clka)
-begin
-if clka'event and clka = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		dout_a <= RAM(to_integer(addr_a));
-	end if;
-end if;
-end process;
-
-process (clkb)
-begin
-if clkb'event and clkb = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-

lib/CPUs/JCpu/src/core/chipreg.vhd

@@ -1,117 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: On-Chip registers
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity chipreg is
-	Port (
-		rst			: in  STD_LOGIC; 
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		din			: in  dmem_data_t;
-		dout		: out dmem_data_t;
-		ctrl_in		: in  creg_ctrl_in_t;
-		ctrl_out	: out creg_ctrl_out_t
-	);
-end chipreg;
-
-architecture Behavioral of chipreg is
-
-	signal reg_bank_sel		: bank_sel_t;
-	signal reg_int_ctrl		: int_ctrl_in_t;
-	signal reg_stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-	signal reg_cmem_high	: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-
-begin
-
-proc_assign_ctrl_lines:
-	process (clk)
-	begin
-		if rising_edge(clk) then
-			ctrl_out.bank_sel	<= reg_bank_sel;
-			ctrl_out.int_ctrl	<= reg_int_ctrl;
-			ctrl_out.stk_high	<= reg_stk_high;
-			ctrl_out.cmem_high	<= reg_cmem_high;
-		end if;
-	end process;
-
-proc_reg_write:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			reg_stk_high <= (others => '0');
-			reg_cmem_high <= (others => '0');
-			reg_bank_sel <= (others => '0');
-			reg_int_ctrl.enable		<= '0';
-		elsif rising_edge(clk) then
-			if we = '1' then
-				case addr is
-				when X"01" =>
-					reg_bank_sel(bank_sel_t'range)	<= din(bank_sel_t'range);
-				when X"03" =>
-					reg_int_ctrl.enable		<= din(0);
-				when X"04" =>
-					reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-				when X"05" =>
-					reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-				when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-proc_reg_read:
-	process (clk)
-	begin
-		if rising_edge(clk) then
-			case addr is
-			when X"00" =>	-- Revison
-				dout <= to_unsigned(REVISION, dmem_data_t'length);
-			when X"01" =>	-- Control 0
-				dout <= (7 downto bank_sel_t'length => '0') & reg_bank_sel;
-			when X"02" =>	-- CPU status
-				dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
-			when X"03" =>	-- Interrupt control
-				dout <= "0000000" & reg_int_ctrl.enable;
-			when X"04" =>	-- Upper stack bits out
-				dout <= "0000" & reg_cmem_high;
-			when X"05" =>	-- Upper cmem bits out
-				dout <= "0000" & reg_stk_high;
-			when others => 
-				if addr(0) = '0' then
-					dout <= X"DE";
-				else
-					dout <= X"AD";
-				end if;
-			end case;
-			
-		end if;
-	end process;
-
-end Behavioral;
-

lib/CPUs/JCpu/src/core/cpu.vhd

@@ -1,564 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: JCPU top file 
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity cpu is
-	Generic (
-		use_instr_register	: boolean := false;
-		use_ctrl_rom		: boolean := true
-
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out STD_LOGIC;
-		xmem_we		: out STD_LOGIC;
-		xmem_re		: out STD_LOGIC;
-		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
-		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
-		io_sel		: out std_logic
-	);
-end cpu;
-
-architecture rtl of cpu is
-
-	COMPONENT stack_ctrl
-	GENERIC (
-		addr_width	: integer
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		push		: in  STD_LOGIC;
-		pop			: in  STD_LOGIC;
-		din			: in  inst_addr_t;
-		dout		: out inst_addr_t;
-		mem_we		: out  STD_LOGIC;
-		ptr_out		: out unsigned (addr_width-1 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT pc
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		inc			: in  STD_LOGIC;
-		load		: in  STD_LOGIC;
-		pc_in		: in  inst_addr_t;
-		pc_out		: out inst_addr_t;
-		pc_next		: out inst_addr_t
-	);
-	END COMPONENT;
-
-	COMPONENT dpath_ctrl
-	GENERIC (
-		use_rom		: boolean
-	);
-	Port (
-		inst_in		: in  inst_t;
-		iphase_in	: in  iphase_t;
-		status_in	: in  cpu_status_t;
-		ctrl_out	: out dpath_ctrl_out_t;
-		idout		: out inst_addr_t;
-		ddout		: out dmem_data_t
-	);
-	END COMPONENT;
-
-	COMPONENT int_ctrl
-	Port (
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		ctrl_in			: in  int_ctrl_in_t;
-		int_in			: in  STD_LOGIC;
-		int_exit		: in  STD_LOGIC;
-		iphase_in		: in  iphase_t;
-		int_ack_out		: out STD_LOGIC;
-		stat_save_out	: out STD_LOGIC; 
-		stat_rest_out	: out STD_LOGIC; 
-		pc_addr_out		: out inst_addr_t;
-		pc_load_out		: out STD_LOGIC;
-		stk_push_out	: out STD_LOGIC;
-		stk_pop_out		: out STD_LOGIC
-	);
-	END COMPONENT;
-
-	COMPONENT reg_dual
-	GENERIC (
-		addr_width	: integer;
-		data_width	: integer
-	);
-	Port (
-		clk			: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		ptr_a		: in  reg_ptr_t;
-		ptr_b		: in  reg_ptr_t;
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT chipram
-	GENERIC (
-		addr_width : integer;
-		data_width : integer
-	);
-	Port (
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT chipreg
-	Port (
-		rst			: in  STD_LOGIC; 
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		din			: in  dmem_data_t;
-		dout		: out dmem_data_t;
-		ctrl_in		: in  creg_ctrl_in_t;
-		ctrl_out	: out creg_ctrl_out_t
-	);
-	END COMPONENT;
-
-	COMPONENT alu
-	GENERIC (
-		data_width : integer := 8
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		op_en		: in  STD_LOGIC;
-		cy_in		: in  STD_LOGIC;
-		op1_in		: in  unsigned (data_width-1 downto 0);
-		op2_in		: in  unsigned (data_width-1 downto 0);
-		opsel		: in  alu_op_t;
-		res_out		: out unsigned (data_width-1 downto 0);
-		stat_load	: in  STD_LOGIC;
-		stat_in		: in  alu_status_t;
-		stat_out	: out alu_status_t
-	);
-	END COMPONENT;
-
-	signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0');
-	signal ctrl : dpath_ctrl_out_t;
-	signal stk_out : inst_addr_t;
-	signal stk_in : inst_addr_t;
-	signal stk_reg : inst_addr_t;
-	signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t;
-	signal iphase : iphase_t;
-	signal const_data, reg_a_dout, reg_b_dout : dmem_data_t;
-	signal reg_din : dmem_data_t;
-	signal alu_op1, alu_op2, alu_result : dmem_data_t;
-	signal alu_status : alu_status_t;
-	signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC;
-	signal ctrl_inst : inst_t;
-	signal ctrl_iphase : iphase_t;
-	signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC;
-	signal status_save, status_restore : STD_LOGIC;
-	signal creg_dout : dmem_data_t;
-	signal cmem_din, cmem_dout : inst_addr_t;
-	signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0);
-	signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0);
-	signal creg_ctrl_out : creg_ctrl_out_t;
-	signal creg_ctrl_in : creg_ctrl_in_t;
-	signal irq_out : std_logic;
-	signal xio_sel, cio_sel : std_logic; 
-	signal mem_data : dmem_data_t;
-	signal mem_addr : dmem_data_t;
-	
-begin
-	io_sel <= xio_sel;
-	instr_addr <= pc_out;
-	pc_inc <= cpu_active and ctrl.lines.pc_inc;
-	stk_addr <= '0' & stk_ptr;
-	cpu_status.alu <= alu_status;
-	creg_ctrl_in.alu <= alu_status;
-
-	xmem_dout <= mem_data;
-	xmem_addr <= mem_addr;
-	cmem_din <= creg_ctrl_out.cmem_high & mem_data;
-	cmem_addr <= '1' & creg_ctrl_out.bank_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.bank_sel'length-1, mem_addr'length)-1 downto 0);
-
---------------------------------------------------------------------
-mem_ctrl_lines:
-	process(ctrl.lines)
-	begin
-		xio_sel <= '0';
-		xmem_re <= '0';
-		xmem_we <= '0';
-		cio_sel <= '0';
-		cmem_we <= '0';
-		creg_we <= '0';
-		
-		case ctrl.lines.mem_access is
-			when xmem_access =>
-				xmem_re <= ctrl.lines.mem_read;
-				xmem_we <= ctrl.lines.mem_write;
-			when xio_access =>
-				xio_sel <= '1';
-				xmem_re <= ctrl.lines.mem_read;
-				xmem_we <= ctrl.lines.mem_write;
-			when cmem_access =>
-				cmem_we <= ctrl.lines.mem_write;
-			when cio_access =>
-				cio_sel <= '1';
-				creg_we <= ctrl.lines.mem_write;
-			when others => null;
-		end case;
-	end process;
-
-iphase_counter:
-	process(rst, clk, ce)
-	variable pos : integer; 
-	begin
-		if rst = '1' then
-			iphase <= iphase_t'low;
-			cpu_active <= '0';
-		elsif rising_edge(clk) then
-			cpu_active <= '0';
-			if ce = '1' then
-				cpu_active <= '1';
-				if iphase = iphase_t'high then
-					iphase <= iphase_t'low;
-				else
-					iphase <= iphase + 1;
-				end if;
-			end if;	
-		end if;
-	end process;
-
-gen_instr_reg:
-if use_instr_register = true generate
-
-instr_reg:
-	process (rst, clk, ce)
-	begin
-		if rst = '1' then
-			ctrl_inst <= (others => '0');
-			ctrl_iphase <= 0;
-		elsif rising_edge(clk) and ce = '1' then
-			ctrl_inst <= instr_din;
-			ctrl_iphase <= iphase;
-		end if;
-	end process;
-
-end generate;
-	
-gen_instr_direct:
-if use_instr_register = false generate
-
-	ctrl_inst <= instr_din;
-	ctrl_iphase <= iphase;
-
-end generate;
-
-status_register:
-	process(clk, status_save)
-	begin
-		if rising_edge(clk) and status_save = '1' then
-			status_reg.alu <= alu_status;
-		end if;
-	end process;
-
-pc_pushpop:
-	process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc)
-	begin
-		pc_load <= ctrl.lines.pc_load or int_pc_load;
-		stk_push <= (ctrl.lines.stk_pushd or ctrl.lines.stk_push) or (int_stk_push and not was_pop2pc);
-		stk_pop <= ctrl.lines.stk_popd or int_stk_pop or (ctrl.lines.stk_pop and not int_pc_load);
-	end process;
-	
-lines_delay:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			was_pcld <= ctrl.lines.pc_load;
-			was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load;
-		end if;
-	end process;
-
-stk_mux:
-	process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out)
-	begin
-		if was_pcld = '1' and int_stk_push = '1' then 
-			stk_in <= idata;
-		elsif ctrl.lines.stk_pushd = '1' then
-			stk_in <= creg_ctrl_out.stk_high & reg_a_dout;
-		else	
-			stk_in <= pc_next;
-		end if;	
-		
-	end process;
-
-pc_mux:
-	process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out)
-	begin
-		
-		pc_in <= stk_out;
-		if int_pc_load = '1' then 
-			if int_stk_pop = '0' then
-				pc_in <= int_pc_addr;
-			end if;	
-		elsif ctrl.lines.pc_load = '1' then
-			if ctrl.lines.stk_pop = '0' then
-				pc_in <= idata;
-			end if;	
-		end if;	
-
-	end process;
-
-mem_data_mux:
-	process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out)
-	begin
-		case ctrl.lines.ddata_src_sel is
-		when reg_a => 
-			mem_data <= reg_a_dout;
-		when reg_b =>
-			mem_data <= reg_b_dout;
-		when const =>
-			mem_data <= const_data;
-		when others =>
-			mem_data <= const_data;
-		end case;
-
-	end process;
-
-mem_addr_mux:
-	process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.bank_sel)
-	begin
-		case ctrl.lines.daddr_src_sel is
-		when reg_a => 
-			mem_addr <= reg_a_dout;
-		when reg_b =>
-			mem_addr <= reg_b_dout;
-		when const =>
-			mem_addr <= const_data;
-		when others =>
-			mem_addr <= const_data;
-		end case;
-
-	end process;
-
-reg_in_mux:
-	process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout)
-	variable data : dmem_data_t;
-	begin
-		case ctrl.lines.reg_src_sel is
-		when xmem_src =>
-			data := xmem_din;
-		when cmem_src =>
-			if cio_sel = '0' then
-				data := cmem_dout(dmem_data_t'range);
-			else
-				data := creg_dout(dmem_data_t'range);
-			end if;
-		when stk_src =>
-			data := stk_out(dmem_data_t'range);
-		when others =>
-			data := alu_result;
-		end case;
-
-		reg_din <= data;
-
-	end process;
-
-alu_op1_mux:
-	process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data)
-	variable data : dmem_data_t;
-	begin
-		case ctrl.lines.alu_op1_src_sel is
-		when reg_a =>
-			data := reg_a_dout;
-		when reg_b =>
-			data := reg_b_dout;
-		when others =>
-			data := const_data;
-		end case;
-
-		alu_op1 <= data;
-
-	end process;
-
-alu_op2_mux:
-	process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data)
-	variable data : dmem_data_t;
-	begin
-		case ctrl.lines.alu_op2_src_sel is
-		when reg_a =>
-			data := reg_a_dout;
-		when reg_b =>
-			data := reg_b_dout;
-		when others =>
-			data := const_data;
-		end case;
-
-		alu_op2 <= data;
-
-	end process;
-
---------------------------------------------------------------------
-	inst_stack_ctrl: stack_ctrl
-	GENERIC MAP (
-		addr_width	=> STACK_SIZE_BITS
-	)
-	PORT MAP(
-		rst			=> rst,
-		clk			=> clk,
-		push		=> stk_push,
-		pop			=> stk_pop,
-		dout		=> stk_reg,
-		din			=> stk_in,
-		ptr_out		=> stk_ptr,
-		mem_we		=> stk_we
-	);
-
-	inst_pc: pc
-	PORT MAP(
-		rst			=> rst,
-		clk			=> clk,
-		inc			=> pc_inc,
-		load		=> pc_load,
-		pc_in		=> pc_in,
-		pc_out		=> pc_out,
-		pc_next		=> pc_next
-	);
-
-	inst_dpath_ctrl: dpath_ctrl
-	GENERIC MAP (
-		use_rom		=> use_ctrl_rom
-	)
-	PORT MAP(
-		inst_in		=> ctrl_inst,
-		iphase_in   => ctrl_iphase,
-		status_in	=> cpu_status,
-		ctrl_out	=> ctrl,
-		ddout		=> const_data,
-		idout		=> idata
-	);
-	
-	inst_int_ctrl: int_ctrl
-	PORT MAP(
-		rst				=> rst,
-		clk				=> clk,
-		ctrl_in			=> creg_ctrl_out.int_ctrl,
-		int_in			=> int_in,
-		int_ack_out		=> int_ack,
-		int_exit		=> ctrl.lines.int_exit,
-		iphase_in		=> ctrl_iphase,
-		stat_save_out	=> status_save,
-		stat_rest_out	=> status_restore,
-		pc_addr_out		=> int_pc_addr,
-		pc_load_out		=> int_pc_load,
-		stk_push_out	=> int_stk_push,
-		stk_pop_out		=> int_stk_pop
-		
-	);
-	
-	inst_reg_ab: reg_dual
-	GENERIC MAP (
-		addr_width	=> REG_SIZE_BITS,
-		data_width	=> DMEM_DATA_WIDTH
-	)
-	PORT MAP(
-		clk			=> clk,
-		we_a		=> ctrl.lines.reg_we,
-		ptr_a		=> ctrl.reg_a_ptr,
-		ptr_b		=> ctrl.reg_b_ptr,
-		din_a		=> reg_din,
-		dout_a		=> reg_a_dout,
-		dout_b		=> reg_b_dout
-	);
-
-	inst_chipram: chipram
-	GENERIC MAP (
-		addr_width	=> CHIPRAM_SIZE_BITS,
-		data_width	=> IMEM_ADDR_WIDTH
-	)
-	PORT MAP(
-		clka		=> clk,
-		clkb		=> clk,
-		en_a		=> cpu_active,
-		en_b		=> cpu_active,
-		we_a		=> stk_we,
-		we_b		=> cmem_we,
-		addr_a		=> stk_addr,
-		addr_b		=> cmem_addr,
-		din_a		=> stk_reg,
-		din_b		=> cmem_din,
-		dout_a		=> stk_out,
-		dout_b		=> cmem_dout
-	);
-
-	inst_chipreg: chipreg
-	PORT MAP(
-		rst			=> rst,
-		clk			=> clk,
-		we			=> creg_we,
-		addr		=> mem_addr,
-		din			=> mem_data,
-		dout		=> creg_dout,
-		ctrl_in		=> creg_ctrl_in,
-		ctrl_out	=> creg_ctrl_out
-	);
-
-	inst_alu: alu
-	GENERIC MAP (
-		data_width	=> DMEM_DATA_WIDTH
-	)
-	PORT MAP(
-		rst			=> rst,
-		clk			=> clk,
-		op_en		=> ctrl.lines.alu_load,
-		cy_in		=> ctrl.lines.alu_cy_in,
-		op1_in		=> alu_op1,
-		op2_in		=> alu_op2,
-		opsel		=> ctrl.lines.alu_opsel,
-		res_out		=> alu_result,
-		stat_load	=> status_restore,
-		stat_in		=> status_reg.alu,
-		stat_out	=> alu_status
-	);
-
-end rtl;

lib/CPUs/JCpu/src/core/cpu_pkg.vhd

@@ -1,856 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Types, constants and functions for JCPU
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-
-package cpu_pkg is
-
-	-- Revision of the CPU
-	constant REVISION : integer := 4;
-	
-	-- Chipram depth (valid values 9..floor(log2(BlockRamBytes)))
-	constant CHIPRAM_SIZE_BITS : integer := 10;
-	
-	-- Number of registers (16 registers fixed)
-	constant REG_SIZE_BITS : integer := 4;
-	
-	-- Instruction memory
-	constant IMEM_ADDR_WIDTH : integer := 12;
-	
-	-- Data memory
-	constant DMEM_DATA_WIDTH : integer := 8;
-	constant DMEM_ADDR_WIDTH : integer := 8;
-	
-	-- Instruction format
-	constant INST_OPCODE_WIDTH : integer := 6;
-	constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
-
-	-- Microcode ROM
-	constant MUCODE_ADDR_WIDTH : integer := 9;
-	
-	-- Stack depth (uses lower half of CHIPRAM)
-	constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
-
-	--Types
-	subtype iphase_t is integer range 0 to 1;
-	type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access);
-	type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src);
-	type alu_src_t is (reg_a, reg_b, const);
-	type ddata_src_t is (reg_a, reg_b, const);
-	type daddr_src_t is (reg_a, reg_b, const);
-	subtype instr_name_t is string(1 to 12);
-	type instr_name_array_t is array (0 to 63) of instr_name_t;
-	subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0);
-	subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-	subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-	subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0);
-	subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
-	subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
-	subtype reg_ptr_t is unsigned (3 downto 0);
-	type dmem_array_t is array (natural range <>) of dmem_data_t;
-	type instr_addr_array is array (integer range <>) of inst_addr_t;
-	subtype bank_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
-	
-	type alu_op_t is
-	(
-		pass_op2,
-		op1_add_op2,
-		op1_sub_op2,
-		op1_addc_op2,
-		op1_subc_op2,
-		op1_and_op2,
-		op1_or_op2,
-		op1_xor_op2,
-		swap_op,
-		shl_op,
-		shr_op,
-		rol_op,
-		ror_op,
-		rolc_op,
-		rorc_op
-	);
-	
-	type alu_status_t is record
-		zero		: STD_LOGIC;
-		carry		: STD_LOGIC;
-	end record;
-
-	type cpu_status_t is record
-		alu			: alu_status_t;
-	end record;
-
-	type ctrl_lines_t is record
-		reg_we			: STD_LOGIC;
-		reg_src_sel		: reg_src_t;
-		alu_op1_src_sel	: alu_src_t;
-		alu_op2_src_sel	: alu_src_t;
-		alu_opsel		: alu_op_t;
-		alu_load		: STD_LOGIC;
-		alu_cy_in		: STD_LOGIC;
-		ddata_src_sel	: ddata_src_t;
-		daddr_src_sel	: daddr_src_t; 
-		pc_load			: STD_LOGIC;
-		pc_inc			: STD_LOGIC;
-		stk_push		: STD_LOGIC; 
-		stk_pop			: STD_LOGIC;
-		stk_pushd		: STD_LOGIC; 
-		stk_popd		: STD_LOGIC;
-		mem_access		: mem_access_t;
-		mem_read		: STD_LOGIC;
-		mem_write		: STD_LOGIC;
-		int_exit		: STD_LOGIC;
-	end record;
-
-	type dpath_ctrl_out_t is record
-		lines			: ctrl_lines_t;
-		reg_a_ptr		: reg_ptr_t;
-		reg_b_ptr		: reg_ptr_t;
-	end record;
-	
-	type int_ctrl_in_t is record
-		enable			: std_logic;
-	end record;
-	
-	type creg_ctrl_out_t is record
-		bank_sel		: bank_sel_t;
-		int_ctrl		: int_ctrl_in_t;
-		stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-		cmem_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-	end record;
-	
-	type creg_ctrl_in_t is record
-		alu				: alu_status_t;
-	end record;
-
-	
-	type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t;
-
-	constant instr_name_array : instr_name_array_t := 
-	(
-		"NOP         ", -- 00
-		"HALT        ", -- 01
-		"MOV|R|R     ", -- 02
-		"MOV|R|K     ", -- 03
-		"MOVX|R|Ri   ", -- 04
-		"MOVX|R|Ki   ", -- 05
-		"MOVX|Ri|R   ", -- 06
-		"MOVX|Ri|K   ", -- 07
-		"MOVX|Ki|R   ", -- 08
-		"MOVC|R|Ri   ", -- 09
-		"MOVC|R|Ki   ", -- 0A
-		"MOVC|Ri|R   ", -- 0B
-		"MOVC|Ri|K   ", -- 0C
-		"MOVC|Ki|R   ", -- 0D
-		"CMP|R|R     ", -- 0E
-		"CMP|R|K     ", -- 0F
-		"ADD|R|R     ", -- 10
-		"ADD|R|K     ", -- 11
-		"ADDC|R|R    ", -- 12
-		"ADDC|R|K    ", -- 13
-		"SUB|R|R     ", -- 14
-		"SUB|R|K     ", -- 15
-		"SUBC|R|R    ", -- 16
-		"SUBC|R|K    ", -- 17
-		"AND|R|R     ", -- 18
-		"AND|R|K     ", -- 19
-		"OR|R|R      ", -- 1A
-		"OR|R|K      ", -- 1B
-		"XOR|R|R     ", -- 1C
-		"XOR|R|K     ", -- 1D
-		"SHL|R       ", -- 1E
-		"SHR|R       ", -- 1F
-		"ROL|R       ", -- 20
-		"ROR|R       ", -- 21
-		"ROLC|R      ", -- 22
-		"RORC|R      ", -- 23
-		"XOUT|Ki|R   ", -- 24
-		"XOUT|Ri|K   ", -- 25
-		"COUT|Ki|R   ", -- 26
-		"COUT|Ri|K   ", -- 27
-		"XIN|R|Ki    ", -- 28
-		"CIN|R|Ki    ", -- 29
-		"SWAP|R      ", -- 2A
-		"SETC        ", -- 2B
-		"UNDEF       ", -- 2C
-		"UNDEF       ", -- 2D
-		"SUB|K|R     ", -- 2E
-		"SUBC|K|R    ", -- 2F
-		"JMP|K       ", -- 30
-		"JZ|K        ", -- 31
-		"JNZ|K       ", -- 32
-		"JC|K        ", -- 33
-		"JNC|K       ", -- 34
-		"JLT|K       ", -- 35
-		"JGT|K       ", -- 36
-		"JLE|K       ", -- 37
-		"JGE|K       ", -- 38
-		"JEQ|K       ", -- 39
-		"JNE|K       ", -- 3A
-		"CALL|K      ", -- 3B
-		"PUSH|R      ", -- 3C
-		"POP|R       ", -- 3D
-		"RET         ", -- 3E
-		"RETI        "  -- 3F
-	);
-	-- Functions
-	function Instr(opcode : opcode_t) return inst_t;
-	function Instr(opcode : opcode_t; data : inst_data_t) return inst_t;
-	function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t;
-	function Instr(opcode : opcode_t; reg_a : integer) return inst_t;
-	function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t;
-	function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t;
-	function ctrl_lines_default return ctrl_lines_t;
-	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
-	function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
-	function gen_murom return murom_t;
-	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned;
-	function MIN (X, Y: INTEGER) return INTEGER;
-	function MAX (X, Y: INTEGER) return INTEGER;
-
-end cpu_pkg;
-
-package body cpu_pkg is
-
-	function Instr(opcode : opcode_t) return inst_t is
-	variable inst : inst_t := (others => '0'); 
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is
-	variable inst : inst_t := (others => '0'); 
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data;
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is
-	variable inst : inst_t := (others => '0');
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data;
-		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length));
-
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; reg_a : integer) return inst_t is
-	variable inst : inst_t := (others => '0');
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
-
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is
-	variable inst : inst_t := (others => '0');
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
-		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
-
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is
-	variable inst : inst_t := (others => '0');
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length));
-		inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
-		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
-
-		return inst;
-
-	end Instr;
-
-	function ctrl_lines_default return ctrl_lines_t is
-	variable result : ctrl_lines_t;
-	begin
-		result.pc_load := '0';
-		result.pc_inc := '0';
-		result.stk_push := '0';
-		result.stk_pop := '0';
-		result.stk_pushd := '0';
-		result.stk_popd := '0';
-		result.reg_we := '0';
-		result.reg_src_sel := alu_src;
-		result.ddata_src_sel := reg_a;
-		result.daddr_src_sel := reg_b;
-		result.alu_opsel := pass_op2;
-		result.alu_op1_src_sel := reg_a;
-		result.alu_op2_src_sel := reg_b;
-		result.alu_load := '0';
-		result.alu_cy_in := '0';
-		result.mem_access := cmem_access;
-		result.mem_read := '0';
-		result.mem_write := '0';
-		result.int_exit := '0';
-		return result;
-	
-	end ctrl_lines_default;
-
-	function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
-	variable instr_name : instr_name_t;
-	begin
-		instr_name := instr_name_array(to_integer(opcode));
-		return idecoder(instr_name, iphase, status);
-	end idecoder;
-
-	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
-	variable result : ctrl_lines_t;
-	variable ze, cy : STD_LOGIC;
-	
-	begin
-		ze			:= status.alu.zero;
-		cy			:= status.alu.carry;
-		
-		result := ctrl_lines_default;
-		if iphase = 0 then
-			result.pc_inc := '1';
-		end if;
-
-		case instr_name is
-
-		when "HALT        " =>
-			result.pc_inc := '0';
-		when "SETC        " => -- carry <= 1
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := pass_op2;
-			result.alu_op2_src_sel := reg_b;
-			result.alu_load := '1';
-			result.alu_cy_in := '1';
-		when "MOV|R|R     " => -- R(a) <= R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := pass_op2;
-			result.alu_op2_src_sel := reg_b;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "MOV|R|K     " => -- R(a) <= #kk
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := pass_op2;
-			result.alu_op2_src_sel := const;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "MOVC|Ri|R   " => -- [R(b)] <= R(a)
-			result.mem_access := cmem_access;
-			result.daddr_src_sel := reg_b;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVC|Ri|K   " => -- [R(a)] <= kk
-			result.mem_access := cmem_access;
-			result.daddr_src_sel := reg_a;
-			result.ddata_src_sel := const;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "COUT|Ri|K   " => -- [R(a)] <= kk
-			result.mem_access := cio_access;
-			result.daddr_src_sel := reg_a;
-			result.ddata_src_sel := const;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVC|R|Ri   " => -- R(a) <= [R(b)]
-			result.mem_access := cmem_access;
-			result.reg_src_sel := cmem_src;
-			result.daddr_src_sel := reg_b;
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "MOVC|R|Ki   " => -- R(a) <= [#addr]
-			result.mem_access := cmem_access;
-			result.reg_src_sel := cmem_src;
-			result.daddr_src_sel := const;
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "CIN|R|Ki    " => -- R(a) <= [#addr]
-			result.mem_access := cio_access;
-			result.reg_src_sel := cmem_src;
-			result.daddr_src_sel := const;
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "MOVC|Ki|R   " => -- [#addr] <= R(a)
-			result.mem_access := cmem_access;
-			result.daddr_src_sel := const;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "COUT|Ki|R   " => -- [#addr] <= R(a)
-			result.mem_access := cio_access;
-			result.daddr_src_sel := const;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVX|Ri|R   " => -- [R(b)] <= R(a)
-			result.mem_access := xmem_access;
-			result.daddr_src_sel := reg_b;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVX|Ri|K   " => -- [R(a)] <= kk
-			result.mem_access := xmem_access;
-			result.daddr_src_sel := reg_a;
-			result.ddata_src_sel := const;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "XOUT|Ri|K   " => -- [R(a)] <= kk
-			result.mem_access := xio_access;
-			result.daddr_src_sel := reg_a;
-			result.ddata_src_sel := const;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVX|R|Ri   " => -- R(a) <= [R(b)]
-			result.mem_access := xmem_access;
-			result.reg_src_sel := xmem_src;
-			result.daddr_src_sel := reg_b;
-			if iphase = 0 then
-				result.mem_read := '1';
-			elsif iphase = 1 then
-					result.reg_we := '1';
-				end if;
-		when "MOVX|R|Ki   " => -- R(a) <= [#addr]
-			result.mem_access := xmem_access;
-			result.reg_src_sel := xmem_src;
-			result.daddr_src_sel := const;
-			if iphase = 0 then
-				result.mem_read := '1';
-			elsif iphase = 1 then
-					result.reg_we := '1';
-				end if;
-		when "XIN|R|Ki    " => -- R(a) <= [#addr]
-			result.mem_access := xio_access;
-			result.reg_src_sel := xmem_src;
-			result.daddr_src_sel := const;
-			if iphase = 0 then
-				result.mem_read := '1';
-			elsif iphase = 1 then
-					result.reg_we := '1';
-				end if;
-		when "MOVX|Ki|R   " => -- [#addr] <= R(a)
-			result.mem_access := xmem_access;
-			result.daddr_src_sel := const;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "XOUT|Ki|R   " => -- [#addr] <= R(a)
-			result.mem_access := xio_access;
-			result.daddr_src_sel := const;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "ADD|R|R     " => -- R(a) <= R(a) + R(b)
-			result.alu_opsel := op1_add_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ADD|R|K     " => -- R(a) <= R(a) + k
-			result.alu_opsel := op1_add_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ADDC|R|R    " => -- R(a) <= R(a) + R(b)
-			result.alu_opsel := op1_addc_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ADDC|R|K    " => -- R(a) <= R(a) + k
-			result.alu_opsel := op1_addc_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUB|R|R     " => -- R(a) <= R(a) + R(b)
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUB|R|K     " => -- R(a) <= R(a) + k
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUB|K|R     " => -- R(a) <= k - R(a)
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := const;
-			result.alu_op2_src_sel := reg_a;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUBC|R|R    " => -- R(a) <= R(a) + R(b)
-			result.alu_opsel := op1_subc_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUBC|R|K    " => -- R(a) <= R(a) + k
-			result.alu_opsel := op1_subc_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUBC|K|R    " => -- R(a) <= K - R(a)
-			result.alu_opsel := op1_subc_op2;
-			result.alu_op1_src_sel := const;
-			result.alu_op2_src_sel := reg_a;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "AND|R|R     " => -- R(a) <= R(a) and R(b)
-			result.alu_opsel := op1_and_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "AND|R|K     " => -- R(a) <= R(a) and k
-			result.alu_opsel := op1_and_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "OR|R|R      " => -- R(a) <= R(a) or R(b)
-			result.alu_opsel := op1_or_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "OR|R|K      " => -- R(a) <= R(a) or R(b)
-			result.alu_opsel := op1_or_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "XOR|R|R     " => -- R(a) <= R(a) xor R(b)
-			result.alu_opsel := op1_xor_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "XOR|R|K     " => -- R(a) <= R(a) xor R(b)
-			result.alu_opsel := op1_xor_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SWAP|R      " => -- R(a) <= R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := swap_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SHL|R       " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := shl_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SHR|R       " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := shr_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ROL|R       " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := rol_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ROR|R       " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := ror_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ROLC|R      " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := rolc_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "RORC|R      " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := rorc_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "CMP|R|R     " => -- 
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.alu_load := '1';
-		when "CMP|R|K     " => -- 
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.alu_load := '1';
-		when "JMP|K       " => -- PC <= #addr
-			if iphase = 0 then
-				result.pc_load := '1';
-			end if;
-		when "JZ|K        " => -- PC <= #addr, zero
-			if iphase = 0 then
-				if ze = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JNZ|K       " => -- PC <= #addr, !zero
-			if iphase = 0 then
-				if ze = '0' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JC|K        " => -- PC <= #addr, carry
-			if iphase = 0 then
-				if cy = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JNC|K       " => -- PC <= #addr, !carry
-			if iphase = 0 then
-				if cy = '0' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JLT|K       " => -- PC <= #addr, !carry
-			if iphase = 0 then
-				if cy = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JGT|K       " => -- 
-			if iphase = 0 then
-				if (cy or ze) = '0' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JLE|K       " => -- 
-			if iphase = 0 then
-				if (cy xor ze) = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JGE|K       " => -- 
-			if iphase = 0 then
-				if (not cy or ze) = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JEQ|K       " => -- 
-			if iphase = 0 then
-				if ze = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JNE|K       " => -- 
-			if iphase = 0 then
-				if ze = '0' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "PUSH|R      " => -- push
-			if iphase = 0 then
-				result.stk_pushd := '1';
-			end if;
-		when "POP|R       " => -- pop
-			result.reg_src_sel := stk_src;
-			if iphase = 0 then
-				result.stk_popd := '1';
-			elsif iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "CALL|K      " => -- call
-			if iphase = 0 then
-				result.pc_load := '1';
-				result.stk_push := '1';
-			end if;
-		when "RET         " => -- return
-			if iphase = 0 then
-				result.pc_load := '1';
-				result.stk_pop := '1';
-			end if;
-		when "RETI        " => -- return
-			result.pc_inc := '0';
-			result.int_exit := '1';
-			
-		when others => null; -- nop
-		end case;
-
-		return result;
-
-	end idecoder;
-
-	function gen_murom return murom_t is
-	variable result : murom_t; 
-	variable opcode : opcode_t;
-	variable iphase : iphase_t;
-	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
-	variable status : cpu_status_t;
-	variable pos : integer := 0;
-	
-	begin
-		for i in 0 to 2**addr'length-1 loop
-			addr := to_unsigned(i, addr'length);
-			opcode := addr(opcode'length-1 downto 0);
-			pos := opcode'length;
-			iphase := 0;
-			if addr(pos) = '1' then
-				iphase := 1;
-			end if;
-			pos := pos + 1;
-			status.alu.zero := addr(pos);
-			pos := pos + 1;
-			status.alu.carry := addr(pos);
-			
-			result(i) := idecoder(opcode, iphase, status);
-		end loop;
-
-		return result;
-	end gen_murom;
-
-	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
-	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
-	begin
-		addr := status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
-		return addr;
-		
-	end get_muromaddr;
-
-	-------------------------------------------------------------
-	function MIN (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y < X then
-		res := Y;
-	end if;
-
-	return res;
-
-	end MIN;
-
-	-------------------------------------------------------------
-	function MAX (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y > X then
-		res := Y;
-	end if;
-
-	return res;
-	
-	end MAX;
-
-
-end cpu_pkg;
-

lib/CPUs/JCpu/src/core/dpath_ctrl.vhd

@@ -1,87 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The datapath controller
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity dpath_ctrl is
-	Generic (
-		use_rom		: boolean := true
-	);
-	Port (
-		inst_in		: in  inst_t;
-		iphase_in	: in  iphase_t;
-		status_in	: in  cpu_status_t;
-		ctrl_out	: out dpath_ctrl_out_t;
-		idout		: out inst_addr_t;
-		ddout		: out dmem_data_t
-	);
-end dpath_ctrl;
-
-architecture Behavioral of dpath_ctrl is
-
-	signal opcode : opcode_t;
-	signal ctrl_lines : ctrl_lines_t;
-	signal dbg_iname : instr_name_t;
-	
-begin
-
-	idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0);
-	ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS);
-	opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH);
-
-	ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0);
-	ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length);
-	ctrl_out.lines <= ctrl_lines;
-
-	-- pragma translate_off
-	dbg_iname <= instr_name_array(to_integer(opcode));
-	-- pragma translate_on
-
-gen_ctrl_rom:
-if use_rom = true generate
-
-	i_dec:
-		process(opcode, iphase_in, status_in)
-		constant rom_data : murom_t := gen_murom;
-		variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
-		begin
-			addr := get_muromaddr(opcode, iphase_in, status_in);
-			ctrl_lines <= rom_data(to_integer(addr));
-		end process;
-end generate;
-
-gen_ctrl:
-if use_rom = false generate
-	i_dec:
-		process (opcode, iphase_in, status_in)
-		begin
-			ctrl_lines <= idecoder(opcode, iphase_in, status_in);
-		end process;
-end generate;
-
-end Behavioral;
-

lib/CPUs/JCpu/src/core/int_ctrl.vhd

@@ -1,138 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Interrupt controller 
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity int_ctrl is
-	Port (
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		ctrl_in			: in  int_ctrl_in_t;
-		int_in			: in  STD_LOGIC;
-		int_exit		: in  STD_LOGIC;
-		iphase_in		: in  iphase_t;
-		pc_addr_out		: out inst_addr_t;
-		int_ack_out		: out STD_LOGIC;
-		stat_save_out	: out STD_LOGIC; 
-		stat_rest_out	: out STD_LOGIC; 
-		pc_load_out		: out STD_LOGIC;
-		stk_push_out	: out STD_LOGIC;
-		stk_pop_out		: out STD_LOGIC
-	);
-end int_ctrl;
-
-architecture Behavioral of int_ctrl is
-
-	type int_state_t is (int_idle, int_inject, int_active, int_release);
-	
-	signal int_state, int_state_next : int_state_t;
-	signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC;
-	signal int_request : std_logic;
-	
-	
-begin
-
-	int_ack_out		<= int_ack;
-	pc_load_out		<= pc_load;
-	stk_push_out	<= stk_push;
-	stk_pop_out		<= stk_pop;
-	
------------------------------------------------------------------------
-irg_ctrl_fsm:
-	process (int_state, iphase_in, int_request, int_exit)
-	begin
-
-		pc_addr_out <= to_unsigned(1, inst_addr_t'length);
-		int_state_next <= int_state;
-		int_ack <= '0';
-		pc_load <= '0';
-		stk_push <= '0';
-		stk_pop <= '0';
-		case int_state is
-		
-		when int_idle =>
-			if int_request = '1' and iphase_in = 1 then
-				int_state_next <= int_inject;
-			end if;
-		when int_inject =>
-			if iphase_in = 0 then
-				int_ack <= '1';
-				pc_load <= '1';
-			elsif iphase_in = 1 then
-				stk_push <= '1';
-				int_state_next <= int_active;
-			end if;
-		when int_active =>
-			if int_exit = '1' and iphase_in = 1 then
-				int_state_next <= int_release;
-			end if;
-		when int_release =>
-			if iphase_in = 0 then
-				stk_pop <= '1';
-				pc_load <= '1';
-			elsif iphase_in = 1 then
-				int_state_next <= int_idle;
-			end if;	
-		when others => 	
-			int_state_next <= int_idle;
-		end case;	
-			
-	end process;
-	
-irq_ctrl_states:
-	process (rst, clk, int_state_next)
-	begin
-		if rst = '1' then
-			int_state <= int_idle;
-		elsif rising_edge(clk) then
-			int_state <= int_state_next;
-		end if;
-	end process;
-
------------------------------------------------------------------------
-pin_sample:
-	process (clk)
-	begin
-		if rising_edge(clk) then
-			int_request <= '0';
-			if ctrl_in.enable = '1' then
-				int_request <= int_in;
-			end if;	
-		end if;
-	end process;
-
------------------------------------------------------------------------
-stat_save_restore:
-	process (clk, stk_push, stk_pop)
-	begin
-		if rising_edge(clk) then
-			stat_save_out <= stk_push;
-			stat_rest_out <= stk_pop;
-		end if;
-	end process;
-
-end Behavioral;

lib/CPUs/JCpu/src/core/pc.vhd

@@ -1,70 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Programm counter
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity pc is
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		inc			: in  STD_LOGIC;
-		load		: in  STD_LOGIC;
-		pc_in		: in  inst_addr_t;
-		pc_out		: out inst_addr_t;
-		pc_next		: out inst_addr_t
-	);
-end pc;
-
-architecture Behavioral of pc is
-
-begin
-
-proc_pc:
-	process(rst, clk, inc, load, pc_in)
-	variable vpc, vpc_reg: inst_addr_t;
-	begin
-		if rst = '1' then
-			vpc_reg := (others => '0');
-		elsif rising_edge(clk) then
-			if inc = '1' or load = '1' then
-				vpc_reg := vpc;
-			elsif inc = '0'	then
-				pc_next <= vpc;		
-			end if;
-		end if;
-		
-		if load = '1' then
-			vpc := pc_in;	
-		else
-			vpc := vpc_reg + 1;
-		end if;	
-		pc_out <= vpc_reg;
-		
-	end process;
-
-end Behavioral;
-

lib/CPUs/JCpu/src/core/reg_dual.vhd

@@ -1,81 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: On-Chip work registers
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity reg_dual is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clk			: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		ptr_a		: in  reg_ptr_t;
-		ptr_b		: in  reg_ptr_t;
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end reg_dual;
-
-architecture Behavioral of reg_dual is
-
-	constant depth : integer := 2**addr_width;
-	type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0');
-
-	signal mem : mem_t;
-begin
-
-	addr_a <= TO_01(ptr_a(addr_width-1 downto 0));
-	addr_b <= TO_01(ptr_b(addr_width-1 downto 0));
-
-reg_in_ab:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if we_a = '1' then
-				mem(to_integer(addr_a)) <= din_a;
-			end if;
-		end if;	
-	end process;
-
-reg_out_a:
-	process(mem, addr_a)
-	begin
-		dout_a <= TO_01(mem(to_integer(addr_a)));
-	end process;
-
-reg_out_b:
-	process(mem, addr_b)
-	begin
-		dout_b <= TO_01(mem(to_integer(addr_b)));
-	end process;
-
-end Behavioral;
-

lib/CPUs/JCpu/src/core/stack_ctrl.vhd

@@ -1,73 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The call/return/data stack
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity stack_ctrl is
-Generic (
-	addr_width : integer := 3
-);
-Port (
-	rst			: in  STD_LOGIC;
-	clk			: in  STD_LOGIC;
-	push		: in  STD_LOGIC;
-	pop			: in  STD_LOGIC;
-	ptr_out		: out unsigned (addr_width-1 downto 0);
-	din			: in  inst_addr_t;
-	dout		: out inst_addr_t;
-	mem_we		: out STD_LOGIC
-	);
-end stack_ctrl;
-
-architecture Behavioral of stack_ctrl is
-
-	signal ptr : unsigned (addr_width-1 downto 0);
-
-begin
-
-	ptr_out <= ptr;
-
-stk_ptr:
-	process(rst, clk, ptr, push, pop)
-	begin
-		if rst = '1' then
-			ptr <= (others => '0');
-			dout <= (others => '0');
-			mem_we <= '0';
-		elsif rising_edge(clk) then
-			mem_we <= push;
-			if push = '1' then
-				ptr <= ptr + 1;
-				dout <= din;
-			elsif pop = '1' then
-				ptr <= ptr - 1;
-			end if;
-		end if;
-	end process;
-
-end Behavioral;
-

lib/CPUs/JCpu/src/cpu_embedded.vhd

@@ -1,106 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity cpu_embedded is
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out STD_LOGIC;
-		xmem_we		: out STD_LOGIC;
-		xmem_re		: out STD_LOGIC;
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
-		io_sel		: out STD_LOGIC
-	);
-end cpu_embedded;
-
-architecture rtl of cpu_embedded is
-
-	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0);
-	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-
-	COMPONENT cpu
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out STD_LOGIC;
-		xmem_we		: out STD_LOGIC;
-		xmem_re		: out STD_LOGIC;
-		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
-		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		io_sel		: out STD_LOGIC
-	);
-	END COMPONENT;
-
-
-	COMPONENT irom
-		Port (
-			clk			: in  STD_LOGIC;
-			ce			: in  STD_LOGIC;
-			addr		: in  inst_addr_t;
-			dout		: out inst_t
-		);
-	END COMPONENT;
-
-begin
-
-inst_cpu: cpu
-	PORT MAP(
-		rst => rst,
-		clk => clk,
-		ce => ce,
-		int_in => int_in,
-		int_ack => int_ack,
-		xmem_we => xmem_we,
-		xmem_re => xmem_re,
-		instr_din => irom_data,
-		instr_addr => irom_addr,
-		xmem_din => xmem_din,
-		xmem_dout => xmem_dout,
-		xmem_addr => xmem_addr,
-		io_sel => io_sel
-	);
-
-inst_irom: irom
-	PORT MAP(
-		clk			=> clk,
-		ce			=> ce,
-		addr		=> irom_addr,
-		dout 		=> irom_data
-	);
-
-end rtl;

lib/CPUs/JCpu/src/dctest_irom.vhdl

@@ -1,79 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY irom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  inst_addr_t;
-	dout		: out inst_t
-	);
-END irom;
-
-ARCHITECTURE dctest OF irom IS 
-
-	type imem_rom_t is array (0 to 17) of inst_t;
-
-	-- Assembled from dctest.jsm
-	constant imem_rom : imem_rom_t :=
-	(
-		"110000" & X"010", -- 0x000: JMP 0x010
-		"110000" & X"011", -- 0x001: JMP 0x011
-		"000000" & X"000", -- 0x002:
-		"000000" & X"000", -- 0x003:
-		"000000" & X"000", -- 0x004:
-		"000000" & X"000", -- 0x005:
-		"000000" & X"000", -- 0x006:
-		"000000" & X"000", -- 0x007:
-		"000000" & X"000", -- 0x008:
-		"000000" & X"000", -- 0x009:
-		"000000" & X"000", -- 0x00A:
-		"000000" & X"000", -- 0x00B:
-		"000000" & X"000", -- 0x00C:
-		"000000" & X"000", -- 0x00D:
-		"000000" & X"000", -- 0x00E:
-		"000000" & X"000", -- 0x00F:
-		"110000" & X"010", -- 0x010: JMP 0x010
-		"111111" & X"000"  -- 0x011: RETI
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end dctest;
-

lib/CPUs/JCpu/src/dctest_xrom.vhdl

@@ -1,317 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY xrom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  dmem_addr_t;
-	dout		: out dmem_data_t
-	);
-END xrom;
-
-ARCHITECTURE dctest OF xrom IS 
-
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-
-	-- Assembled from dctest.jsm
-	constant xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"01", -- 0x04
-		X"12", -- 0x05
-		X"41", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"48", -- 0x17
-		X"61", -- 0x18
-		X"6C", -- 0x19
-		X"6C", -- 0x1A
-		X"6F", -- 0x1B
-		X"0D", -- 0x1C
-		X"0A", -- 0x1D
-		X"00", -- 0x1E
-		X"4A", -- 0x1F
-		X"65", -- 0x20
-		X"6E", -- 0x21
-		X"73", -- 0x22
-		X"00", -- 0x23
-		X"57", -- 0x24
-		X"65", -- 0x25
-		X"6C", -- 0x26
-		X"63", -- 0x27
-		X"6F", -- 0x28
-		X"6D", -- 0x29
-		X"65", -- 0x2A
-		X"20", -- 0x2B
-		X"74", -- 0x2C
-		X"6F", -- 0x2D
-		X"20", -- 0x2E
-		X"4A", -- 0x2F
-		X"41", -- 0x30
-		X"53", -- 0x31
-		X"4D", -- 0x32
-		X"20", -- 0x33
-		X"43", -- 0x34
-		X"50", -- 0x35
-		X"55", -- 0x36
-		X"00", -- 0x37
-		X"52", -- 0x38
-		X"65", -- 0x39
-		X"61", -- 0x3A
-		X"64", -- 0x3B
-		X"79", -- 0x3C
-		X"00", -- 0x3D
-		X"54", -- 0x3E
-		X"65", -- 0x3F
-		X"73", -- 0x40
-		X"74", -- 0x41
-		X"69", -- 0x42
-		X"6E", -- 0x43
-		X"67", -- 0x44
-		X"00", -- 0x45
-		X"50", -- 0x46
-		X"61", -- 0x47
-		X"73", -- 0x48
-		X"73", -- 0x49
-		X"65", -- 0x4A
-		X"64", -- 0x4B
-		X"00", -- 0x4C
-		X"45", -- 0x4D
-		X"72", -- 0x4E
-		X"72", -- 0x4F
-		X"6F", -- 0x50
-		X"72", -- 0x51
-		X"00", -- 0x52
-		X"0D", -- 0x53
-		X"0A", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end dctest;
-

lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl

@@ -1,413 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from dctest.jsm
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-	signal xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"01", -- 0x04
-		X"12", -- 0x05
-		X"41", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"48", -- 0x17
-		X"61", -- 0x18
-		X"6C", -- 0x19
-		X"6C", -- 0x1A
-		X"6F", -- 0x1B
-		X"0D", -- 0x1C
-		X"0A", -- 0x1D
-		X"00", -- 0x1E
-		X"4A", -- 0x1F
-		X"65", -- 0x20
-		X"6E", -- 0x21
-		X"73", -- 0x22
-		X"00", -- 0x23
-		X"57", -- 0x24
-		X"65", -- 0x25
-		X"6C", -- 0x26
-		X"63", -- 0x27
-		X"6F", -- 0x28
-		X"6D", -- 0x29
-		X"65", -- 0x2A
-		X"20", -- 0x2B
-		X"74", -- 0x2C
-		X"6F", -- 0x2D
-		X"20", -- 0x2E
-		X"4A", -- 0x2F
-		X"41", -- 0x30
-		X"53", -- 0x31
-		X"4D", -- 0x32
-		X"20", -- 0x33
-		X"43", -- 0x34
-		X"50", -- 0x35
-		X"55", -- 0x36
-		X"00", -- 0x37
-		X"52", -- 0x38
-		X"65", -- 0x39
-		X"61", -- 0x3A
-		X"64", -- 0x3B
-		X"79", -- 0x3C
-		X"00", -- 0x3D
-		X"54", -- 0x3E
-		X"65", -- 0x3F
-		X"73", -- 0x40
-		X"74", -- 0x41
-		X"69", -- 0x42
-		X"6E", -- 0x43
-		X"67", -- 0x44
-		X"00", -- 0x45
-		X"50", -- 0x46
-		X"61", -- 0x47
-		X"73", -- 0x48
-		X"73", -- 0x49
-		X"65", -- 0x4A
-		X"64", -- 0x4B
-		X"00", -- 0x4C
-		X"45", -- 0x4D
-		X"72", -- 0x4E
-		X"72", -- 0x4F
-		X"6F", -- 0x50
-		X"72", -- 0x51
-		X"00", -- 0x52
-		X"0D", -- 0x53
-		X"0A", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;

lib/CPUs/JCpu/src/itest_xrom.vhdl

@@ -1,317 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY xrom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  dmem_addr_t;
-	dout		: out dmem_data_t
-	);
-END xrom;
-
-ARCHITECTURE itest OF xrom IS 
-
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-
-	-- Assembled from itest.jsm
-	constant xmem_rom : xmem_rom_t :=
-	(
-		X"48", -- 0x00
-		X"61", -- 0x01
-		X"6C", -- 0x02
-		X"6C", -- 0x03
-		X"6F", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end itest;
-

lib/CPUs/JCpu/src/itest_xrom_ld.vhdl

@@ -1,413 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from itest.jsm
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-	signal xmem_rom : xmem_rom_t :=
-	(
-		X"48", -- 0x00
-		X"61", -- 0x01
-		X"6C", -- 0x02
-		X"6C", -- 0x03
-		X"6F", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;

lib/CPUs/JCpu/src/mul8x8_irom.vhdl

@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY irom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  inst_addr_t;
-	dout		: out inst_t
-	);
-END irom;
-
-ARCHITECTURE mul8x8 OF irom IS 
-
-	type imem_rom_t is array (0 to 26) of inst_t;
-
-	-- Assembled from mul8x8.jsm
-	constant imem_rom : imem_rom_t :=
-	(
-		"110000" & X"001", -- 0x000: JMP 0x001
-		"000011" & X"450", -- 0x001: MOV R00, 0x45
-		"000011" & X"F51", -- 0x002: MOV R01, 0xF5
-		"111011" & X"005", -- 0x003: CALL 0x005
-		"110000" & X"004", -- 0x004: JMP 0x004
-		"111100" & X"002", -- 0x005: PUSH R02
-		"111100" & X"003", -- 0x006: PUSH R03
-		"111100" & X"004", -- 0x007: PUSH R04
-		"000010" & X"014", -- 0x008: MOV R04, R01
-		"000011" & X"001", -- 0x009: MOV R01, 0x00
-		"000011" & X"002", -- 0x00A: MOV R02, 0x00
-		"000011" & X"003", -- 0x00B: MOV R03, 0x00
-		"001111" & X"014", -- 0x00C: CMP R04, 0x01
-		"111001" & X"015", -- 0x00D: JEQ 0x015
-		"011111" & X"004", -- 0x00E: SHR R04
-		"110100" & X"012", -- 0x00F: JNC 0x012
-		"010000" & X"002", -- 0x010: ADD R02, R00
-		"010010" & X"013", -- 0x011: ADDC R03, R01
-		"011110" & X"000", -- 0x012: SHL R00
-		"100010" & X"001", -- 0x013: ROLC R01
-		"110000" & X"00C", -- 0x014: JMP 0x00C
-		"010000" & X"020", -- 0x015: ADD R00, R02
-		"010010" & X"031", -- 0x016: ADDC R01, R03
-		"111101" & X"004", -- 0x017: POP R04
-		"111101" & X"003", -- 0x018: POP R03
-		"111101" & X"002", -- 0x019: POP R02
-		"111110" & X"000"  -- 0x01A: RET
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end mul8x8;
-

lib/CPUs/JCpu/src/mul8x8_xrom.vhdl

@@ -1,317 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY xrom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  dmem_addr_t;
-	dout		: out dmem_data_t
-	);
-END xrom;
-
-ARCHITECTURE mul8x8 OF xrom IS 
-
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-
-	-- Assembled from mul8x8.jsm
-	constant xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"00", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end mul8x8;
-

lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl

@@ -1,413 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from mul8x8.jsm
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-	signal xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"00", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;

lib/CPUs/JCpu/src/reti_issue_irom.vhdl

@@ -1,89 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY irom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  inst_addr_t;
-	dout		: out inst_t
-	);
-END irom;
-
-ARCHITECTURE reti_issue OF irom IS 
-
-	type imem_rom_t is array (0 to 27) of inst_t;
-
-	-- Assembled from reti_issue.jsm
-	constant imem_rom : imem_rom_t :=
-	(
-		"110000" & X"002", -- 0x000: JMP 0x002
-		"111111" & X"000", -- 0x001: RETI
-		"000011" & X"050", -- 0x002: MOV R00, 0x05
-		"100110" & X"030", -- 0x003: COUT (0x03), R00
-		"000011" & X"000", -- 0x004: MOV R00, 0x00
-		"000000" & X"000", -- 0x005: NOP
-		"010001" & X"010", -- 0x006: INC R00
-		"000000" & X"000", -- 0x007: NOP
-		"111011" & X"01B", -- 0x008: CALL 0x01B
-		"000000" & X"000", -- 0x009: NOP
-		"111100" & X"003", -- 0x00A: PUSH R03
-		"000000" & X"000", -- 0x00B: NOP
-		"111100" & X"002", -- 0x00C: PUSH R02
-		"000000" & X"000", -- 0x00D: NOP
-		"111100" & X"001", -- 0x00E: PUSH R01
-		"000000" & X"000", -- 0x00F: NOP
-		"111100" & X"000", -- 0x010: PUSH R00
-		"000000" & X"000", -- 0x011: NOP
-		"111101" & X"000", -- 0x012: POP R00
-		"000000" & X"000", -- 0x013: NOP
-		"111101" & X"001", -- 0x014: POP R01
-		"000000" & X"000", -- 0x015: NOP
-		"111101" & X"002", -- 0x016: POP R02
-		"000000" & X"000", -- 0x017: NOP
-		"111101" & X"003", -- 0x018: POP R03
-		"000000" & X"000", -- 0x019: NOP
-		"110000" & X"005", -- 0x01A: JMP 0x005
-		"111110" & X"000"  -- 0x01B: RET
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end reti_issue;
-

lib/CPUs/JCpu/src/reti_issue_xrom.vhdl

@@ -1,317 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY xrom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  dmem_addr_t;
-	dout		: out dmem_data_t
-	);
-END xrom;
-
-ARCHITECTURE reti_issue OF xrom IS 
-
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-
-	-- Assembled from reti_issue.jsm
-	constant xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"00", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end reti_issue;
-

lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl

@@ -1,413 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from reti_issue.jsm
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-	signal xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"00", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;

lib/CPUs/JCpu/src/tb_cpu_embedded.vhd

@@ -1,126 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for embedded cpu with rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY tb_cpu_embedded IS
-END tb_cpu_embedded;
-
-ARCHITECTURE behavior OF tb_cpu_embedded IS 
-
-	COMPONENT cpu_embedded
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out  STD_LOGIC;
-		xmem_we		: out STD_LOGIC;
-		xmem_re		: out STD_LOGIC;
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
-		io_sel		: out STD_LOGIC
-	);
-	END COMPONENT;
-
-	constant CLK_PERIOD : time := 10 ns;
-	type sram_t is array (integer range <>) of dmem_data_t;
-	signal rst : std_logic := '1';
-	signal clk : std_logic := '1';
-	signal ce  : std_logic := '0';
-	signal int_in : std_logic := '0';
-	signal int_ack : std_logic;
-	signal xmem_din : dmem_data_t := (others => '-');
-	signal xmem_dout : dmem_data_t;
-	signal xmem_addr : dmem_addr_t;
-	signal xmem_we : std_logic;
-	signal xmem_re : std_logic;
-	signal io_sel : std_logic;
-	signal sram : sram_t(0 to 2**dmem_addr_t'length-1);
-	
-
-BEGIN
-
-uut: cpu_embedded
-	PORT MAP(
-		rst => rst,
-		clk => clk,
-		ce => ce,
-		int_in => int_in,
-		int_ack => int_ack,
-		xmem_we => xmem_we,
-		xmem_re => xmem_re,
-		xmem_din => xmem_din,
-		xmem_dout => xmem_dout,
-		xmem_addr => xmem_addr,
-		io_sel => io_sel
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		rst <= '0';
-		wait for 2*CLK_PERIOD;
-	
-		wait until rising_edge(clk);
-		ce <= '1';
-	
-		wait for 1000*CLK_PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	
-	end process;
-
-SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we)
-	begin
-		if (rst = '1') then
-			xmem_din <= X"00";
-		elsif rising_edge(clk) then
-			if io_sel = '0' then
-				if xmem_we = '1' then	
-					sram(to_integer(xmem_addr)) <= xmem_dout;
-				end if;	
-				xmem_din <= to_01(sram(to_integer(xmem_addr)));
-			else
-				xmem_din <= X"FF";
-			end if;	
-		end if;
-	end process;
-	
-END;

lib/CPUs/JCpu/src/tb_cpu_itest.vhd

@@ -1,200 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Formal test of correct function of JCPU,
---            also writes 'opc.lst' for JASM-assembler
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-use work.cpu_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_cpu IS
-END tb_cpu;
-
-ARCHITECTURE behavior OF tb_cpu IS 
-
-	COMPONENT cpu
-	Generic (
-		use_instr_register	: boolean;
-		use_ctrl_rom		: boolean
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out  STD_LOGIC;
-		xmem_we		: out  STD_LOGIC;
-		xmem_re		: out  STD_LOGIC;
-		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
-		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		io_sel		: out  STD_LOGIC
-		
-	);
-	END COMPONENT;
-
-	COMPONENT irom
-		Port (
-			clk			: in  STD_LOGIC;
-			ce			: in  STD_LOGIC;
-			addr		: in  inst_addr_t;
-			dout		: out inst_t
-		);
-	END COMPONENT;
-
-	constant CLK_PERIOD : time := 10 ns;
-	type prom_t is array (integer range <>) of inst_t;
-	type sram_t is array (integer range <>) of dmem_data_t;
-	signal rst : std_logic := '1';
-	signal clk : std_logic := '1';
-	signal ce  : std_logic := '0';
-	signal int_in : std_logic := '0';
-	signal int_ack : std_logic;
-	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-');
-	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-	signal xmem_din : dmem_data_t := (others => '-');
-	signal xmem_dout : dmem_data_t;
-	signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0);
-	signal xmem_we : std_logic;
-	signal xmem_re : std_logic;
-	signal io_sel : std_logic;
-	signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1);
-	
-	type reg_t is record
-		revision : dmem_data_t;
-		testid : dmem_data_t;
-		interrupt : std_logic;
-	end record;	
-	
-	signal reg : reg_t;
-	
-
-BEGIN
-
-	int_in <= reg.interrupt;
-uut: cpu
-	GENERIC MAP
-	(	
-		use_instr_register	=> false,
-		use_ctrl_rom		=> true
-	)
-	PORT MAP(
-		rst => rst,
-		clk => clk,
-		ce => ce,
-		int_in => int_in,
-		int_ack => int_ack,
-		xmem_we => xmem_we,
-		xmem_re => xmem_re,
-		instr_din => irom_data,
-		instr_addr => irom_addr,
-		xmem_din => xmem_din,
-		xmem_dout => xmem_dout,
-		xmem_addr => xmem_addr,
-		io_sel => io_sel
-	);
-
-the_irom: irom
-	PORT MAP(
-		clk			=> clk,
-		ce			=> ce,
-		addr		=> irom_addr,
-		dout 		=> irom_data
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-STIMULUS: process
-	file RESULT:        text open write_mode is "../tools/opc.list"; 
-	variable L:         line;
-
-	begin
-
-		for i in 0 to instr_name_array'length-1 loop
-			fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
-		end loop;	
-
-		wait for 3*CLK_PERIOD;
-		rst <= '0';
-		wait for 2*CLK_PERIOD;
-	
-		wait until rising_edge(clk);
-		ce <= '1';
-	
-		assert false report "Test finished" severity error;
-		wait; 
-	
-	end process;
-
-SRAM_RW: process(rst, clk)
-	begin
-		if (rst = '1') then
-			reg.revision <= (others => '0');
-			reg.testid <= (others => '0');
-			reg.interrupt <= '0';
-		elsif rising_edge(clk) then
-			if int_ack = '1' then
---				reg.interrupt <= '0';
-			end if;	
-			if xmem_we = '1' then	
-				if io_sel = '0' then
-					sram(to_integer(xmem_addr)) <= xmem_dout;
-				else	
-					case xmem_addr is
-						when X"00" =>
-							reg.revision <= xmem_dout;
-						when X"01" =>
-							reg.testid <= xmem_dout;
-						when X"02" =>
-							reg.interrupt <= xmem_dout(0);
-						when others => null;
-					end case;
-				end if;	
-			else
-				if io_sel = '0' then
-					xmem_din <= to_01(sram(to_integer(xmem_addr)));
-				else
-					case xmem_addr is
-						when X"00" =>
-							xmem_din <= reg.revision;
-						when X"01" =>
-							xmem_din <= reg.testid;
-						when others =>
-							xmem_din <= X"BC";
-					end case;
-				end if;				
-			end if;	
-		end if;
-	end process;
-	
-END;

lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj

@@ -1,10 +0,0 @@
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu_pkg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\stack_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\reg_dual.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\pc.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\int_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\dpath_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipreg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipram.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\alu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu.vhd"

lib/CPUs/JCpu/tools/eval_scan.rb

@@ -1,42 +0,0 @@
-#!/usr/bin/env ruby
-
-str1 = %Q!lbl:		dc		"Hallo", ", ", 0, 1, " der","Jens"!
-
-i=0;
-
-def get_stri_lit (str)
-	res = [""];
-	state = "out"
-	
-	j = 0;
-	k = 0;
-	for i in (0..str.length-1)
-		c = str[i];
-		nstate = state
-		case state 
-		when "out"
-			if c == "\""[0]
-				nstate = "in"
-			end
-		when "in"	
-			if c == "\""[0]
-				nstate = "out"
-				if j > 0
-					k = k + 1;
-					res[k] = ""
-				end	
-			else
-				res[k] = res[k] + format("%c", c);
-				j = j + 1;
-			end
-		end
-		state = nstate
-	end;
-	return res
-end		
-	
-get_stri_lit(str1).each do |word|
-	puts word
-end	
- 	
- 

lib/CPUs/JCpu/tools/insrom.rb

@@ -1,46 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: Insertion of code fragments into templates
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-arg = $*
-rom_filename = arg[0].to_s
-tpl_filename = arg[1].to_s
-
-subst_pattern = "JASM_ROM_INSERT_HERE"
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-romfile = File.open(rom_filename, "r")
-tplfile = File.open(tpl_filename, "r")
-re = Regexp.new(subst_pattern)
-
-while (line = tplfile.gets)
-	puts line
-	line.scan(re).each do |word|
-		romfile.each do |raw_line|
-			puts raw_line
-		end	
-	end
-end

lib/CPUs/JCpu/tools/irom.vhd.tpl

@@ -1,32 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-

lib/CPUs/JCpu/tools/irom_ld.vhd.tpl

@@ -1,151 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY irom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  inst_addr_t;
-		dout		: out inst_t
-	);
-	
-END irom;
-
-ARCHITECTURE loadable OF irom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: inst_addr_t;
-	signal jtag_ld_dout		: inst_t;
-	signal jtag_ld_din		: inst_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (31 downto 0);
-	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
-	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;

lib/CPUs/JCpu/tools/jasm.bak.rb

@@ -1,494 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: A small assembler for the JCPU
-
-# Copyright (C) 2007 J. Ahrensfeld
-
-# This library is free software; you can redistribute it and/or
-# modify it under the terms of the GNU Lesser General Public
-# License as published by the Free Software Foundation; either
-# version 2.1 of the License, or (at your option) any later version.
-
-# This library is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# Lesser General Public License for more details.
-
-# You should have received a copy of the GNU Lesser General Public
-# License along with this library; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
-# For questions and ideas, please contact the author at jens@jayfield.org
-
-# ---------------------------------------------------------------------
-
-arg = $*
-MAX_SIZE_ROM = 1024
-PROJECT_NAME = arg.to_s.gsub(/\..*/, "")
-ENTITY_NAME = "rom"
-ENTITY_DATA_TYPE = "inst_t"
-ENTITY_ADDR_TYPE = "inst_addr_t"
-OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-filename = arg.to_s
-if !File.exists?(filename)
-	STDERR.puts "#{filename} does not exist"
-	exit 1
-end
-
-# --------------------------------------------------------
-# Pass 1
-# --------------------------------------------------------
-lc = 0	# Line counter
-pc = 0	# Program counter
-chip_dc = [0,0,0,0]	# chip data counter
-xmem_dc = 0	# xmem data counter
-curr_segment = "UNDEF";
-page = 0
-
-label_list=[[],[]]
-instr_list=[nil]
-file = File.open(filename, "r")
-file.each do |raw_line|
-	lc += 1
-
-	# Make all upper case
-	iline = "#{raw_line}".strip.upcase
-	
-	# Remove comments
-	iline = iline.gsub(/;.*/, "")
-	
-	# Split instruction at spaces
-	iline_member = iline.split(" ")
-
-	if iline_member[0] == nil
-		next
-	end	
-	
-	mc = 0;
-	label = nil
-	clean_line = nil
-	if (iline_member[0] =~ /\w+:/)
-		mc += 1
-		label = iline_member[0].delete(":")
-		if label_list.rindex(label) != nil
-			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
-			exit 1
-		end
-	end
-	
-	case iline_member[mc]
-	when nil
-		value = format("0x%3.3X",pc)
-	when "EQU"
-		if 0 == (iline_member[mc+1] =~ /\d+/)
-			value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
-		else 	
-			value = iline_member[mc+1]
-		end 	
-	when "ORG", "CODE"
-		pc = eval(iline_member[mc+1..iline_member.nitems].to_s)
-		value = format("0x%3.3X",pc)
-	when "CDATA", "CMEM"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: CDATA needs argument!", lc)
-			exit 1
-		end 	
-		curr_segment = "CMEM";
-		page = iline_member[mc+1].to_i(16)
-	when "XDATA", "XMEM"
-		curr_segment = "XMEM";
-	when "DC"
-		len = 0;
-		iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte| 
-			len += 1
-		end	
-		if curr_segment == "CMEM"
-			STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc)
-			exit 1
-		else
-			value = format("0x%2.2X",xmem_dc)
-			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
-			xmem_dc += len
-		end	
-	when "DB"
-		len = iline_member[mc+1].to_i
-		if curr_segment == "CMEM"
-			value = format("0x%2.2X",chip_dc[page])
-			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page);
-			chip_dc[page] += len
-		else
-			value = format("0x%2.2X",xmem_dc)
-			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
-			xmem_dc += len
-		end	
-	else
-		op_line = iline_member[mc+1..iline_member.nitems].to_s
-		value = format("0x%3.3X",pc)
-		opc = iline_member[mc]
-		if iline_member[mc+1] != nil
-			op1 = op_line.gsub(/,+.*$/, "")
-		end	
-		if iline_member[mc+2] != nil
-			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
-		end	
-		if instr_list[pc] == nil
-			instr_list[pc] = [lc, pc, opc , op1 , op2]
-			pc += 1
-		else
-			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc)
-			exit 1
-		end
-	end;	
-
-	# Push labels
-	if label	
-		label_list = label_list + [label, value]
-	end
-end
-file.close
-
-# --------------------------------------------------------
-def instr(opcode)
-	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
-end	
-
-def tcl_bits(pc, opcode)
-	return format("%10.10B%6.6B%12.12B",pc, opcode ,0)
-end
-
-def instr_k(opcode, k)
-	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
-end	
-
-def tcl_bits_k(pc, opcode, k)
-	return format("%10.10B%6.6B%12.12B",pc, opcode ,k)
-end
-
-def instr_r(opcode, r)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
-end	
-
-def tcl_bits_r(pc, opcode, r)
-	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r)
-end
-
-def instr_kr(opcode, k, r)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
-end	
-
-def tcl_bits_kr(pc, opcode, k, r)
-	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
-end
-
-def instr_rk(opcode, r, k)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
-end	
-
-def tcl_bits_rk(pc, opcode, r, k)
-	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
-end
-
-def instr_rr(opcode, ra, rb)
-	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
-end	
-
-def tcl_bits_rr(pc, opcode, ra, rb)
-	return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
-end
-
-# --------------------------------------------------------
-# Read mnemonic set
-# --------------------------------------------------------
-filename = OPC_LIST_NAME
-if !File.exists?(filename)
-	STDERR.puts "#{filename} does not exist"
-	exit 1
-end
-
-mnemo_list = []
-num_opcodes = 0
-file = File.open(filename, "r")
-file.each do |raw_line|
-	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
-	num_opcodes += 1
-end
-
-# --------------------------------------------------------
-# Pass 2
-# --------------------------------------------------------
-pc = 0
-opc_start = 2
-num_errors = 0
-vhdl_trans_list = [nil]
-vhdl_comment_list = [nil]
-vhdl_tcl_list = [nil]
-instr_list.each do |instruct|
-		
-	# puts instruct
-	if instruct == nil
-		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
-		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
-		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
-		pc += 1
-		next
-	end
-		
-	# determine arglen of instruction
-	ilen = 0
-	if instruct[opc_start+1] == nil
-		arglen = 0
-	elsif instruct[opc_start+2] == nil
-		arglen = 1
-	elsif instruct[opc_start+3] == nil
-		arglen = 2
-	end	
-	
-	# Symbol substitution
-	error = false
-	for i in (1..3)
-		subst_pos = opc_start+i
-		if instruct[subst_pos] == nil
-			next
-		end	
-		expr_token = ""
-		expr_subst = nil
-		is_direct = true;
-		
-#		instruct[subst_pos] = instruct[subst_pos].delete(" ")
-
-		# checks R0 .. R16, Mnemonics
-		instr_str = instruct[subst_pos]
-		if 0 == (instr_str =~ /\(.+\)/)
-			instr_str = instr_str.delete("()")
-			is_direct = false;
-		end	
-
-		expr_token = instr_str.split(/\+|\-|\*|\//)[0]
-		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
-			idx = label_list.rindex(expr_token)
-			if idx != nil
-				expr_subst = label_list[idx+1]
-				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
-			else
-				STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token)
-				error = true
-			end
-		end	
-		
-		if expr_subst != nil
-			if 0 == (expr_subst =~ /\d+/) 
-				if is_direct == true
-					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
-				else
-					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
-				end	
-			else
-				if 0 != (expr_subst =~ /R[0-9]+/)
-					STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst)
-					error = true
-				end
-			end
-		end	
-	end
-	
-	# Parse operands
-	reg = [0,0]
-	kk = 0
-	format = instruct[opc_start]
-	for i in (0..1)
-		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
-			# Check indirect addressing
-			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
-			format += "|R"
-			if reg[i] > 15
-				STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i])
-				error = true
-			end
-		else
-			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
-				kk = instruct[opc_start+i+1].delete("()").to_i(16)
-				format += "|K"
-			end
-		end
-		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
-			format += "i";
-		end
-	end 
-	
-	# Output instruction
-	opcode = mnemo_list.rindex(format).to_i
-	mnemo = instruct[2];
-
-	case format
-	when "NOP", "HALT", "RET", "RETI"
-		vhdl_trans_list[pc] = instr(opcode)
-		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
-		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
-	when "MOVC|R|Ri", "MOVX|R|Ri"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
-		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
-	when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
-		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
-	when "MOVC|Ri|R", "MOVX|Ri|R"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
-		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
-	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
-	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
-	when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
-	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
-		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
-		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
-	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
-		vhdl_trans_list[pc] = instr_k(opcode, kk)
-		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
-		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
-	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R"
-		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
-		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-	when "TST|R"
-		kk = 0
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("CMP|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "INC|R"
-		kk = 1
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("ADD|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "DEC|R"
-		kk = 1
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("SUB|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	else
-		STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format)
-		error = true
-	end
-
-	if error
-		num_errors += 1
-		break
-	end
-	vhdl_comment_list[pc] = minstr_comment
-
-	puts vhdl_trans_list[pc] + " -- " + minstr_comment
-	
-	pc += 1
-end
-
-# --------------------------------------------------------
-# Output ROM file
-# --------------------------------------------------------
-if num_errors == 0
-
-	filename = format("rom_%s.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("ENTITY %s IS\n", ENTITY_NAME)
-	file.puts format("\tPort (\n")
-	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\taddr\t\t: in  %s;\n", ENTITY_ADDR_TYPE)
-	file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE)
-	file.puts format("\t);\n")
-	file.puts format("END %s;\n", ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE)
-	file.puts format("\n")
-	file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..pc-2)
-		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
-	end;
-	file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
-	file.puts format("\t);\n")
-	file.puts format("\n")
-	file.puts format("begin")
-	file.puts format("\n")
-	file.puts format("PROM_READ:")
-	file.puts format("\tprocess(clk, ce)\n")
-	file.puts format("\tbegin\n")
-	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
-	file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n")
-	file.puts format("\t\tend if;\n")
-	file.puts format("\tend process;\n")
-	file.puts format("\n")
-	file.puts format("end %s;\n", PROJECT_NAME)
-	puts format("ROM file written to \"%s\"\n",filename)
-	file.close
-end
-if num_errors == 0
-
-	filename = format("preinit_%s.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..pc-2)
-		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
-	end;
-	if pc < (MAX_SIZE_ROM-1)
-		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
-		for i in (pc..(MAX_SIZE_ROM-2))
-			file.puts "\t\t" + instr(0) + ",\n"
-		end;
-		file.puts "\t\t" + instr(0) + "\n"
-	else
-		file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
-	end	
-	file.puts format("\t);\n")
-	puts format("PREINIT file written to \"%s\"\n",filename)
-	file.close
-end
-if num_errors == 0
-	filename = format("rom_%s.tcl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-	for i in (0..pc-1)
-		# Chipscope 8.1
-#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
-
-		# Chipscope 9.1
-		file.puts format("\# %s", vhdl_comment_list[i]) 
-		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
-	end;
-	puts format("TCL snippet written to \"%s\"\n",filename)
-	file.close
-end
-
-# --------------------------------------------------------
-# Output final statistics
-# --------------------------------------------------------
-if num_errors == 0
-	puts "Program uses #{pc} instruction addresses"
-	puts "No errors found"
-	exit 0
-else
-	puts "#{num_errors} errors found"
-	exit 1
-end	

lib/CPUs/JCpu/tools/jasm.rb

@@ -1,814 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: A small assembler for the JCPU
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-arg = $*
-FILE_SUFFIX = "jsm"
-IROM_MAX_SIZE = 1024
-IROM_ENTITY_NAME = "irom"
-IROM_DATA_TYPE = "inst_t"
-IROM_ADDR_TYPE = "inst_addr_t"
-XROM_MAX_SIZE = 256
-XROM_DATA_TYPE = "dmem_data_t"
-XROM_ADDR_TYPE = "dmem_addr_t"
-XROM_ENTITY_NAME = "xrom"
-OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
-
-# --------------------------------------------------------
-class Parser
-	def curr_segment
-		@curr_segment
-	end	
-	def curr_segment=(arg)
-		@curr_segment=arg
-	end	
-	def add_label(labelname, addr)
-		@label_list = @label_list + [labelname, addr]
-	end
-	def	getLabelIdByName(label)
-		return @label_list.rindex(label)
-	end
-	def	getLabelNameById(id)
-		return @label_list[id]
-	end
-	def put_instr(name, lc, opc , op1 , op2)
-		if get_instr != nil
-			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc)
-			exit 1
-		end
-		@instr_list[@pc] = [lc, @pc, opc , op1 , op2, name]
-	end
-	def	get_instr
-		return @instr_list[@pc]
-	end
-	def put_xmem(value, lc)
-		if get_xmem != nil
-			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment)
-			exit 1
-		end
-		@xmem[xmem_dc] = value
-		@xmem_dc = xmem_dc + 1
-	end	
-	def get_xmem
-		return @xmem[xmem_dc]
-	end	
-	def xmem
-		return @xmem
-	end	
-	def put_cmem(value, lc)
-		if get_cmem(page) != nil
-			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment)
-			exit 1
-		end
-		@cmem[page][cmem_dc] = value
-		@cmem_dc[page] = cmem_dc + 1
-	end	
-	def get_cmem(pg)
-		return @cmem[pg][cmem_dc]
-	end	
-	def cmem(page)
-		return @cmem[page]
-	end	
-	def	cmem_dc=(addr)
-		@cmem_dc[page] = addr
-	end	
-	def	cmem_dc
-		@cmem_dc[page]
-	end	
-	def	xmem_dc=(addr)
-		@xmem_dc = addr
-	end	
-	def	xmem_dc
-		@xmem_dc
-	end	
-	def page=(page)
-		@page = page;
-	end	
-	def page
-		@page;
-	end	
-	def pc=(pc)
-		@pc = pc;
-		if (pc > @pc_max)
-			@pc_max = pc
-		end	
-	end	
-	def pc
-		@pc;
-	end	
-	def pc_max
-		@pc_max;
-	end	
-	def	instr_list
-		@instr_list
-	end
-	def	label_list
-		@label_list
-	end
-	
-	def initialize()
-		@pc_max = 0
-		@pc = 0					# Program counter
-		@cmem_dc = [0,0,0,0]	# chip data counter
-		@xmem_dc = 0			# xmem data counter
-		@curr_segment = "UNDEF";
-		@page = 0
-		@label_list=[[],[]]
-		@instr_list=[nil]
-		@cmem = [[],[]];
-		@xmem = [];
-	end
-	def method_missing(name, *args)
-		puts "I don't know the method #{name}"
-	end
-end	
-
-# --------------------------------------------------------
-def parse(name, obj)
-
-lc = 0	# Line counter
-file = File.open(name, "r")
-
-file.each do |raw_line|
-	lc += 1
-
-	# Make all upper case
-	iline = "#{raw_line}".strip
-	
-	# Remove comments
-	iline = iline.gsub(/;.*/, "")
-	
-	# Split instruction at spaces
-	iline_member = iline.split(" ")
-
-	if iline_member[0] == nil
-		next
-	end	
-	
-	mc = 0;
-	label = nil
-	clean_line = nil
-	if (iline_member[0] =~ /\w+:/)
-		mc += 1
-		label = iline_member[0].delete(":")
-		if obj.getLabelIdByName(label) != nil
-			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
-			exit 1
-		end
-	end
-	
-	token = iline_member[mc]
-	if token
-		token = token.upcase
-	end
-	
-	case token
-	when nil
-		if obj.curr_segment == "CMEM"
-			curr_addr = format("0x%3.3X",obj.cmem_dc)
-		elsif obj.curr_segment == "XMEM"
-			curr_addr = format("0x%3.3X",obj.xmem_dc)
-		elsif obj.curr_segment == "CODE"
-			curr_addr = format("0x%3.3X",obj.pc)
-		else
-			STDERR.puts format("Error in line %d: Undefined segment", lc)
-			exit 1
-		end
-	when "INCLUDE"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		inc_name = iline_member[mc+1].delete("\"")
-		puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc);
-		parse(inc_name, obj)
-	when "EQU"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		if 0 == (iline_member[mc+1] =~ /\d+/)
-			curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
-		else 	
-			curr_addr = iline_member[mc+1]
-		end 	
-	when "ORG"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		offset = eval(iline_member[mc+1..iline_member.nitems].to_s)
-		case obj.curr_segment
-			when "CODE"
-			obj.pc = offset
-			curr_addr = format("0x%3.3X",obj.pc)
-			when "CMEM"
-			obj.cmem_dc = offset
-			when "XMEM"
-			obj.xmem_dc = offset
-			
-		end	
-	when "CODE"
-		curr_addr = format("0x%3.3X",obj.pc)
-		obj.curr_segment = "CODE";
-	when "CDATA", "CMEM"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		obj.curr_segment = "CMEM";
-		obj.page = iline_member[mc+1].to_i(16)
-	when "XDATA", "XMEM"
-		obj.curr_segment = "XMEM";
-	when "DC"
-		len = 0;
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		if obj.curr_segment == "CMEM"
-			STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment)
-			exit 1
-		elsif obj.curr_segment == "XMEM"
-			curr_addr = format("0x%2.2X",obj.xmem_dc)
-			dc_old = obj.xmem_dc;
-			val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",")
-			
-			# Parse string literals
-			val_array.each do |item| 
-				if 0 == (item =~ /.*\".*\"/)
-					str = item.delete("\"")
-					puts item
-					for nn in (0..str.length-1)
-						if str[nn] > 31
-							obj.put_xmem(str[nn], lc);
-						 	puts "S: " + str[nn].to_s
-							len += 1
-						end	
-					end;
-				else
-					argument = item
-					puts "B: " + argument
-					obj.put_xmem(eval(argument), lc);
-					len += 1
-				end	
-			end	
-			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment);
-		else	
-			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
-			exit 1
-		end	
-	when "DB"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		len = eval(iline_member[mc+1]).to_i
-		if obj.curr_segment == "CMEM"
-			curr_addr = format("0x%2.2X",obj.cmem_dc)
-			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page);
-			for nn in (1..len)
-				obj.put_cmem(0, lc)
-			end	
-		elsif obj.curr_segment == "XMEM"
-			curr_addr = format("0x%2.2X",obj.xmem_dc)
-			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment);
-			for nn in (1..len)
-				obj.put_xmem(0, lc)
-			end	
-		else	
-			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
-			exit 1
-		end	
-	else
-		if obj.curr_segment != "CODE"
-			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
-			exit 1
-		end			
-
-		op_line = iline_member[mc+1..iline_member.nitems].to_s
-		curr_addr = format("0x%3.3X",obj.pc)
-		opc = token
-		if iline_member[mc+1] != nil
-			op1 = op_line.gsub(/,+.*$/, "")
-		end	
-		if iline_member[mc+2] != nil
-			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
-		end	
-		obj.put_instr(name, lc, opc, op1, op2)
-		obj.pc = obj.pc + 1
-	end;	
-
-	# Push labels
-	if label	
-		obj.add_label(label, curr_addr)
-	end
-end
-file.close
-return obj
-end
-
-# --------------------------------------------------------
-# Instruction formatting
-# --------------------------------------------------------
-def instr(opcode)
-	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
-end	
-
-def tcl_bits(pc, opcode)
-	return format("%12.12B%8.8B%12.12B",pc, opcode ,0)
-end
-
-def instr_k(opcode, k)
-	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
-end	
-
-def tcl_bits_k(pc, opcode, k)
-	return format("%12.12B%8.8B%12.12B",pc, opcode ,k)
-end
-
-def instr_r(opcode, r)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
-end	
-
-def tcl_bits_r(pc, opcode, r)
-	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r)
-end
-
-def instr_kr(opcode, k, r)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
-end	
-
-def tcl_bits_kr(pc, opcode, k, r)
-	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
-end
-
-def instr_rk(opcode, r, k)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
-end	
-
-def tcl_bits_rk(pc, opcode, r, k)
-	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
-end
-
-def instr_rr(opcode, ra, rb)
-	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
-end	
-
-def tcl_bits_rr(pc, opcode, ra, rb)
-	return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
-end
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-filename = arg.to_s
-if !File.exists?(filename)
-	STDERR.puts "#{filename} does not exist"
-	exit 1
-end
-PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX)
-
-# --------------------------------------------------------
-# Pass 1
-# --------------------------------------------------------
-first_pass = Parser.new();
-parse(filename, first_pass)
-
-# --------------------------------------------------------
-# Read mnemonic set
-# --------------------------------------------------------
-filename = OPC_LIST_NAME
-if !File.exists?(filename)
-	STDERR.puts "#{filename} does not exist"
-	exit 1
-end
-
-mnemo_list = []
-num_opcodes = 0
-file = File.open(filename, "r")
-file.each do |raw_line|
-	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
-	num_opcodes += 1
-end
-
-# --------------------------------------------------------
-# Pass 2
-# --------------------------------------------------------
-pc = 0
-opc_start = 2
-num_errors = 0
-vhdl_trans_list = [nil]
-vhdl_comment_list = [nil]
-vhdl_tcl_list = [nil]
-
-# ToDo: Use class-methods
-label_list = first_pass.label_list
-instr_list = first_pass.instr_list
-
-instr_list.each do |instruct|
-		
-	# puts instruct
-	if instruct == nil
-		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
-		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
-		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
-		pc += 1
-		next
-	end
-		
-	# determine arglen of instruction
-	ilen = 0
-	if instruct[opc_start+1] == nil
-		arglen = 0
-	elsif instruct[opc_start+2] == nil
-		arglen = 1
-	elsif instruct[opc_start+3] == nil
-		arglen = 2
-	end	
-	
-	# Symbol substitution
-	error = false
-	for i in (1..2)
-		subst_pos = opc_start+i
-		if instruct[subst_pos] == nil
-			next
-		end	
-		expr_token = ""
-		expr_subst = nil
-		is_direct = true;
-		
-		# checks R0 .. R16, Mnemonics
-		instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "")
-		if (nil != (instruct[subst_pos] =~ /'high/))
-			instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, ""))
-		end	
-		instr_str = instruct[subst_pos]
-		if 0 == (instr_str =~ /\(.+\)/)
-			instr_str = instr_str.delete("()")
-			is_direct = false;
-		end	
-
-		expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0]
-		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
-			idx = label_list.rindex(expr_token)
-			if idx != nil
-				expr_subst = label_list[idx+1]
-				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
-			else
-				STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token)
-				error = true
-			end
-		end	
-		
-		if expr_subst != nil
-			if 0 == (expr_subst =~ /\d+/) 
-				if is_direct == true
-					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
-				else
-					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
-				end	
-			else
-				if 0 != (expr_subst =~ /R[0-9]+/)
-					STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst)
-					error = true
-				end
-			end
-		end	
-	end
-	
-	# Parse operands
-	reg = [0,0]
-	kk = 0
-	format = instruct[opc_start]
-	for i in (0..1)
-		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
-			# Check indirect addressing
-			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
-			format += "|R"
-			if reg[i] > 15
-				STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i])
-				error = true
-			end
-		else
-			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
-				kk = eval(instruct[opc_start+i+1].delete("()"))
-				format += "|K"
-			end
-		end
-		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
-			format += "i";
-		end
-	end 
-	
-	if error
-		num_errors += 1
-		break
-	end
-
-	# Output instruction
-	opcode = mnemo_list.rindex(format).to_i
-	mnemo = instruct[2];
-
-	case format
-	# Native instructions
-	when "NOP", "HALT", "RET", "RETI", "SETC"
-		vhdl_trans_list[pc] = instr(opcode)
-		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
-		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
-	when "MOVC|R|Ri", "MOVX|R|Ri"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
-		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
-	when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
-		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
-	when "MOVC|Ri|R", "MOVX|Ri|R"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
-		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
-	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
-		kk = kk % 256;
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
-	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
-	when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
-		kk = kk % 256;
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
-	when "SUB|K|R", "SUBC|K|R"
-		kk = kk % 256;
-		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
-		minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1])
-	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
-		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
-		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
-	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
-		vhdl_trans_list[pc] = instr_k(opcode, kk)
-		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
-		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
-	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R"
-		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
-		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-	# Synthetic instructions
-	when "CLRC"
-		kk = 0;
-		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
-		opcode = mnemo_list.rindex("SUB|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "TST|R"
-		kk = 0
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("CMP|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "NEG|R"
-		kk = 0
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("SUB|K|R").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "NOT|R"
-		kk = 0
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("XOR|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "INC|R"
-		kk = 1
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("ADD|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "DEC|R"
-		kk = 1
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("SUB|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	else
-		STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format)
-		error = true
-	end
-
-	if error
-		num_errors += 1
-		break
-	end
-
-	vhdl_comment_list[pc] = minstr_comment
-
-	puts vhdl_trans_list[pc] + " -- " + minstr_comment
-	
-	pc += 1
-end
-
-# --------------------------------------------------------
-# Output ROM file
-# --------------------------------------------------------
-if num_errors == 0
-
-	# I-ROM VHDL-ROM
-	filename = format("%s.irom.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME)
-	file.puts format("\tPort (\n")
-	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\taddr\t\t: in  %s;\n", IROM_ADDR_TYPE)
-	file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE)
-	file.puts format("\t);\n")
-	file.puts format("END %s;\n", IROM_ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE)
-	file.puts format("\n")
-	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("\tconstant imem_rom : imem_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..[IROM_MAX_SIZE, pc].min-2)
-		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
-	end;
-	file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
-	file.puts format("\t);\n")
-	file.puts format("\n")
-	file.puts format("begin")
-	file.puts format("\n")
-	file.puts format("PROM_READ:")
-	file.puts format("\tprocess(clk, ce)\n")
-	file.puts format("\tbegin\n")
-	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
-	file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n")
-	file.puts format("\t\tend if;\n")
-	file.puts format("\tend process;\n")
-	file.puts format("\n")
-	file.puts format("end %s;\n", PROJECT_NAME)
-	puts format("I-ROM file written to \"%s\"\n",filename)
-	file.close
-
-	# I-ROM VHDL-ROM (loadable)
-	filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE)
-	file.puts format("\tsignal imem_rom : imem_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..pc-2)
-		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
-	end;
-	if pc < (IROM_MAX_SIZE-1)
-		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
-		for i in (pc..(IROM_MAX_SIZE-2))
-			file.puts "\t\t" + instr(0) + ",\n"
-		end;
-		file.puts "\t\t" + instr(0) + "\n"
-	else
-		file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
-	end	
-	file.puts format("\t);\n")
-	puts format("I-ROM (loadable) file written to \"%s\"\n",filename)
-	file.close
-
-	# I-ROM TCL-Loader
-	filename = format("%s.irom.tcl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("# ---------------------------------------------------------------");
-	file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA");
-	file.puts format("# User 1")
-	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n")
-	for i in (0..pc-1)
-		# Chipscope 8.1
-#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
-
-		# Chipscope 9.1
-		file.puts format("\# %s", vhdl_comment_list[i]) 
-		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
-	end;
-	puts format("I-ROM TCL-loader written to \"%s\"\n",filename)
-	file.close
-
-	# X-ROM VHDL-ROM
-	filename = format("%s.xrom.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME)
-	file.puts format("\tPort (\n")
-	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\taddr\t\t: in  %s;\n", XROM_ADDR_TYPE)
-	file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE)
-	file.puts format("\t);\n")
-	file.puts format("END %s;\n", XROM_ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
-	file.puts format("\n")
-	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..XROM_MAX_SIZE-2)
-		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
-	end;
-	i = XROM_MAX_SIZE-1
-	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i], i)
-	file.puts format("\t);\n")
-	file.puts format("\n")
-	file.puts format("begin")
-	file.puts format("\n")
-	file.puts format("PROM_READ:")
-	file.puts format("\tprocess(clk, ce)\n")
-	file.puts format("\tbegin\n")
-	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
-	file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n")
-	file.puts format("\t\tend if;\n")
-	file.puts format("\tend process;\n")
-	file.puts format("\n")
-	file.puts format("end %s;\n", PROJECT_NAME)
-	puts format("X-ROM file written to \"%s\"\n",filename)
-	file.close
-
-	# X-ROM VHDL-ROM (loadable)
-	filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
-	file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..XROM_MAX_SIZE-2)
-		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
-	end;
-	i = XROM_MAX_SIZE-1
-	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i], i)
-	file.puts format("\t);\n")
-	puts format("X-ROM (loadable) file written to \"%s\"\n",filename)
-	file.close
-
-	# X-ROM TCL-Loader
-	filename = format("%s.xrom.tcl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("# ---------------------------------------------------------------");
-	file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA");
-	file.puts format("# User 2")
-	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n")
-	for i in (0..first_pass.xmem.length-1)
-		# Chipscope 8.1
-#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
-
-		# Chipscope 9.1
-		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]);
-	end;
-	puts format("X-ROM TCL-loader written to \"%s\"\n",filename)
-	file.close
-
-end
-
-# --------------------------------------------------------
-# Output final statistics
-# --------------------------------------------------------
-if num_errors == 0
-	puts "Program uses #{first_pass.pc_max} instruction addresses"
-	puts "No errors found"
-	exit 0
-else
-	puts "#{num_errors} errors found"
-	exit 1
-end	
-

lib/CPUs/JCpu/tools/lib/cg.inc.jsm

@@ -1,72 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xio-address equates for
-; reg_cg_char_addr:	equ		0xXX	; RW
-; reg_cg_line_addr:	equ		0xXX	; RW
-; reg_cg_data:		equ		0xXX	; RW
-; reg_cg_ctrl:		equ		0xXX	; WO
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-cg_clr_line:	push	R0
-				mov		R0, 2
-				xout	(reg_cg_ctrl), R0	
-				pop		R0
-				ret
-				
-; -------------------------------------------------
-cg_clr_screen:	push	R0
-				mov		R0, 1
-				xout	(reg_cg_ctrl), R0	
-				pop		R0
-				ret
-				
-; -------------------------------------------------
-; R0 : char address
-; R1 : line address
-cg_set_addr:	call	cg_wait_rdy
-				xout	(reg_cg_line_addr), R1
-				xout	(reg_cg_char_addr), R0
-				ret
-
-; -------------------------------------------------
-; R0 : character
-cg_putchar:		call	cg_wait_rdy
-				xout	(reg_cg_data), R0
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts:		push	R0
-cg_p_lp:		movx	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		ex_cgp
-				call	cg_putchar
-				jmp		cg_p_lp
-ex_cgp:			pop		R0
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_clr_puts:	call	cg_clr_line
-				call	cg_puts
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts_clr:	call	cg_puts
-				call	cg_clr_line
-				ret				
-
-; -------------------------------------------------
-cg_wait_rdy:	push	R0
-cg_wr_lp:		xin		R0, (reg_hwstat)
-				and		R0, 0x02
-				jz		cg_wr_lp
-				pop		R0
-				ret
-
-; -------------------------------------------------

lib/CPUs/JCpu/tools/lib/cregs.inc.jsm

@@ -1,7 +0,0 @@
-; JCPU On-Chip register
-cpu_revision:		equ		0x00	; RO
-cpu_control:		equ		0x01	; R/W
-cpu_status:			equ		0x02	; RO
-cpu_int_ctrl:		equ		0x03	; RW
-cpu_cmem_high:		equ		0x04	; RW
-cpu_stack_high:		equ		0x05	; RW

lib/CPUs/JCpu/tools/lib/delays.inc.jsm

@@ -1,64 +0,0 @@
-; -------------------------------------------------
-; Delays
-; -------------------------------------------------
-delay1s:		push	R15
-				mov		R15, 10
-loop1s:			call 	delay100ms		
-				dec		R15
-				jnz		loop1s
-				pop		R15
-				ret
-
-delay100ms:		push	R15
-				mov		R15, 10
-loop100ms:		call 	delay10ms		
-				dec		R15
-				jnz		loop100ms
-				pop		R15
-				ret
-			
-delay10ms:		push	R15
-				mov		R15, 10
-loop10ms:		call	delay1ms		
-				dec		R15
-				jnz		loop10ms
-				pop		R15
-				ret
-		
-delay1ms:		push	R15
-				mov		R15, 10
-loop1ms:		call	delay100us
-				dec		R15
-				jnz		loop1ms
-				pop		R15
-				ret
-
-delay100us:		push	R15
-				mov		R15, 10
-loop100us:		call	delay10us
-				dec		R15
-				jnz		loop100us
-				pop		R15
-				ret
-
-delay10us:		push	R15
-				mov		R15, 99
-loop10us:		nop
-				nop
-				nop
-				dec		R15
-				jnz		loop10us
-				pop		R15
-				ret
-
-delay1us:		push	R15
-				mov		R15, 9
-loop1us:		nop
-				nop
-				nop
-				dec		R15
-				jnz		loop1us
-				pop		R15
-				ret
-				
-; -------------------------------------------------

lib/CPUs/JCpu/tools/lib/lcd.inc.jsm

@@ -1,208 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - lcd_port (LCD-Base)
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-lcd_cmd:		equ		0x00
-lcd_rd:			equ		0x20
-lcd_data:		equ		0x40
-lcd_enable:		equ		0x80
-
-LCD_CMD_Z1:		equ		0x80
-LCD_CMD_Z2:		equ		0xC0
-LCD_CMD_CLEAR:	equ		0x01
-
-; -------------------------------------------------
-; Init LCD
-; -------------------------------------------------
-LCD_init:		mov		R2, 0x00		
-				mov		R0, 0x03
-				call	_write_lcd
-				call	delay10ms
-				mov		R2, 0x00		
-				mov		R0, 0x03
-				call	_write_lcd
-				call	delay10ms
-
-				mov		R2, 0x00		
-				mov		R0, 0x02
-				call	_write_lcd
-				call	delay1ms
-
-				; 1. Function set: 4-Bit mode, two display lines
-				mov		R0, 0x28
-				call	LCD_writecmd
-
-				; 2. Display on, no cursor
-				mov		R0, 0x0C		
-				call	LCD_writecmd
-
-				; 3. Cursor shift during write
-				mov		R0, 0x06
-				call	LCD_writecmd
-
-				; 4. Display clear
-				mov		R0, 0x01
-				call	LCD_writecmd
-
-				ret
-				
-; -------------------------------------------------
-; LCD_waitbsy
-; -------------------------------------------------
-LCD_waitbsy:	push	R0
-bsy_loop:		call	LCD_readstat
-				and		R0, 0x80
-				jz		ex_bsy
-				call	delay1us
-				jmp		bsy_loop
-ex_bsy:			pop		R0
-				ret
-
-; -------------------------------------------------
-; LCD_writecmd
-; -------------------------------------------------
-; R0 = cmd
-LCD_writeaddr:
-LCD_writecmd:	push	R2
-				mov		R2, lcd_cmd
-				call	LCD_write
-				pop		R2
-				ret
-
-; -------------------------------------------------
-; LCD_putsx
-; -------------------------------------------------
-; R1 = address of null-terminated string in XMEM
-LCD_putsx:		push	R0
-putsx_loop:		movx	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		putsx_ex
-				call	LCD_writechar
-				jmp		putsx_loop
-putsx_ex:		pop		R0
-				ret
-				
-; -------------------------------------------------
-; LCD_putsc
-; -------------------------------------------------
-; R1 = address of null-terminated string in CMEM
-LCD_putsc:		push	R0
-putsc_loop:		movc	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		putsc_ex
-				call	LCD_writechar
-				jmp		putsc_loop
-putsc_ex:		pop		R0
-				ret
-				
-; -------------------------------------------------
-; LCD_writechar
-; -------------------------------------------------
-; R0 = char
-LCD_writedata:
-LCD_writechar:	push	R2
-				mov		R2, lcd_data
-				call	LCD_write
-				pop		R2
-				ret
-				
-; -------------------------------------------------
-; LCD_write
-; -------------------------------------------------
-; R0 = input
-; R2 = register
-LCD_write:		call	LCD_waitbsy
-				push	R0
-				swap	R0
-				call	_write_lcd
-				pop		R0
-				call	_write_lcd
-				ret
-
-; -------------------------------------------------
-; LCD_readstat
-; -------------------------------------------------
-; R0 = status
-LCD_readstat:	push	R2
-				mov		R2, lcd_cmd
-				call	LCD_read
-				pop		R2
-				ret
-
-; -------------------------------------------------
-; LCD_read
-; -------------------------------------------------
-; R0 = output
-; R2 = register
-LCD_read:		call	_read_lcd
-				swap	R0
-				push	R0
-				call	_read_lcd
-				pop		R2
-				or		R0, R2
-				ret
-				
-; -------------------------------------------------
-; _write
-; -------------------------------------------------
-; R0 = input
-_write_lcd:		push	R1
-
-				and		R0, 0x0F
-				mov		R1, R0
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, R0
-				or		R1, R2
-				or		R1, lcd_enable
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, R0
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				or		R1, lcd_rd
-				xout	(lcd_port), R1
-
-				pop		R1
-				ret
-
-; -------------------------------------------------
-; _read
-; -------------------------------------------------
-; R0 = output
-_read_lcd:		push	R1
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				or		R1, lcd_enable
-				xout	(lcd_port), R1
-				call	delay1us
-				xin		R0, (lcd_port)
-				and		R0, 0x0F
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				pop		R1
-				ret
-
-				

lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm

@@ -1,42 +0,0 @@
-; -------------------------------------------------
-; mul8x8.inc.jsm
-; -------------------------------------------------
-
-; -------------------------------------------------
-; Parameter:
-; R0 : operand 1
-; R1 : operand 2
-; Return:
-; R0 : product low
-; R1 : product high
-mul8x8:			push	R2
-				push	R3
-				push	R4
-				
-				mov		R4, R1
-				mov		R1, 0
-				mov		R2, 0
-				mov		R3, 0
-				
-loop1:			cmp		R4, 0x01
-				jeq		ende1
-
-				shr		R4
-				jnc		next1
-
-				add		R2, R0
-				addc	R3, R1
-
-next1:			shl		R0
-				rolc	R1
-				jmp		loop1
-				
-ende1:			add		R0, R2
-				addc	R1, R3
-				
-				pop		R4
-				pop		R3
-				pop		R2
-				ret
-
-; -------------------------------------------------

lib/CPUs/JCpu/tools/lib/uart.inc.jsm

@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; uart.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - uart_status (Status register)
-; - uart_data	(Data register)
-
-; -------------------------------------------------
-; sout
-; -------------------------------------------------
-; R0 = input
-sout:			push 	R1
-sout1:			xin		R1, (uart_status)
-				and		R1, 0x02
-				jnz		sout1
-				xout	(uart_data), R0
-				pop		R1
-				ret
-
-; -------------------------------------------------
-; sin
-; -------------------------------------------------
-; R0 = output
-sin:			push 	R1
-sin1:			xin		R1, (uart_status)
-				and		R1, 0x10
-				jnz		sin1
-				xin		R0, (uart_data)
-				pop		R1
-				ret
-
-; -------------------------------------------------

lib/CPUs/JCpu/tools/lib/utils.inc.jsm

@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; utils.inc.jsm
-; -------------------------------------------------
-
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value in lower nibble
-; Return
-; R0 : Hex character representing lower nibble
-nibble2hex:		and		R0, 0x0F
-				cmp		R0, 0x0A
-				jlt		isNum1
-				add		R0, 0x07
-isNum1:			add		R0, 0x30
-				ret
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value
-; Return
-; R0 : Hex character high
-; R1 : Hex character low
-bin2hex:		push	R0
-				call	nibble2hex
-				mov		R1, R0
-				pop		R0
-				swap	R0
-				call	nibble2hex
-				ret
-
-; -------------------------------------------------

lib/CPUs/JCpu/tools/opc.list

@@ -1,64 +0,0 @@
-0 NOP         
-1 HALT        
-2 MOV|R|R     
-3 MOV|R|K     
-4 MOVX|R|Ri   
-5 MOVX|R|Ki   
-6 MOVX|Ri|R   
-7 MOVX|Ri|K   
-8 MOVX|Ki|R   
-9 MOVC|R|Ri   
-10 MOVC|R|Ki   
-11 MOVC|Ri|R   
-12 MOVC|Ri|K   
-13 MOVC|Ki|R   
-14 CMP|R|R     
-15 CMP|R|K     
-16 ADD|R|R     
-17 ADD|R|K     
-18 ADDC|R|R    
-19 ADDC|R|K    
-20 SUB|R|R     
-21 SUB|R|K     
-22 SUBC|R|R    
-23 SUBC|R|K    
-24 AND|R|R     
-25 AND|R|K     
-26 OR|R|R      
-27 OR|R|K      
-28 XOR|R|R     
-29 XOR|R|K     
-30 SHL|R       
-31 SHR|R       
-32 ROL|R       
-33 ROR|R       
-34 ROLC|R      
-35 RORC|R      
-36 XOUT|Ki|R   
-37 XOUT|Ri|K   
-38 COUT|Ki|R   
-39 COUT|Ri|K   
-40 XIN|R|Ki    
-41 CIN|R|Ki    
-42 SWAP|R      
-43 SETC        
-44 UNDEF       
-45 UNDEF       
-46 SUB|K|R     
-47 SUBC|K|R    
-48 JMP|K       
-49 JZ|K        
-50 JNZ|K       
-51 JC|K        
-52 JNC|K       
-53 JLT|K       
-54 JGT|K       
-55 JLE|K       
-56 JGE|K       
-57 JEQ|K       
-58 JNE|K       
-59 CALL|K      
-60 PUSH|R      
-61 POP|R       
-62 RET         
-63 RETI        

lib/CPUs/JCpu/tools/regx.rb

@@ -1,20 +0,0 @@
-#!/usr/bin/env ruby
-
-st = "\033[7m"
-en = "\033[m"
-
- while TRUE
-   print "str> "
-   STDOUT.flush
-   str = gets
-   break if not str
-   str.chop!
-   print "pat> "
-   STDOUT.flush
-   re = gets
-   break if not re
-   re.chop!
-   str.gsub! re, "#{st}\\&#{en}"
-   print str, "\n"
-end
-print "\n"

lib/CPUs/JCpu/tools/rom.tcl.tpl

@@ -1,61 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit

lib/CPUs/JCpu/tools/templates.rb

@@ -1,44 +0,0 @@
-#!/usr/bin/env ruby
-
-
-template = <<'END'
-		-- (tv #1342) read output FIFO
-		(
-			cycles		=>	1,
-			cm_i		=>	bus_read_init(addr => ADDR_KS_OFIFO_DOUT),
-			sep			=>	msg(""),
-			cm_o 		=>	bus_no_ack,
-			irq			=>	(others => '0')
-		),
-
-		-- (tv #1343) wait while FIFO is read
-		(
-			cycles		=>	2,
-			cm_i		=>	bus_wait_ack,
-			sep			=>	msg(""),
-			cm_o 		=>	bus_no_ack,
-			irq			=>	(others => '0')
-		),
-
-		-- (tv #1343) wait for ack
-		(
-			cycles		=>	1,
-			cm_i		=>	bus_wait_ack,
-			sep			=>	msg(""),
-			cm_o 		=>	bus_read_ack(dat => #{exp_data}),
-			irq			=>	(others => '0')
-		),
-
-END
-
-puts "KS-128 testvectors:\n"
-puts "\n" * 3
-
-
-0.upto(10) { |sk_no|
-	3.downto(0) { |sl_no|
-		exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})"
-		t = template.gsub(/"/, '\\"')
-		puts eval("format(\"#{t}\")")
-	}
-}

lib/CPUs/JCpu/tools/xrom.vhd.tpl

@@ -1,32 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-

lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl

@@ -1,151 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;

lib/CPUs/MIPS/bsp/examples/.directory_history

@@ -0,0 +1,34 @@
+VHDL/lib/CPUs/MIPS/bsp/examples/dbg.c
+
+VHDL/lib/CPUs/MIPS/bsp/examples/irq.c
+
+VHDL/lib/CPUs/MIPS/bsp/examples/irq.h
+
+VHDL/lib/CPUs/MIPS/bsp/examples/kernel.S
+
+VHDL/lib/CPUs/MIPS/bsp/examples/libsys.c
+
+VHDL/lib/CPUs/MIPS/bsp/examples/libsys.h
+
+VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.c
+
+VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.h
+
+VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.c
+
+VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.h
+
+VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.c
+
+VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.h
+
+VHDL/lib/CPUs/MIPS/bsp/examples/regdef.h
+
+VHDL/lib/CPUs/MIPS/bsp/examples/startup.S
+
+VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.c
+
+VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.h
+
+VHDL/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h
+

lib/CPUs/MIPS/bsp/examples/Makefile

@@ -1,7 +1,14 @@
-ENDIAN_FLAGS=-EB
-CFLAGS=$(ENDIAN_FLAGS) -msoft-float -O2 -march=r3000 -I. -Wl,-M
-LIBS=-lc -lm
+ENDIAN='big'
 
+ifeq ($(ENDIAN), 'big')
+  ENDIAN_FLAGS=-EB
+  CFLAGS=$(ENDIAN_FLAGS) -specs=specs/eb/specs -msoft-float -O2 -march=r3000 -I. -Ilibsys -Wl,-M
+else
+  ENDIAN_FLAGS=-EL
+  CFLAGS=$(ENDIAN_FLAGS) -specs=specs/specs -msoft-float -O2 -march=r3000 -I. -Ilibsys -Wl,-M
+endif
+
+LIBS=-lm -lsys
 
 AS=mipsel-elf-as
 AR=mipsel-elf-ar
@@ -11,145 +18,164 @@ OBJDUMP=mipsel-elf-objdump
 OBJCOPY=mipsel-elf-objcopy
 FLASHGEN=flashgen
 
-PROG = hello testbench test_irq dhry queens stanford paranoia rmd160_test Bessel whet phrasen dttl richards_benchmark test_exception life r3 gunzip basic_math jman_patches jman_patchmeshes jman_polys
+PROG = hello.elf testbench.elf test_irq.elf dhry.elf queens.elf stanford.elf paranoia.elf rmd160_test.elf Bessel.elf whet.elf phrasen.elf dttl.elf richards_benchmark.elf test_exception.elf life.elf r3.elf gunzip.elf basic_math.elf jman_patches.elf jman_patchmeshes.elf jman_polys.elf test_hpi.elf test_vga.elf
 
 all: $(PROG)
 
-libsys: startup.S kernel.S libsys.c xcpt.c irq.c
-	$(CC) $(CFLAGS) -G 0 -c startup.S -o startup.o
-	$(CC) $(CFLAGS) -G 0 -c kernel.S -o kernel.o
-	$(CC) $(CFLAGS) -G 0 -DSTDERR_FUNCTION=_ser_putchar -DSTDOUT_FUNCTION=_ser_putchar -D_putchar=_ser_putchar -c libsys.c -o libsys.o
-	$(CC) $(CFLAGS) -G 0 -c xcpt.c -o xcpt.o
-	$(CC) $(CFLAGS) -G 0 -c irq.c -o irq.o
-	$(CC) $(CFLAGS) -G 0 -c dbg.c -o dbg.o
-	$(CC) $(CFLAGS) -G 0 -c mipsdis.c -o mipsdis.o
-	$(AR) -r libsys.a libsys.o xcpt.o irq.o dbg.o mipsdis.o
-	
-hello: hello.c
-	$(CC) $(CFLAGS) -o $@.elf -Os hello.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+libsys.a:
+	$(MAKE) -C libsys
 
-testbench: testbench.c 
-	$(CC) $(CFLAGS) -O3 -o $@.elf -DNOSIGNAL -DBATCHMODE -DNOMAIN -Os -g testbench.c paranoia.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+hello.elf: hello.c libsys.a
+	$(CC) $(CFLAGS) -o $@ -Os hello.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-test_irq: test_irq.c 
-	$(CC) $(CFLAGS) -o $@.elf test_irq.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+testbench.elf: testbench.c  libsys.a
+	$(CC) $(CFLAGS) -O3 -o $@ -DHZ=1000 -DNOSIGNAL -DBATCHMODE -DNOMAIN -Os -g testbench.c paranoia.c delay_mips.c bogomips.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-dhry: dhry_1.c dhry_2.c dhry.h
-	$(CC) $(CFLAGS) -o $@.elf -DHZ=1000 dhry_1.c dhry_2.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+test_irq.elf: test_irq.c libsys.a
+	$(CC) $(CFLAGS) -o $@ test_irq.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-queens: queens.c 
-	$(CC) $(CFLAGS) -o $@.elf -DUNIX_Old -DHZ=1000 queens.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+dhry.elf: dhry_1.c dhry_2.c dhry.h libsys.a
+	$(CC) $(CFLAGS) -o $@ -DHZ=1000 dhry_1.c dhry_2.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-stanford: stanford.c
-	$(CC) $(CFLAGS) -O3 -o $@.elf -DHZ=1000 stanford.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+queens.elf: queens.c libsys.a
+	$(CC) $(CFLAGS) -o $@ -DUNIX_Old -DHZ=1000 queens.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-paranoia: paranoia.c
-	$(CC) $(CFLAGS) -O3 -o $@.elf -DNOSIGNAL -DBATCHMODE paranoia.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+stanford.elf: stanford.c libsys.a
+	$(CC) $(CFLAGS) -O3 -o $@ -DHZ=1000 stanford.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-rmd160_test: rmd160_test.c rmd160.c rmd160.h
-	$(CC) $(CFLAGS) -O2 -o $@.elf -DNOSIGNAL -DBATCHMODE rmd160.c rmd160_test.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+paranoia.elf: paranoia.c libsys.a
+	$(CC) $(CFLAGS) -O3 -o $@ -DNOSIGNAL -DBATCHMODE paranoia.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-Bessel: Bessel.c 
-	$(CC) $(CFLAGS) -o $@.elf Bessel.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+rmd160_test.elf: rmd160_test.c rmd160.c rmd160.h libsys.a
+	$(CC) $(CFLAGS) -O3 -o $@ rmd160_test.c rmd160.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-whet: whet.c 
-	$(CC) $(CFLAGS) -o $@.elf whet.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+hashtest.elf: hashtest.c rmd160.c rmd160.h libsys.a
+	$(CC) $(CFLAGS) -O3 -o $@ hashtest.c rmd160.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-phrasen: phrasen.c 
-	$(CC) $(CFLAGS) -o $@.elf phrasen.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+Bessel.elf: Bessel.c libsys.a
+	$(CC) $(CFLAGS) -o $@ Bessel.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-dttl: dttl.c random.c
-	$(CC) $(CFLAGS) -o $@.elf dttl.c random.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+whet.elf: whet.c libsys.a
+	$(CC) $(CFLAGS) -o $@ whet.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-richards_benchmark: richards_benchmark.c 
-	$(CC) $(CFLAGS) -o $@.elf richards_benchmark.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+phrasen.elf: phrasen.c libsys.a
+	$(CC) $(CFLAGS) -o $@ phrasen.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-test_exception: test_exception.c 
-	$(CC) $(CFLAGS) -o $@.elf -O1 test_exception.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+dttl.elf: dttl.c random.c libsys.a
+	$(CC) $(CFLAGS) -o $@ dttl.c random.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-life: life.c 
-	$(CC) $(CFLAGS) -o $@.elf -g life.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+richards_benchmark.elf: richards_benchmark.c libsys.a
+	$(CC) $(CFLAGS) -o $@ richards_benchmark.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-r3: r3.c 
-	$(CC) $(CFLAGS) -O3 -o $@.elf -DJMIPS_VGA -O2 r3.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+test_exception.elf: test_exception.c libsys.a
+	$(CC) $(CFLAGS) -o $@ -O1 test_exception.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-gunzip: gunzip.c inflate.c crc32.c
-	$(CC) $(CFLAGS) -o $@.elf -o $@.elf gunzip.c inflate.c crc32.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+life.elf: life.c libsys.a
+	$(CC) $(CFLAGS) -o $@ -g life.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-basic_math: basicmath_small.c   rad2deg.c  cubic.c   isqrt.c
-	$(CC) $(CFLAGS) -o $@.elf -o $@.elf basicmath_small.c rad2deg.c cubic.c isqrt.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+r3.elf: r3.c libsys.a
+	$(CC) $(CFLAGS) -O3 -o $@ -DJMIPS_VGA -O2 r3.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+gunzip.elf: gunzip.c inflate.c crc32.c libsys.a
+	$(CC) $(CFLAGS) -o $@ -o $@ gunzip.c inflate.c crc32.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+basic_math.elf: basicmath_small.c   rad2deg.c  cubic.c   isqrt.c libsys.a
+	$(CC) $(CFLAGS) -o $@ -o $@ basicmath_small.c rad2deg.c cubic.c isqrt.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
 JMAN_SRC= \
 	jman/bintree.c \
@@ -167,34 +193,141 @@ JMAN_SRC= \
 	jman/stack.c \
 	jman/vars.c
 
-jman_patches:	$(JMAN_SRC) jman/main_patches.c
-	$(CC) $(CFLAGS) -I../ -o $@.elf -o $@.elf jman/main_patches.c $(JMAN_SRC) $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+jman_patches.elf:	$(JMAN_SRC) jman/main_patches.c libsys.a
+	$(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_patches.c $(JMAN_SRC) $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-jman_patchmeshes:	$(JMAN_SRC) jman/main_patchmeshes.c jman/patches2.c
-	$(CC) $(CFLAGS) -I../ -o $@.elf -o $@.elf jman/main_patchmeshes.c jman/patches2.c $(JMAN_SRC) $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+jman_patchmeshes.elf:	$(JMAN_SRC) jman/main_patchmeshes.c jman/patches2.c libsys.a
+	$(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_patchmeshes.c jman/patches2.c $(JMAN_SRC) $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-jman_polys:	$(JMAN_SRC) jman/main_polypin.c jman/polys.c 
-	$(CC) $(CFLAGS) -I../ -o $@.elf -o $@.elf jman/main_polypin.c jman/polys.c $(JMAN_SRC) $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+jman_polys.elf:	$(JMAN_SRC) jman/main_polypin.c jman/polys.c  libsys.a
+	$(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_polypin.c jman/polys.c $(JMAN_SRC) $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
-serdump: serdump.c 
-	$(CC) $(CFLAGS) -O3 -o $@.elf -O2 serdump.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@.elf > $@.dis
-	$(OBJCOPY) $@.elf -O binary $@.bin
-	$(OBJCOPY) -O srec $@.elf $@.srec
+serdump.elf: serdump.c  libsys.a
+	$(CC) $(CFLAGS) -O3 -o $@ -O2 serdump.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
 	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
+pppi.elf: pppissue/test1.c pppissue/utils.c pppissue/pppd.h libsys.a
+	$(CC) $(CFLAGS) -O2 -o $@ -O2 pppissue/test1.c pppissue/utils.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+lwl.elf: lwl.c  libsys.a
+	$(CC) $(CFLAGS) -O2 -o $@ lwl.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+ucb.elf: ucb.c  libsys.a
+	$(CC) $(CFLAGS) -O2 -o $@ ucb.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+test_hpi.elf: hpi.c test_hpi.c cfiflash.c libsys.a
+	$(CC) $(CFLAGS) -o $@ -g hpi.c test_hpi.c cfiflash.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin
+	cat $@.srec | packhex > $@.pack
+
+test_vga.elf: test_vga.c libsys.a
+	$(CC) $(CFLAGS) -o $@ test_vga.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+barcode.elf: barcode.c libsys.a
+	$(CC) $(CFLAGS) -o $@ barcode.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+lua.elf: lua_init.c libsys.a
+	$(CC) $(CFLAGS) -I./lua-5.1.4/etc -I./lua-5.1.4/src -o $@ lua_init.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+mandelbrot.elf: mandelbrot.c libsys.a
+	$(CC) $(CFLAGS) -o $@ mandelbrot.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+bogomips.elf: bogomips.c delay_mips.c libsys.a
+	$(CC) $(CFLAGS) -DHZ=1000 -o $@ bogomips.c delay_mips.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+test_asm.elf: test_asm.S libsys.a
+	$(CC) $(CFLAGS) -DHZ=1000 -o $@ test_asm.S $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+test_ac97.elf: test_ac97.c libsys.a
+	$(CC) $(CFLAGS) -o $@ test_ac97.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+test_dcache.elf: test_dcache.c libsys.a
+	$(CC) $(CFLAGS) -O0 -o $@ test_dcache.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
+
+aes256_1.elf: aes256_1.c aes256.c aes256.h libsys.a
+	$(CC) $(CFLAGS) -O3 -o $@ aes256_1.c aes256.c $(LIBS) >$@.map
+	$(OBJDUMP) -d $@ > $@.dis
+	$(OBJCOPY) $@ -O binary $@.bin
+	$(OBJCOPY) -O srec $@ $@.srec
+	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
+	cat $@.srec | packhex > $@.pack
 
 clean:
-	rm -rf *.a *.o *.bin *.map *.dis *.srec *.elf $(PROG) > /dev/null
+	rm -rf *.a *.o *.bin *.map *.dis *.srec *.pack *.elf $(PROG) > /dev/null

lib/CPUs/MIPS/bsp/examples/aes256.c

@@ -0,0 +1,359 @@
+/*
+*   Byte-oriented AES-256 implementation.
+*   All lookup tables replaced with 'on the fly' calculations.
+*
+*   Copyright (c) 2007-2009 Ilya O. Levin, http://www.literatecode.com
+*   Other contributors: Hal Finney
+*
+*   Permission to use, copy, modify, and distribute this software for any
+*   purpose with or without fee is hereby granted, provided that the above
+*   copyright notice and this permission notice appear in all copies.
+*
+*   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+*   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+*   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+*   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+*   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+*   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+*   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+#include "aes256.h"
+
+#define F(x)   (((x)<<1) ^ ((((x)>>7) & 1) * 0x1b))
+#define FD(x)  (((x) >> 1) ^ (((x) & 1) ? 0x8d : 0))
+
+#define BACK_TO_TABLES
+#ifdef BACK_TO_TABLES
+
+const uint8_t sbox[256] = {
+    0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
+    0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
+    0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
+    0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
+    0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
+    0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+    0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
+    0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
+    0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
+    0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
+    0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
+    0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+    0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
+    0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
+    0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
+    0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
+    0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
+    0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+    0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
+    0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
+    0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
+    0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
+    0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
+    0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+    0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
+    0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
+    0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
+    0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
+    0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
+    0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+    0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
+    0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+};
+const uint8_t sboxinv[256] = {
+    0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38,
+    0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
+    0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87,
+    0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
+    0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d,
+    0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
+    0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2,
+    0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
+    0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16,
+    0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
+    0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda,
+    0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
+    0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a,
+    0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
+    0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02,
+    0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
+    0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea,
+    0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
+    0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85,
+    0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
+    0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89,
+    0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
+    0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20,
+    0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
+    0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31,
+    0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
+    0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d,
+    0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
+    0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0,
+    0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
+    0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26,
+    0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+};
+
+#define rj_sbox(x)     sbox[(x)]
+#define rj_sbox_inv(x) sboxinv[(x)]
+
+#else /* tableless subroutines */
+
+/* -------------------------------------------------------------------------- */
+uint8_t gf_alog(uint8_t x) // calculate anti-logarithm gen 3
+{
+    uint8_t atb = 1, z;
+
+    while (x--) {z = atb; atb <<= 1; if (z & 0x80) atb^= 0x1b; atb ^= z;}
+
+    return atb;
+} /* gf_alog */
+
+/* -------------------------------------------------------------------------- */
+uint8_t gf_log(uint8_t x) // calculate logarithm gen 3
+{
+    uint8_t atb = 1, i = 0, z;
+
+    do {
+        if (atb == x) break;
+        z = atb; atb <<= 1; if (z & 0x80) atb^= 0x1b; atb ^= z;
+    } while (++i > 0);
+
+    return i;
+} /* gf_log */
+
+
+/* -------------------------------------------------------------------------- */
+uint8_t gf_mulinv(uint8_t x) // calculate multiplicative inverse
+{
+    return (x) ? gf_alog(255 - gf_log(x)) : 0;
+} /* gf_mulinv */
+
+/* -------------------------------------------------------------------------- */
+uint8_t rj_sbox(uint8_t x)
+{
+    uint8_t y, sb;
+
+    sb = y = gf_mulinv(x);
+    y = (y<<1)|(y>>7); sb ^= y;  y = (y<<1)|(y>>7); sb ^= y;
+    y = (y<<1)|(y>>7); sb ^= y;  y = (y<<1)|(y>>7); sb ^= y;
+
+    return (sb ^ 0x63);
+} /* rj_sbox */
+
+/* -------------------------------------------------------------------------- */
+uint8_t rj_sbox_inv(uint8_t x)
+{
+    uint8_t y, sb;
+
+    y = x ^ 0x63;
+    sb = y = (y<<1)|(y>>7);
+    y = (y<<2)|(y>>6); sb ^= y; y = (y<<3)|(y>>5); sb ^= y;
+
+    return gf_mulinv(sb);
+} /* rj_sbox_inv */
+
+#endif
+
+/* -------------------------------------------------------------------------- */
+uint8_t rj_xtime(uint8_t x)
+{
+    return (x & 0x80) ? ((x << 1) ^ 0x1b) : (x << 1);
+} /* rj_xtime */
+
+/* -------------------------------------------------------------------------- */
+void aes_subBytes(uint8_t *buf)
+{
+    register uint8_t i = 16;
+
+    while (i--) buf[i] = rj_sbox(buf[i]);
+} /* aes_subBytes */
+
+/* -------------------------------------------------------------------------- */
+void aes_subBytes_inv(uint8_t *buf)
+{
+    register uint8_t i = 16;
+
+    while (i--) buf[i] = rj_sbox_inv(buf[i]);
+} /* aes_subBytes_inv */
+
+/* -------------------------------------------------------------------------- */
+void aes_addRoundKey(uint8_t *buf, uint8_t *key)
+{
+    register uint8_t i = 16;
+
+    while (i--) buf[i] ^= key[i];
+} /* aes_addRoundKey */
+
+/* -------------------------------------------------------------------------- */
+void aes_addRoundKey_cpy(uint8_t *buf, uint8_t *key, uint8_t *cpk)
+{
+    register uint8_t i = 16;
+
+    while (i--)  buf[i] ^= (cpk[i] = key[i]), cpk[16+i] = key[16 + i];
+} /* aes_addRoundKey_cpy */
+
+
+/* -------------------------------------------------------------------------- */
+void aes_shiftRows(uint8_t *buf)
+{
+    register uint8_t i, j; /* to make it potentially parallelable :) */
+
+    i = buf[1]; buf[1] = buf[5]; buf[5] = buf[9]; buf[9] = buf[13]; buf[13] = i;
+    i = buf[10]; buf[10] = buf[2]; buf[2] = i;
+    j = buf[3]; buf[3] = buf[15]; buf[15] = buf[11]; buf[11] = buf[7]; buf[7] = j;
+    j = buf[14]; buf[14] = buf[6]; buf[6]  = j;
+
+} /* aes_shiftRows */
+
+/* -------------------------------------------------------------------------- */
+void aes_shiftRows_inv(uint8_t *buf)
+{
+    register uint8_t i, j; /* same as above :) */
+
+    i = buf[1]; buf[1] = buf[13]; buf[13] = buf[9]; buf[9] = buf[5]; buf[5] = i;
+    i = buf[2]; buf[2] = buf[10]; buf[10] = i;
+    j = buf[3]; buf[3] = buf[7]; buf[7] = buf[11]; buf[11] = buf[15]; buf[15] = j;
+    j = buf[6]; buf[6] = buf[14]; buf[14] = j;
+
+} /* aes_shiftRows_inv */
+
+/* -------------------------------------------------------------------------- */
+void aes_mixColumns(uint8_t *buf)
+{
+    register uint8_t i, a, b, c, d, e;
+
+    for (i = 0; i < 16; i += 4)
+    {
+        a = buf[i]; b = buf[i + 1]; c = buf[i + 2]; d = buf[i + 3];
+        e = a ^ b ^ c ^ d;
+        buf[i] ^= e ^ rj_xtime(a^b);   buf[i+1] ^= e ^ rj_xtime(b^c);
+        buf[i+2] ^= e ^ rj_xtime(c^d); buf[i+3] ^= e ^ rj_xtime(d^a);
+    }
+} /* aes_mixColumns */
+
+/* -------------------------------------------------------------------------- */
+void aes_mixColumns_inv(uint8_t *buf)
+{
+    register uint8_t i, a, b, c, d, e, x, y, z;
+
+    for (i = 0; i < 16; i += 4)
+    {
+        a = buf[i]; b = buf[i + 1]; c = buf[i + 2]; d = buf[i + 3];
+        e = a ^ b ^ c ^ d;
+        z = rj_xtime(e);
+        x = e ^ rj_xtime(rj_xtime(z^a^c));  y = e ^ rj_xtime(rj_xtime(z^b^d));
+        buf[i] ^= x ^ rj_xtime(a^b);   buf[i+1] ^= y ^ rj_xtime(b^c);
+        buf[i+2] ^= x ^ rj_xtime(c^d); buf[i+3] ^= y ^ rj_xtime(d^a);
+    }
+} /* aes_mixColumns_inv */
+
+/* -------------------------------------------------------------------------- */
+void aes_expandEncKey(uint8_t *k, uint8_t *rc)
+{
+    register uint8_t i;
+
+    k[0] ^= rj_sbox(k[29]) ^ (*rc);
+    k[1] ^= rj_sbox(k[30]);
+    k[2] ^= rj_sbox(k[31]);
+    k[3] ^= rj_sbox(k[28]);
+    *rc = F( *rc);
+
+    for(i = 4; i < 16; i += 4)  k[i] ^= k[i-4],   k[i+1] ^= k[i-3],
+        k[i+2] ^= k[i-2], k[i+3] ^= k[i-1];
+    k[16] ^= rj_sbox(k[12]);
+    k[17] ^= rj_sbox(k[13]);
+    k[18] ^= rj_sbox(k[14]);
+    k[19] ^= rj_sbox(k[15]);
+
+    for(i = 20; i < 32; i += 4) k[i] ^= k[i-4],   k[i+1] ^= k[i-3],
+        k[i+2] ^= k[i-2], k[i+3] ^= k[i-1];
+
+} /* aes_expandEncKey */
+
+/* -------------------------------------------------------------------------- */
+void aes_expandDecKey(uint8_t *k, uint8_t *rc)
+{
+    uint8_t i;
+
+    for(i = 28; i > 16; i -= 4) k[i+0] ^= k[i-4], k[i+1] ^= k[i-3],
+        k[i+2] ^= k[i-2], k[i+3] ^= k[i-1];
+
+    k[16] ^= rj_sbox(k[12]);
+    k[17] ^= rj_sbox(k[13]);
+    k[18] ^= rj_sbox(k[14]);
+    k[19] ^= rj_sbox(k[15]);
+
+    for(i = 12; i > 0; i -= 4)  k[i+0] ^= k[i-4], k[i+1] ^= k[i-3],
+        k[i+2] ^= k[i-2], k[i+3] ^= k[i-1];
+
+    *rc = FD(*rc);
+    k[0] ^= rj_sbox(k[29]) ^ (*rc);
+    k[1] ^= rj_sbox(k[30]);
+    k[2] ^= rj_sbox(k[31]);
+    k[3] ^= rj_sbox(k[28]);
+} /* aes_expandDecKey */
+
+
+/* -------------------------------------------------------------------------- */
+void aes256_init(aes256_context *ctx, uint8_t *k)
+{
+    uint8_t rcon = 1;
+    register uint8_t i;
+
+    for (i = 0; i < sizeof(ctx->key); i++) ctx->enckey[i] = ctx->deckey[i] = k[i];
+    for (i = 8;--i;) aes_expandEncKey(ctx->deckey, &rcon);
+} /* aes256_init */
+
+/* -------------------------------------------------------------------------- */
+void aes256_done(aes256_context *ctx)
+{
+    register uint8_t i;
+
+    for (i = 0; i < sizeof(ctx->key); i++)
+        ctx->key[i] = ctx->enckey[i] = ctx->deckey[i] = 0;
+} /* aes256_done */
+
+/* -------------------------------------------------------------------------- */
+void aes256_encrypt_ecb(aes256_context *ctx, uint8_t *buf)
+{
+    uint8_t i, rcon;
+
+    aes_addRoundKey_cpy(buf, ctx->enckey, ctx->key);
+    for(i = 1, rcon = 1; i < 14; ++i)
+    {
+        aes_subBytes(buf);
+        aes_shiftRows(buf);
+        aes_mixColumns(buf);
+        if( i & 1 ) aes_addRoundKey( buf, &ctx->key[16]);
+        else aes_expandEncKey(ctx->key, &rcon), aes_addRoundKey(buf, ctx->key);
+    }
+    aes_subBytes(buf);
+    aes_shiftRows(buf);
+    aes_expandEncKey(ctx->key, &rcon);
+    aes_addRoundKey(buf, ctx->key);
+} /* aes256_encrypt */
+
+/* -------------------------------------------------------------------------- */
+void aes256_decrypt_ecb(aes256_context *ctx, uint8_t *buf)
+{
+    uint8_t i, rcon;
+
+    aes_addRoundKey_cpy(buf, ctx->deckey, ctx->key);
+    aes_shiftRows_inv(buf);
+    aes_subBytes_inv(buf);
+
+    for (i = 14, rcon = 0x80; --i;)
+    {
+        if( ( i & 1 ) )
+        {
+            aes_expandDecKey(ctx->key, &rcon);
+            aes_addRoundKey(buf, &ctx->key[16]);
+        }
+        else aes_addRoundKey(buf, ctx->key);
+        aes_mixColumns_inv(buf);
+        aes_shiftRows_inv(buf);
+        aes_subBytes_inv(buf);
+    }
+    aes_addRoundKey( buf, ctx->key);
+} /* aes256_decrypt */

lib/CPUs/MIPS/bsp/examples/aes256.h

@@ -0,0 +1,42 @@
+/*  
+*   Byte-oriented AES-256 implementation.
+*   All lookup tables replaced with 'on the fly' calculations. 
+*
+*   Copyright (c) 2007-2009 Ilya O. Levin, http://www.literatecode.com
+*   Other contributors: Hal Finney
+*
+*   Permission to use, copy, modify, and distribute this software for any
+*   purpose with or without fee is hereby granted, provided that the above
+*   copyright notice and this permission notice appear in all copies.
+*
+*   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+*   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+*   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+*   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+*   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+*   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+*   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+#ifndef uint8_t
+#define uint8_t  unsigned char
+#endif
+
+#ifdef __cplusplus
+extern "C" { 
+#endif
+
+    typedef struct {
+        uint8_t key[32]; 
+        uint8_t enckey[32]; 
+        uint8_t deckey[32];
+    } aes256_context; 
+
+
+    void aes256_init(aes256_context *, uint8_t * /* key */);
+    void aes256_done(aes256_context *);
+    void aes256_encrypt_ecb(aes256_context *, uint8_t * /* plaintext */);
+    void aes256_decrypt_ecb(aes256_context *, uint8_t * /* cipertext */);
+
+#ifdef __cplusplus
+}
+#endif

lib/CPUs/MIPS/bsp/examples/aes256_1.c

@@ -0,0 +1,76 @@
+/*
+*   Byte-oriented AES-256 implementation.
+*   All lookup tables replaced with 'on the fly' calculations.
+*
+*   Copyright (c) 2007 Ilya O. Levin, http://www.literatecode.com
+*
+*   Permission to use, copy, modify, and distribute this software for any
+*   purpose with or without fee is hereby granted, provided that the above
+*   copyright notice and this permission notice appear in all copies.
+*
+*   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+*   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+*   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+*   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+*   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+*   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+*   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+#include <stdlib.h>
+#include <stdio.h>
+#include <time.h>
+#include <sys/times.h>
+#include <sys/time.h>
+#include "aes256.h"
+
+#ifndef NUM_BLOCKS
+#define	NUM_BLOCKS	10000
+#endif
+
+#define DUMP(s, i, buf, sz)  {printf(s);                   \
+                              for (i = 0; i < (sz);i++)    \
+                                  printf("%02x ", buf[i]); \
+                              printf("\n");}
+
+
+int main (int argc, char *argv[])
+{
+    aes256_context ctx;
+    uint8_t key[32];
+    uint8_t buf[16], i;
+	long start, end, j;
+
+    /* put a test vector */
+    for (i = 0; i < sizeof(buf);i++) buf[i] = i * 16 + i;
+    for (i = 0; i < sizeof(key);i++) key[i] = i;
+
+    DUMP("txt: ", i, buf, sizeof(buf));
+    DUMP("key: ", i, key, sizeof(key));
+    printf("---\n");
+
+    aes256_init(&ctx, key);
+	start = clock();
+	for (j=0; j < NUM_BLOCKS; j++)
+	{
+	    aes256_encrypt_ecb(&ctx, buf);
+  	}
+	end = clock();
+    DUMP("enc: ", i, buf, sizeof(buf));
+
+	printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC));
+
+    aes256_init(&ctx, key);
+	start = clock();
+	for (j=0; j < NUM_BLOCKS; j++)
+	{
+	    aes256_decrypt_ecb(&ctx, buf);
+  	}
+	end = clock();
+    DUMP("dec: ", i, buf, sizeof(buf));
+
+	printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC));
+
+    aes256_done(&ctx);
+
+    return 0;
+} /* main */

lib/CPUs/MIPS/bsp/examples/barcode.c

@@ -0,0 +1,358 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+#include <time.h>
+#include <sys/times.h>
+#include <sys/time.h>
+
+#define	CPU_FREQ_HZ	100000000
+#include "libsys.h"
+#include "irq.h"
+
+UINT32 buffer[16384];
+
+#define	T_SAMPLE		5000
+#define	TIMEOUT			1000
+
+typedef struct _bar_t
+{
+	UINT32 T;
+	UINT32 black;
+} bar_t;
+
+enum
+{
+	state_idle = 0,
+	state_sample,
+	state_finish
+};
+
+typedef struct _sbar_cand_t
+{
+	UINT32 T;
+	UINT32 is_primitive;
+} bar_cand_t;
+
+bar_t bars[1024];
+
+void bsort(float *pData, UINT32 len)
+{
+	float t;
+	int i, j;
+
+	for(i=len-1; i>=0; i--)
+	{
+		for(j=1; j<len; j++)
+		{
+			if (pData[j-1] > pData[j])
+			{
+				t = pData[j-1];
+				pData[j-1] = pData[j];
+				pData[j] = t;
+			}
+		}
+	}
+}
+
+typedef struct _smedian_t
+{
+	UINT32 N;
+	UINT32 is_dirty;
+	float *pBuf, *pSorted;
+	UINT32 w;
+	float median;
+} median_t;
+
+void Median_init(median_t *pObj, UINT32 N, float init_val)
+{
+	int i;
+	pObj->pBuf = (float*)malloc(N*sizeof(float));
+	pObj->pSorted = (float*)malloc(N*sizeof(float));
+	for (i=0; i < N; i++)
+		pObj->pBuf[0] = init_val;
+	pObj->median = init_val;
+	pObj->is_dirty = 0;
+	pObj->w = 0;
+	pObj->N = N;
+}
+
+void Median_free(median_t *pObj)
+{
+	if (pObj->pBuf)
+		free(pObj->pBuf);
+
+	if (pObj->pSorted)
+		free(pObj->pSorted);
+
+	pObj->pBuf = NULL;
+	pObj->pSorted = NULL;
+
+}
+
+void Median_value_add(median_t *pObj, float value)
+{
+	pObj->is_dirty = 1;
+	pObj->pBuf[pObj->w++] = value;
+
+	if (pObj->w == pObj->N)
+		pObj->w = 0;
+
+}
+
+float Median_get(median_t *pObj)
+{
+	if (!pObj->is_dirty)
+		return pObj->median;
+
+	memcpy(pObj->pSorted, pObj->pBuf, pObj->N*sizeof(float));
+
+	bsort(pObj->pSorted, pObj->N);
+
+	if (pObj->N&1)
+	{
+		pObj->median = pObj->pSorted[(pObj->N-1)/2];
+	}
+	else
+	{
+		pObj->median = 0.5f*(pObj->pSorted[pObj->N/2] + pObj->pSorted[pObj->N/2+1]);
+	}
+
+	pObj->is_dirty = 0;
+
+	return pObj->median;
+}
+
+// -------------------------------------------------------------
+UINT32 detect_module(UINT32 T, UINT32 T0)
+{
+	UINT32 m, best_M;
+	float err, kc, best_err;
+
+	best_err = 4.f;
+	best_M = 0;
+
+	for (m=1; m < 5; m++)
+	{
+		kc = (float)T/(m*T0);
+		err = fabs(kc - 1);
+
+		if (err < best_err)
+		{
+			best_M = m;
+			best_err = err;
+		}
+	}
+
+	return best_M;
+}
+
+void handler7(void)
+{
+	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
+	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
+	UINT32 volatile *pPS20_stat = (UINT32*)SYS_PS2_0_STAT;
+	UINT32 volatile *pPS21_stat = (UINT32*)SYS_PS2_1_STAT;
+	static UINT32 state, bar_count;
+	static UINT32 timeout_count, timeout_reload;
+	static UINT32 white, pin_last, skip, start;
+	static UINT32 module_cnt_w, module_cnt_b, Tmod0_w, Tmod0_b, M, T0;
+	float ratio, error, kc;
+	UINT32 i;
+	static median_t med_b, med_w;
+	static bar_cand_t bc_b, bc_w;
+	static median_t speed_b, speed_w;
+
+	if (*pTim_stat & 1)
+	{
+		*pTim_stat = 1;
+		white = ((*pPS20_stat & SYS_PS2_BIT_PIN_DATA) == 0);
+
+		switch (state)
+		{
+			case state_idle:
+			timeout_reload = TIMEOUT;
+			if (white != pin_last)
+			{
+				if (white)
+					break;
+
+				state = state_sample;
+				module_cnt_b = 0;
+				module_cnt_w = 0;
+				Tmod0_w	= 0xFFFFFFFF;
+				Tmod0_b	= 0xFFFFFFFF;
+				bar_count = 0;
+				Median_init(&med_b, 3, 0);
+				Median_init(&med_w, 3, 0);
+				Median_init(&speed_b, 3, 1);
+				Median_init(&speed_w, 3, 1);
+			}
+			break;
+
+			case state_sample:
+			if (!timeout_count)
+			{
+				state = state_finish;
+				break;
+			}
+
+			if (white)
+			{
+				module_cnt_w++;
+			}
+			else
+			{
+				module_cnt_b++;
+			}
+			if (white != pin_last)
+			{
+				if (pin_last)
+				{
+					if (bar_count < 10)
+					{
+						if (1.5*module_cnt_w < Tmod0_w)
+						{
+							Tmod0_w = module_cnt_w;
+						}
+					}
+					Median_value_add(&med_w, Tmod0_w);
+
+					timeout_reload = 10*Tmod0_w;
+					bars[bar_count].T = module_cnt_w;
+					bars[bar_count].black = 0;
+					module_cnt_w = 0;
+
+				}
+				else
+				{
+					if (bar_count < 10)
+					{
+						if (1.5*module_cnt_b < Tmod0_b)
+						{
+							Tmod0_b = module_cnt_b;
+						}
+					}
+					Median_value_add(&med_b, Tmod0_b);
+
+					timeout_reload = 10*Tmod0_b;
+					bars[bar_count].T = module_cnt_b;
+					bars[bar_count].black = 1;
+					module_cnt_b = 0;
+				}
+				bar_count++;
+
+			}
+			break;
+
+			case state_finish:
+			printf("------------------------------------------------\n");
+			printf("          Black                    White        \n");
+			skip = 0;
+			start = 1;
+			Tmod0_w = Median_get(&med_w);
+			Tmod0_b = Median_get(&med_b);
+			for (i=0; i < bar_count; i++)
+			{
+				if (bars[i].black)
+				{
+					T0 = Median_get(&med_b);
+					ratio = (float)bars[i].T/T0;
+					if (start)
+					{
+						if (ratio > 4)
+						{
+							skip = 1;
+							continue;
+						}
+					}
+					start = 0;
+					skip = 0;
+					M = detect_module(bars[i].T, T0);
+					kc = (float)bars[i].T/(M*T0);
+					error = kc - 1;
+
+//					printf("M=%d, R=%2.2f, E=%+2.2f [%04d]", M, ratio, error, T0);
+//					if (M == 1)
+					Median_value_add(&med_b, (UINT32)(T0*kc));
+					Median_value_add(&speed_b, (float)bars[i].T/(M*Tmod0_b));
+
+					printf("%06d %2.6f ", bars[i].T, Median_get(&speed_b));
+
+				}
+				else
+				{
+					if (skip)
+						continue;
+
+					T0 = Median_get(&med_w);
+					ratio = (float)bars[i].T/T0;
+					if (ratio > 9)
+					{
+						start = 1;
+//						printf("\n");
+//						printf("------------------------------------------------\n");
+//						printf("          Black                    White        \n");
+						continue;
+					}
+
+
+					M = detect_module(bars[i].T, T0);
+					kc = (float)bars[i].T/(M*T0);
+					error = kc - 1;
+
+//					printf("          M=%d, R=%2.2f, E=%+2.2f [%04d]", M, ratio, error, T0);
+//					if (M == 1)
+					Median_value_add(&med_w, (UINT32)(T0*kc));
+					Median_value_add(&speed_w, (float)bars[i].T/(M*Tmod0_w));
+
+					printf("%06d %2.6f ", bars[i].T, Median_get(&speed_w));
+					printf("\n");
+				}
+			}
+			Median_free(&med_b);
+			Median_free(&med_w);
+			Median_free(&speed_b);
+			Median_free(&speed_w);
+			if (bar_count)
+				printf("\n");
+
+			state = state_idle;
+			break;
+
+		}
+		if (white != pin_last)
+			timeout_count = timeout_reload;
+
+		pin_last = white;
+		if (timeout_count)
+			timeout_count--;
+
+	}
+}
+
+int main(void)
+{
+
+	int i;
+	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
+	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
+	UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT;
+	UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP;
+
+	*pTim0_cnt = 0;
+	*pTim0_cmp = (UINT32)T_SAMPLE;
+	*pTim_stat = 1;
+	*pTim_ctrl = 3;
+
+	interrupt_register(7, (void*)handler7);
+
+	printf("Jenners BarCoder\n");
+
+	interrupt_enable(7);
+
+	while(1)
+	{
+	}
+	return 0;
+}

lib/CPUs/MIPS/bsp/examples/barcode.new.c

@@ -0,0 +1,322 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+#include <time.h>
+#include <sys/times.h>
+#include <sys/time.h>
+
+#define	CPU_FREQ_HZ	100000000
+#include "libsys.h"
+#include "irq.h"
+
+UINT32 buffer[16384];
+
+#define	T_SAMPLE		5000
+#define	TIMEOUT			1000
+
+typedef struct _bar_t
+{
+	UINT32 T;
+	UINT32 black;
+} bar_t;
+
+enum
+{
+	state_idle = 0,
+	state_sample,
+	state_finish
+};
+
+bar_t bars[1024];
+
+void bsort(float *pData, UINT32 len)
+{
+	float t;
+	int i, j;
+
+	for(i=len-1; i>=0; i--)
+	{
+		for(j=1; j<len; j++)
+		{
+			if (pData[j-1] > pData[j])
+			{
+				t = pData[j-1];
+				pData[j-1] = pData[j];
+				pData[j] = t;
+			}
+		}
+	}
+}
+
+typedef struct _smedian_t
+{
+	UINT32 N;
+	UINT32 is_dirty;
+	float *pBuf, *pSorted;
+	UINT32 w;
+	float median;
+} median_t;
+
+void Median_init(median_t *pObj, UINT32 N, float init_val)
+{
+	int i;
+	pObj->pBuf = (float*)malloc(N*sizeof(float));
+	pObj->pSorted = (float*)malloc(N*sizeof(float));
+	for (i=0; i < N; i++)
+		pObj->pBuf[0] = init_val;
+	pObj->median = init_val;
+	pObj->is_dirty = 0;
+	pObj->w = 0;
+	pObj->N = N;
+}
+
+void Median_free(median_t *pObj)
+{
+	if (pObj->pBuf)
+		free(pObj->pBuf);
+
+	if (pObj->pSorted)
+		free(pObj->pSorted);
+
+	pObj->pBuf = NULL;
+	pObj->pSorted = NULL;
+
+}
+
+void Median_value_add(median_t *pObj, float value)
+{
+	pObj->is_dirty = 1;
+	pObj->pBuf[pObj->w++] = value;
+
+	if (pObj->w == pObj->N)
+		pObj->w = 0;
+
+}
+
+float Median_get(median_t *pObj)
+{
+	if (!pObj->is_dirty)
+		return pObj->median;
+
+	memcpy(pObj->pSorted, pObj->pBuf, pObj->N*sizeof(float));
+
+	bsort(pObj->pSorted, pObj->N);
+
+	if (pObj->N&1)
+	{
+		pObj->median = pObj->pSorted[(pObj->N-1)/2];
+	}
+	else
+	{
+		pObj->median = 0.5f*(pObj->pSorted[pObj->N/2] + pObj->pSorted[pObj->N/2+1]);
+	}
+
+	pObj->is_dirty = 0;
+
+	return pObj->median;
+}
+
+// -------------------------------------------------------------
+UINT32 detect_module(UINT32 T, UINT32 *pBC)
+{
+	UINT32 m, best_M;
+	float err, kc, best_err;
+
+	best_err = 4.f;
+	best_M = 0;
+
+	for (m=0; m < 4; m++)
+	{
+		kc = (float)T/pBC[m];
+		err = fabs(kc - 1);
+
+		if (err < best_err)
+		{
+			best_M = m+1;
+			best_err = err;
+		}
+	}
+
+	return best_M;
+}
+
+void handler7(void)
+{
+	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
+	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
+	UINT32 volatile *pPS20_stat = (UINT32*)SYS_PS2_0_STAT;
+	UINT32 volatile *pPS21_stat = (UINT32*)SYS_PS2_1_STAT;
+	static UINT32 state, bar_count;
+	static UINT32 timeout_count, timeout_reload;
+	static UINT32 white, pin_last, skip, start;
+	static UINT32 module_cnt_w, module_cnt_b, Tmod0_w, Tmod0_b, M, T0;
+	float ratio, error, kc;
+	UINT32 i, j;
+	static median_t med_b, med_w;
+	static UINT32 bc_b[4], bc_w[4];
+
+	if (*pTim_stat & 1)
+	{
+		*pTim_stat = 1;
+		white = ((*pPS20_stat & SYS_PS2_BIT_PIN_DATA) == 0);
+
+		switch (state)
+		{
+			case state_idle:
+			timeout_reload = TIMEOUT;
+			if (white != pin_last)
+			{
+				if (white)
+					break;
+
+				state = state_sample;
+				module_cnt_b = 0;
+				module_cnt_w = 0;
+				Tmod0_w	= 0xFFFFFFFF;
+				Tmod0_b	= 0xFFFFFFFF;
+				bar_count = 0;
+				Median_init(&med_b, 3, 1);
+				Median_init(&med_w, 3, 1);
+			}
+			break;
+
+			case state_sample:
+			if (!timeout_count)
+			{
+				state = state_finish;
+				break;
+			}
+
+			if (white)
+			{
+				module_cnt_w++;
+			}
+			else
+			{
+				module_cnt_b++;
+			}
+			if (white != pin_last)
+			{
+				if (pin_last)
+				{
+					if (bar_count < 10)
+					{
+						if (1.5*module_cnt_w < Tmod0_w)
+						{
+							Tmod0_w = module_cnt_w;
+						}
+					}
+					timeout_reload = 10*Tmod0_w;
+					bars[bar_count].T = module_cnt_w;
+					bars[bar_count].black = 0;
+					module_cnt_w = 0;
+
+				}
+				else
+				{
+					if (bar_count < 10)
+					{
+						if (1.5*module_cnt_b < Tmod0_b)
+						{
+							Tmod0_b = module_cnt_b;
+						}
+					}
+					timeout_reload = 10*Tmod0_b;
+					bars[bar_count].T = module_cnt_b;
+					bars[bar_count].black = 1;
+					module_cnt_b = 0;
+				}
+				bar_count++;
+
+			}
+			break;
+
+			case state_finish:
+			printf("------------------------------------------------\n");
+			printf("          Black                    White        \n");
+			skip = 0;
+			start = 1;
+			for (i=0; i < 4; i++)
+			{
+				bc_b[i] = (i+1)*Tmod0_b;
+				bc_w[i] = (i+1)*Tmod0_w;
+			}
+			for (i=0; i < bar_count; i++)
+			{
+				if (bars[i].black)
+				{
+					M = detect_module(bars[i].T, bc_b);
+					if (M)
+					{
+						kc = (float)bars[i].T/bc_b[M-1];
+						error = kc - 1;
+						Median_value_add(&med_b, kc);
+						printf("M=%d, R=%2.2f, E=%+2.2f [%04d]", M, kc, error, bc_b[M-1]);
+						kc = Median_get(&med_b);
+						bc_b[M-1] = (UINT32)(kc*bc_b[M-1]);
+					}
+//					printf("%d", M);
+
+				}
+				else
+				{
+					M = detect_module(bars[i].T, bc_w);
+					if (M)
+					{
+						kc = (float)bars[i].T/bc_w[M-1];
+						error = kc - 1;
+						Median_value_add(&med_w, kc);
+						printf("          M=%d, R=%2.2f, E=%+2.2f [%04d]", M, kc, error, bc_w[M-1]);
+						kc = Median_get(&med_w);
+						bc_w[M-1] = (UINT32)(kc*bc_w[M-1]);
+
+					}
+//					printf("%d", M);
+					printf("\n");
+				}
+			}
+			Median_free(&med_b);
+			Median_free(&med_w);
+			if (bar_count)
+				printf("\n");
+
+			state = state_idle;
+			break;
+
+		}
+		if (white != pin_last)
+			timeout_count = timeout_reload;
+
+		pin_last = white;
+		if (timeout_count)
+			timeout_count--;
+
+	}
+}
+
+int main(void)
+{
+
+	int i;
+	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
+	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
+	UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT;
+	UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP;
+
+	*pTim0_cnt = 0;
+	*pTim0_cmp = (UINT32)T_SAMPLE;
+	*pTim_stat = 1;
+	*pTim_ctrl = 3;
+
+	interrupt_register(7, (void*)handler7);
+
+	printf("Jenners BarCoder\n");
+
+	interrupt_enable(7);
+
+	while(1)
+	{
+	}
+	return 0;
+}

lib/CPUs/MIPS/bsp/examples/basicmath_small.c

@@ -0,0 +1,84 @@
+#include "snipmath.h"
+#include <math.h>
+
+/* The printf's may be removed to isolate just the math calculations */
+
+int main(void)
+{
+  double  a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0;
+  double  a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0;
+  double  a3 = 1.0, b3 = -3.5, c3 = 22.0, d3 = -31.0;
+  double  a4 = 1.0, b4 = -13.7, c4 = 1.0, d4 = -35.0;
+  double  x[3];
+  double X;
+  int     solutions;
+  int i;
+  unsigned long l = 0x3fed0169L;
+  struct int_sqrt q;
+  long n = 0;
+
+  /* solve soem cubic functions */
+  printf("********* CUBIC FUNCTIONS ***********\n");
+  /* should get 3 solutions: 2, 6 & 2.5   */
+  SolveCubic(a1, b1, c1, d1, &solutions, x);  
+  printf("Solutions:");
+  for(i=0;i<solutions;i++)
+    printf(" %f",x[i]);
+  printf("\n");
+  /* should get 1 solution: 2.5           */
+  SolveCubic(a2, b2, c2, d2, &solutions, x);  
+  printf("Solutions:");
+  for(i=0;i<solutions;i++)
+    printf(" %f",x[i]);
+  printf("\n");
+  SolveCubic(a3, b3, c3, d3, &solutions, x);
+  printf("Solutions:");
+  for(i=0;i<solutions;i++)
+    printf(" %f",x[i]);
+  printf("\n");
+  SolveCubic(a4, b4, c4, d4, &solutions, x);
+  printf("Solutions:");
+  for(i=0;i<solutions;i++)
+    printf(" %f",x[i]);
+  printf("\n");
+  /* Now solve some random equations */
+  for(a1=1;a1<10;a1++) {
+    for(b1=10;b1>0;b1--) {
+      for(c1=5;c1<15;c1+=0.5) {
+	for(d1=-1;d1>-11;d1--) {
+	  SolveCubic(a1, b1, c1, d1, &solutions, x);  
+	  printf("Solutions:");
+	  for(i=0;i<solutions;i++)
+	    printf(" %f",x[i]);
+	  printf("\n");
+	}
+      }
+    }
+  }
+  
+  printf("********* INTEGER SQR ROOTS ***********\n");
+  /* perform some integer square roots */
+  for (i = 0; i < 1001; ++i)
+    {
+      usqrt(i, &q);
+			// remainder differs on some machines
+     // printf("sqrt(%3d) = %2d, remainder = %2d\n",
+     printf("sqrt(%3d) = %2d\n",
+	     i, q.sqrt);
+    }
+  usqrt(l, &q);
+  //printf("\nsqrt(%lX) = %X, remainder = %X\n", l, q.sqrt, q.frac);
+  printf("\nsqrt(%lX) = %X\n", l, q.sqrt);
+
+
+  printf("********* ANGLE CONVERSION ***********\n");
+  /* convert some rads to degrees */
+  for (X = 0.0; X <= 360.0; X += 1.0)
+    printf("%3.0f degrees = %.12f radians\n", X, deg2rad(X));
+  puts("");
+  for (X = 0.0; X <= (2 * PI + 1e-6); X += (PI / 180))
+    printf("%.12f radians = %3.0f degrees\n", X, rad2deg(X));
+  
+  
+  return 0;
+}

lib/CPUs/MIPS/bsp/examples/bogomips.c

@@ -0,0 +1,71 @@
+/*
+ * bogomips.c -- Program to measure bogomips... this program will probably go
+ * totally wacky with cpufreq enabled.
+ *
+ * Copyright (C) 2005 Darrick Wong.
+ */
+#include <stdio.h>
+#include <time.h>
+
+/* this should be approx 2 Bo*oMips to start (note initial shift), and will
+ *    still work even if initially too large, it will just take slightly longer */
+unsigned long loops_per_jiffy = (1<<12);
+
+/* This is the number of bits of precision for the loops_per_jiffy.  Each
+ *    bit takes on average 1.5/HZ seconds.  This (like the original) is a little
+ *       better than 1% */
+#define LPS_PREC 8
+
+extern void delay(unsigned int loops);
+
+//plagiarized straight from the 2.4 sources.
+#ifdef NOMAIN
+int calibrate_delay(void)
+#else
+int main(void)
+#endif
+{
+        unsigned long ticks, loopbit;
+        int lps_precision = LPS_PREC;
+
+        loops_per_jiffy = (1<<12);
+
+        printf("Calibrating delay loop... ");
+        while (loops_per_jiffy <<= 1) {
+                /* wait for "start of" clock tick */
+                ticks = clock();
+                while (ticks == clock())
+                        /* nothing */;
+                /* Go .. */
+                ticks = clock();
+                delay(loops_per_jiffy);
+                ticks = clock() - ticks;
+                if (ticks)
+                        break;
+        }
+
+/* Do a binary approximation to get loops_per_jiffy set to equal one clock
+   (up to lps_precision bits) */
+
+       loops_per_jiffy >>= 1;
+        loopbit = loops_per_jiffy;
+        while ( lps_precision-- && (loopbit >>= 1) ) {
+                loops_per_jiffy |= loopbit;
+                ticks = clock();
+                while (ticks == clock());
+                ticks = clock();
+                delay(loops_per_jiffy);
+                if (clock() != ticks)   /* longer than 1 tick */
+                        loops_per_jiffy &= ~loopbit;
+        }
+
+
+/* Round the value and print it */
+        printf("%lu.%02lu BogoMIPS\n",
+                loops_per_jiffy/(500000/HZ),
+                (loops_per_jiffy/(5000/HZ)) % 100);
+
+
+		return loops_per_jiffy;
+}
+

lib/CPUs/MIPS/bsp/examples/bootloader/Makefile

@@ -1,47 +0,0 @@
-ENDIAN='big'
-
-ifeq ($(ENDIAN), 'big')
-  ENDIAN_FLAGS=-EB
-  LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib/eb -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER)/eb
-else
-  ENDIAN_FLAGS=-EL
-  LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER)
-endif
-
-CFLAGS=$(ENDIAN_FLAGS) -Os -I. -I../ -msoft-float -march=r3000
-LFLAGS=$(ENDIAN_FLAGS) -M -T bootloader.ld
-
-LIBS=-lc -lgcc
-
-CC=mipsel-elf-gcc
-LD=mipsel-elf-ld
-OBJDUMP=mipsel-elf-objdump
-OBJCOPY=mipsel-elf-objcopy
-
-all: bootloader_flash
-
-libsys: startup_boot.S init_boot.S kernel_boot.S libsys_boot.c
-	$(CC) $(CFLAGS) -c startup_boot.S -o startup.o
-	$(CC) $(CFLAGS) -c init_boot.S -o init.o
-	$(CC) $(CFLAGS) -c kernel_boot.S -o kernel.o
-	$(CC) $(CFLAGS) -c libsys_boot.c -o libsys.o
-
-bootloader: libsys bootloader.c 
-	$(CC) $(CFLAGS) -g -c bootloader.c
-	$(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o bootloader.o -o bootloader.elf $(LIBS) >bootloader.map
-	$(OBJDUMP) -d bootloader.elf > bootloader.dis
-	$(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin
-	$(OBJCOPY) -O srec bootloader.elf bootloader.srec
-	romgen bootloader.ROM.bin 10 $(ENDIAN_FLAGS)
-
-bootloader_flash: libsys bootloader_with_flash.c 
-	$(CC) $(CFLAGS) -g -c bootloader_with_flash.c
-	$(CC) $(CFLAGS) -g -c ../cfiflash.c
-	$(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o cfiflash.o bootloader_with_flash.o -o bootloader.elf $(LIBS) >bootloader.map
-	$(OBJDUMP) -d bootloader.elf > bootloader.dis
-	$(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin
-	$(OBJCOPY) -O srec bootloader.elf bootloader.srec
-	romgen bootloader.ROM.bin 11 $(ENDIAN_FLAGS)
-
-clean:
-	rm -rf *.o *.bin *.map *.dis *.srec *.elf *.vhd* *.tcl bootloader > /dev/null

lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c

@@ -1,247 +0,0 @@
-#include "libsys_boot.h"
-
-typedef struct _ssrec_t
-{
-	UINT32 addr;
-	UINT32 size;
-	UINT32 type;
-	UINT8 *data;
-
-} srec_t;
-
-enum srec_type
-{
-	srec_err, srec_sob, srec_data, srec_rec, srec_eob
-};
-
-UINT8 h2i(UINT8 *c)
-{
-	int i;
-	UINT8 t, b = 0;
-
-	for (i=0; i < 2; i++)
-	{
-		t = c[i];
-		if (t >= 'A')
-			t = t - 'A' + 10;
-		else
-			t -= '0';
-
-		b = (b << 4) | t;
-	}
-	return b;
-}
-
-int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen)
-{
-	UINT8 chksum, byte;
-	int alen, i;
-
-	if (!buflen)
-		return srec_err;
-
-	pRec->type = srec_rec;
-	alen = 0;
-	if ((pBuf[1] > '0') && (pBuf[1] < '4'))
-	{
-	  alen = pBuf[1] - '0' + 1;
-	  pRec->type = srec_data;
-	}
-	else if ((pBuf[1] >= '7') && (pBuf[1] <= '9'))
-	{
-	  alen = 11 - (pBuf[1] - '0');
-	  pRec->type = srec_eob;
-	}
-	else if (pBuf[1] == '0')
-	{
-	  alen = 2;
-	  pRec->type = srec_sob;
-	}
-
-	byte = h2i(&pBuf[2]);
-	pRec->size = byte;
-	chksum = byte;
-
-	pRec->addr = 0;
-	for (i=0; i < alen; i++)
-	{
-		byte = h2i(&pBuf[4+2*i]);
-        pRec->addr = pRec->addr << 8 | byte;
-		chksum += byte;
-	}
-	pRec->size -= (alen+1);
-
-	pRec->data = (UINT8*) &pBuf[4 + 2*alen];
-	for (i=0; i < (int)pRec->size; i++)
-	{
-		byte = h2i(&pRec->data[2*i]);
-		pRec->data[i] = byte;
-		chksum += byte;
-	}
-	chksum = ~chksum;
-	byte = h2i(&pRec->data[2*i]);
-	if (chksum != byte)
-		return 0;
-
-	return pRec->type;
-}
-
-int srec_getline(UINT8 *pLine)
-{
-	char c;
-	int i = 0;
-
-	do
-	{
-		c = readchar();
-
-	} while ((c != 's') && (c != 'S'));
-
-	while(((c != 0x0D) && (c != 0x0A)))
-	{
-		pLine[i++] = c;
-		c = readchar();
-	};
-
-	return i;
-}
-
-void Jump_to(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-	__asm
-	(
-		"jr		%[pEntry]\n"				// jump entry
-		:
-		: [pEntry] "r" (pEntry)
-	);
-	__asm
-	(
-		"nop\n"
-	);
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-
-void Exec_at(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-
-	__asm
-	(
-		"mfc0	$26, $12\n"			// change exception vector
-		"li		$27, 0xFFBFFFFF\n"
-		"and	$26, $27\n"
-		"mtc0	$26, $12\n"
-	);
-
-	__asm
-	(
-		"lw		$v0, 16($sp)\n"
-		"nop\n"
-		"jr		$v0\n"				// jump entry
-		"rfe\n"
-	);
-
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-void PrintCPUinfo(void)
-{
-	int result, rev_id;
-
-	char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"};
-
-	// Print Status register
-	result = CP0_SR_read();
-
-	sputs("Status  : ");
-	print_word(result);
-	sputs("\n");
-
-	// Print Revision
-	result = CP0_PRID_read();
-	rev_id = (result >> 8) & 0xFF;
-	sputs("CPU type: ");
-	if ((rev_id > 0) && (rev_id < 0x07))
-	{
-		sputs(cpu_type_str[rev_id]);
-		sputs(" Rev.");
-		rev_id = result & 0xFF;
-		print_byte((char)rev_id);
-	}
-	else
-		sputs("Unknown");
-
-	sputs("\n");
-
-}
-
-#define	MAX_IMG_SIZE		(1024*1024)	// bytes
-
-int main(int argc, char *argv[])
-{
-	UINT8 buf[256];
-	srec_t srec;
-	int result, srec_state, i;
-	UINT32 haddr;
-	volatile UINT8 *pMem;
-	haddr = 0;
-
-	// ----------------------------------------------------------
-	sputs("\n\n");
-	PrintCPUinfo();
-	sputs("Booting from UART..");
-
-	while(1)
-	{
-		sputs(".");
-		while(1)
-		{
-			result = srec_getline(buf);
-			srec_state = decode_srec(&srec, buf, result);
-			switch (srec_state)
-			{
-				case srec_data:
-					if ((srec.addr + srec.size) > haddr)
-						haddr = srec.addr + srec.size;
-
-					pMem = (UINT8*)srec.addr;
-					for (i=0; i < srec.size; i++)
-						*pMem++ = srec.data[i];
-
-					break;
-
-				case srec_eob:
-					sputs("done\n\n");
-					sputs("Execute program at ");
-					print_word(srec.addr);
-					sputs("\n\n");
-
-					Exec_at((void*)srec.addr);
-					break;
-
-				default:
-					result = -1;
-					break;
-			}
-			if (result < 0)
-			{
-				break;
-			}
-
-		};
-	}
-	return 0;
-}
-

lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld

@@ -1,53 +0,0 @@
-MEMORY
-{
-  rom          : ORIGIN = 0xBFC00000, LENGTH = 0x00002000  /*   8K    */
-  ram          : ORIGIN = 0x40000000, LENGTH = 0x00002000  /*   8K    */
-}
-
-OUTPUT_ARCH(mips)
-SEARCH_DIR(".");
-SEARCH_DIR("/usr/local/mipsel-elf/lib:/usr/local/mipsel-elf/lib/eb");
-SEARCH_DIR("/usr/local/lib/gcc/mipsel-elf/4.3.3:/usr/local/lib/gcc/mipsel-elf/4.3.3/eb");
-
-stack_ptr = 0x7FFFEFF0;
-baudrate = 0x0D;
-sys_led_port = 0xA0000000;
-sys_uart_data = 0xA0010000;
-sys_uart_stat = 0xA0010004;
-sys_uart_baud = 0xA0010008;
-sys_timer_usec = 0xA000008;
-sys_timer_sec = 0xA000000C;
-
-
-SECTIONS
-{
-   .init ORIGIN(rom) :
-   {
-      start = ALIGN(4);
-      entry = ALIGN(4);
-      _entry = ALIGN(4);
-      __entry = ALIGN(4);
-     *(.stext)
-   }  > rom
-   
-   .ktext ORIGIN(rom) + 0x180 :
-   {
-     *(.ktext)
-   }  > rom
-
-   .text . :
-   {
-     *(.text)
-   }  > rom
-
-   .rodata . :
-   {
-     *(.rodata*)
-   }  > rom
-
-   .data ORIGIN(ram) :
-   {
-     *(.*data) *(.*bss) *(.*common)
-   }  > ram
-
-}

lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c

@@ -1,391 +0,0 @@
-#include "libsys_boot.h"
-#include "cfiflash.h"
-
-#define	MAGIC_EB	0x4A464931	// "JFI1" in big-endian;
-#define	MAGIC_EL	0x3149464A	// "JFI1" in little-endian;
-
-typedef struct _ssrec_t
-{
-	UINT32 addr;
-	UINT32 size;
-	UINT32 type;
-	UINT8 *data;
-
-} srec_t;
-typedef struct _sflash_alloc_tbl_t
-{
-	UINT32 images[16];
-
-} flash_alloc_tbl_t;
-
-typedef struct _sflash_img_hdr_t
-{
-	UINT32 magic;
-	UINT32 target_base;
-	UINT32 img_base;
-	UINT32 img_size;
-	UINT32 hdr_next;
-	UINT8 img_name[128];
-	UINT8 res[108];
-
-} flash_img_hdr_t;
-
-enum srec_type
-{
-	srec_err, srec_sob, srec_data, srec_rec, srec_eob
-};
-
-UINT8 h2i(UINT8 *c)
-{
-	int i;
-	UINT8 t, b = 0;
-
-	for (i=0; i < 2; i++)
-	{
-		t = c[i];
-		if (t >= 'A')
-			t = t - 'A' + 10;
-		else
-			t -= '0';
-
-		b = (b << 4) | t;
-	}
-	return b;
-}
-
-int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen)
-{
-	UINT8 chksum, byte;
-	int alen, i;
-
-	if (!buflen)
-		return srec_err;
-
-	pRec->type = srec_rec;
-	alen = 0;
-	if ((pBuf[1] > '0') && (pBuf[1] < '4'))
-	{
-	  alen = pBuf[1] - '0' + 1;
-	  pRec->type = srec_data;
-	}
-	else if ((pBuf[1] >= '7') && (pBuf[1] <= '9'))
-	{
-	  alen = 11 - (pBuf[1] - '0');
-	  pRec->type = srec_eob;
-	}
-	else if (pBuf[1] == '0')
-	{
-	  alen = 2;
-	  pRec->type = srec_sob;
-	}
-
-	byte = h2i(&pBuf[2]);
-	pRec->size = byte;
-	chksum = byte;
-
-	pRec->addr = 0;
-	for (i=0; i < alen; i++)
-	{
-		byte = h2i(&pBuf[4+2*i]);
-        pRec->addr = pRec->addr << 8 | byte;
-		chksum += byte;
-	}
-	pRec->size -= (alen+1);
-
-	pRec->data = (UINT8*) &pBuf[4 + 2*alen];
-	for (i=0; i < (int)pRec->size; i++)
-	{
-		byte = h2i(&pRec->data[2*i]);
-		pRec->data[i] = byte;
-		chksum += byte;
-	}
-	chksum = ~chksum;
-	byte = h2i(&pRec->data[2*i]);
-	if (chksum != byte)
-		return 0;
-
-	return pRec->type;
-}
-
-int srec_getline(UINT8 *pLine)
-{
-	char c;
-	int i = 0;
-
-	do
-	{
-		c = readchar();
-
-	} while ((c != 's') && (c != 'S'));
-
-	while(((c != 0x0D) && (c != 0x0A)))
-	{
-		pLine[i++] = c;
-		c = readchar();
-	};
-
-	return i;
-}
-
-void Jump_to(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-	__asm
-	(
-		"jr		%[pEntry]\n"				// jump entry
-		:
-		: [pEntry] "r" (pEntry)
-	);
-	__asm
-	(
-		"nop\n"
-	);
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-
-void Exec_at(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-
-	__asm
-	(
-		"li		$26, 0x10000000\n"
-		"mtc0	$26, $12\n"
-	);
-
-	__asm
-	(
-		"jr		%[pEntry]\n"				// jump entry
-		:
-		: [pEntry] "r" (pEntry)
-	);
-
-	__asm
-	(
-		"rfe\n"
-	);
-
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-
-void Exec_RE_at(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-
-	__asm
-	(
-		"mfc0	$26, $12\n"			// change exception vector
-		"li		$27, 0xFFBFFFFF\n"
-		"and	$26, $27\n"
-		"li		$27, 0x02000000\n"	// Reverse Endianess
-		"or		$26, $27\n"
-		"mtc0	$26, $12\n"
-	);
-
-	__asm
-	(
-		"jr		%[pEntry]\n"				// jump entry
-		:
-		: [pEntry] "r" (pEntry)
-	);
-
-	__asm
-	(
-		"rfe\n"
-	);
-
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-
-#define	MAX_IMG_SIZE		(1024*1024)	// bytes
-#define SDRAM_BASE			0x40000000
-#define FLASH_USE_BLOCK		1
-
-int main(int argc, char *argv[])
-{
-	UINT8 buf[256];
-	srec_t srec;
-	int srec_state, i;
-	UINT32 haddr, result;
-	flash_t flash;
-	flash_img_hdr_t img_hdr = {0};
-	flash_img_hdr_t *pImg_hdr;
-	UINT32 img_size, block_sel;
-
-	volatile UINT32 *pReg = (UINT32*)sys_led_port;
-	volatile UINT32 *pBtn = (UINT32*)sys_gpio0;
-	volatile UINT32 *pDip = (UINT32*)sys_gpio1;
-	volatile UINT8 *pMem;
-	volatile UINT32 *pROM32;
-	volatile UINT32 *pMem32;
-	volatile UINT32 *pFlashIO = (UINT32*)sys_flash_io;		// Flash in uncached area
-	volatile UINT32 *pFlashMem = (UINT32*)sys_flash_mem;	// Flash in cached area
-	volatile UINT32 *pUSB = (UINT32*)sys_usb_data;
-
-	volatile UINT8 *ram8 = (UINT8*)SDRAM_BASE;
-	volatile UINT16 *ram16 = (UINT16*)SDRAM_BASE;
-	volatile UINT32 *ram32 = (UINT32*)SDRAM_BASE;
-	UINT32 flash_offset;
-
-	*pReg = 0;
-	haddr = 0;
-	block_sel = 0x7F & (UINT32)*pDip;
-
-	// ----------------------------------------------------------
-	if (IS_ERROR(flash_find(&flash, sys_flash_io)))
-	{
-		sputs("Cannot find flash device. Exit now!\n\n");
-		return 1;
-	}
-
-	// Get flash offset by value of DIP-switch
-	flash_offset = flash_get_offset_by_blocknum(&flash, block_sel);
-
-	ram32 = (UINT32*)(SDRAM_BASE);
-	pFlashIO = (UINT32*)(sys_flash_io + flash_offset);
-
-	if (!(*pBtn & 8))
-	{
-		sputs("\n\n");
-		pImg_hdr = (flash_img_hdr_t*)pFlashIO;
-		if ((pImg_hdr->magic != MAGIC_EL) && (pImg_hdr->magic != MAGIC_EB))
-		{
-			sputs("\n\n");
-			sputs("Invalid image found at ");print_word(flash_offset); sputs(". Abort.\n");
-			return 1;
-		}
-
-		sputs("Booting application from flash (");print_word(flash_offset);sputs(")...");
-
-		ram32 = (UINT32*)pImg_hdr->target_base;
-		img_size = pImg_hdr->img_size;
-
-		// It's safe to use cached Flash,
-		// because  D-Cache was invalidated during execution of start code
-//		pFlashIO = (UINT32*)(sys_flash_io + pImg_hdr->img_base);
-		pFlashMem = (UINT32*)(sys_flash_mem + pImg_hdr->img_base);
-
-		for (i=0; i < img_size/4; i++)
-//			ram32[i] = pFlashIO[i];
-			ram32[i] = pFlashMem[i];
-
-		sputs("done\n");
-
-		sputs("Execute at ");print_word(pImg_hdr->target_base); sputs("\n\n");
-		Exec_at((void*)ram32);
-	}
-	else
-	{
-
-		sputs("\n\n");
-
-		sputs("Reading HEX-Record from UART..");
-
-		// Erase SDRAM
-		for (i=0; i < MAX_IMG_SIZE/4; i++)
-			ram32[i] = 0;
-
-
-		while(1)
-		{
-			sputs(".");
-			while(1)
-			{
-				result = srec_getline(buf);
-				srec_state = decode_srec(&srec, buf, result);
-				*pReg = 0;
-				switch (srec_state)
-				{
-					case srec_data:
-						if ((srec.addr + srec.size) > haddr)
-							haddr = srec.addr + srec.size;
-
-						pMem = (UINT8*)srec.addr;
-						for (i=0; i < srec.size; i++)
-							*pMem++ = srec.data[i];
-
-						break;
-
-					case srec_eob:
-						sputs("done\n\n");
-						img_hdr.magic = MAGIC_EB;
-						img_hdr.target_base = srec.addr;
-						img_hdr.img_size = haddr - srec.addr;
-						img_hdr.img_base = flash_offset + sizeof(flash_img_hdr_t);
-						img_hdr.hdr_next = flash_get_offset_blockaligned(&flash, img_hdr.img_base + img_hdr.img_size);
-						sputs("Size of application    : ");print_word(img_hdr.img_size); sputs("\n");
-						sputs("Programming flash at   : ");print_word(flash_offset); sputs("\n");
-						sputs("Next free flash offset : ");print_word(img_hdr.hdr_next); sputs("\n");
-
-						sputs("Flash erase...");
-						result = flash_erase(&flash, flash_offset, img_hdr.img_size + sizeof(flash_img_hdr_t));
-						if (IS_ERROR(result))
-						{
-							sputs("failed (");print_word(result);sputs(")\n");
-							break;
-						}
-						sputs("done\n");
-
-						sputs("Flash write...");
-						result = flash_program(&flash, flash_offset, (UINT8*)&img_hdr, sizeof(flash_img_hdr_t));
-						if (IS_ERROR(result))
-						{
-							sputs("failed (");print_word(result);sputs(")\n");
-							break;
-						}
-						result = flash_program(&flash, img_hdr.img_base, (UINT8*)img_hdr.target_base, img_hdr.img_size);
-						if (IS_ERROR(result))
-						{
-							sputs("failed (");print_word(result);sputs(")\n");
-							break;
-						}
-						sputs("done\n");
-
-						sputs("Flash verify...");
-						result = flash_verify(&flash, img_hdr.img_base, (UINT8*)img_hdr.target_base, img_hdr.img_size);
-						if (IS_ERROR(result))
-						{
-							sputs("failed (");print_word(result);sputs(")\n");
-							break;
-						}
-						sputs("passed\n");
-
-						// Jump to reset vector
-						Jump_to((void*)0xBFC00000);
-
-						break;
-
-					default:
-						result = -1;
-						break;
-				}
-				if (IS_ERROR(result))
-				{
-					*pReg = 0x40000000;
-					break;
-				}
-
-			};
-		}
-	}
-	return 0;
-}
-

lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S

@@ -1,46 +0,0 @@
-		.file	"kernel.S"
-
-		.section .ktext,"ax"
-		.align	2
-
-		.macro kpush reg
-		addiu	$sp, 4
-		sw		\reg, 0($sp)
-		.endm
-		
-		.macro kpop reg
-		lw		\reg, 0($sp)
-		addiu	$sp, -4
-		.endm
-
-_exc_handler:
-
-		.set	noreorder
-		
-		# Set Error LED and ExcCode LEDs
-		# Get Cause
-		mfc0	$26, $13
-		li 		$27, 0xC0000000
-		srl		$26, 2
-		andi	$26, 0x000F
-		or 		$26, $27
-		la 		$27, sys_led_port
-		sw 		$26, 0($27)
-
-		# wait for all interrupts = 0
-$w4x:	mfc0	$26, $13
-		nop
-		srl		$26, 8
-		andi	$26, 0xFF
-		bnez	$26, $w4x
-		nop
-		
-		# Get return address
-		mfc0	$26, $14
-
-		# Return
-		nop
-		jr	$26
-		rfe
-		.set	reorder
-	

lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c

@@ -1,214 +0,0 @@
-#include <sys/times.h>
-#include <sys/time.h>
-#include <sys/resource.h>
-#include <sys/stat.h>
-#include <errno.h>
-#include <stdlib.h>
-#include "libsys_boot.h"
-
-// ---------------------------------------------------------------------------------
-// MIPS specific
-UINT32 CP0_SR_read(void)
-{
-	UINT32 result;
-
-	__asm
-	(
-		"mfc0   %[val], $12\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-void CP0_SR_write(UINT32 val)
-{
-	__asm
-	(
-		"mtc0   %[val], $12\n"
-		: /* no output */
-		: [val] "r" (val)
-	);
-}
-
-UINT32 CP0_CR_read(void)
-{
-	UINT32 result;
-
-	__asm
-	(
-		"mfc0   %[val], $13\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-void CP0_CR_write(UINT32 val)
-{
-	__asm
-	(
-		"mtc0   %[val], $13\n"
-		:
-		: [val] "r" (val)
-	);
-}
-
-UINT32 CP0_PRID_read(void)
-{
-	UINT32 result;
-
-	__asm
-	(
-		"mfc0   %[val], $15\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-// ---------------------------------------------------------------------------------
-char readchar(void)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)sys_uart_stat;
-	volatile UINT32 *pUART_data = (UINT32*)sys_uart_data;
-
-	while(!(0x10 & *pUART_stat));
-
-	return (char)*pUART_data;
-}
-
-void writechar(char c)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)sys_uart_stat;
-	volatile UINT32 *pUART_data = (UINT32*)sys_uart_data;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = (UINT32)c;
-}
-
-void _putchar(char c)
-{
-	if (c == 0x0A)
-	{
-		writechar(0x0D);
-	}
-	writechar(c);
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		_putchar(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_byte(char byte)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 2; i++)
-	{
-		nibble = (char)((byte >> 4) & 0xF);
-		byte <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		_putchar(c);
-	}
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 4; i++)
-	{
-		c = (char) (word >> 24);
-		print_byte(c);
-		word <<= 8;
-	}
-}
-
-// ---------------------------------------------------------------------------------
-// PrintBuffer8()
-// Prints byte buffer as hex and ascii interpretation
-// ---------------------------------------------------------------------------------
-// _Parameters :
-// pBuf:       : IN: Buffer to display
-// nbpr        : Number of bytes per row to display
-// len         : Length of input buffer
-// _Return:      none
-//
-// ---------------------------------------------------------------------------
-void PrintBuffer8(UINT8 *pBuf, int nbpr, int len)
-{
-	memdump(pBuf, 1, nbpr, len);
-}
-
-void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len)
-{
-    int i, j, cnt_hex, cnt_asc, base;
-    unsigned char c;
-
-    i = j = 0;
-    cnt_hex = len;
-    cnt_asc = len;
-    base = 0;
-	if (!print_offset_only)
-		base = (int)pBuf;
-
-    do
-    {
-        print_word(base + i);
-        sputs(": ");
-        for (j=0; j < num_bytes_per_row; j++)
-        {
-            if (cnt_hex)
-            {
-    		    print_byte(pBuf[i+j]);
-		        sputs(" ");
-                cnt_hex--;
-            }
-            else
-            {
-                sputs("   ");
-                break;
-            }
-
-        }
-
-        sputs("   ");
-        for (j=0; j < num_bytes_per_row; j++)
-        {
-            if (cnt_asc)
-            {
-                c = pBuf[i+j];
-                if((c < 0x20) || (c > 0x7F))
-                    c = '.';
-
-                _putchar(c);
-                cnt_asc--;
-            }
-            else
-            {
-                sputs(" ");
-                break;
-            }
-        }
-        sputs("\n");
-        i += num_bytes_per_row;
-
-    } while (cnt_hex);
-}
-

lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h

@@ -1,54 +0,0 @@
-#ifndef LIBSYS_H
-#define LIBSYS_H
-
-// ---------------------------------------------------------
-// Types
-// ---------------------------------------------------------
-#define INT8    char
-#define INT16   short
-#define INT32   long
-#define UINT8   unsigned char
-#define UINT16  unsigned short
-#define UINT32  unsigned long
-#define INT     int
-#define UINT    unsigned int
-#define FLOAT32 float
-#define FLOAT64 double
-
-#define	IS_ERROR(e)		((e & 0x80000000) == 0x80000000)
-
-#define	sys_gpio0		0xA0000000
-#define	sys_gpio1		0xA0000004
-#define	sys_led_port	sys_gpio0
-#define	sys_usb_ctrl	sys_gpio1
-#define	sys_timer_usec	0xA0000008
-#define	sys_timer_sec	0xA000000C
-#define	sys_uart_data	0xA0010000
-#define	sys_uart_stat	0xA0010004
-#define	sys_uart_baud	0xA0010008
-#define	sys_usb_data	0xA0020000
-#define	sys_usb_mbx		0xA0020004
-#define	sys_usb_addr	0xA0020008
-#define	sys_usb_status	0xA002000C
-#define	sys_flash_io	0xA4000000
-#define	sys_flash_mem	0x00000000
-
-// MIPS specific
-UINT32 CP0_SR_read(void);
-void CP0_SR_write(UINT32 val);
-UINT32 CP0_CR_read(void);
-void CP0_CR_write(UINT32 val);
-UINT32 CP0_PRID_read(void);
-
-// General
-char readchar(void);
-void writechar(char c);
-int write(int file, char *ptr, int len);
-int sputs(char *pStr);
-void print_byte(char byte);
-void print_word(int word);
-void PrintBuffer8(UINT8 *pBuf, int nbpr, int len);
-void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len);
-
-#endif // LIBSYS_H
-

lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S

@@ -1,43 +0,0 @@
-		.file	"startup.S"
-	
-		.text
-		.section .init,"ax"
-		.extern _init
-		.align	2
-	
-_start:
-		.set	noreorder
-
-		# set stack pointer 
-		la	$sp, stack_ptr
-
-		# Set Kernel mode
-		li		$26, 0x1040000C
-		mtc0	$26, $12
-		li		$26, 0x00000000
-		mtc0	$26, $13
-
-		mfc0	$26, $15
-		nop
-		mtc0	$26, $31
-
-		# Invalidate I-Cache
-		cop0	32
-		
-		# Invalidate D-Cache
-		cop0	34
-
-		# jump init
-		la $26, _init
-		jalr $26
-		nop
-
-		la $26, main
-		jalr $26
-		nop
-_terminate:
-		nop
-		j		_terminate
-		nop
-	
-		.set	reorder

lib/CPUs/MIPS/bsp/examples/cubic.c

@@ -0,0 +1,64 @@
+/* +++Date last modified: 05-Jul-1997 */
+
+/*
+**  CUBIC.C - Solve a cubic polynomial
+**  public domain by Ross Cottrell
+*/
+
+#include <math.h>
+#include <stdlib.h>
+#include "snipmath.h"
+
+void SolveCubic(double  a,
+                double  b,
+                double  c,
+                double  d,
+                int    *solutions,
+                double *x)
+{
+      long double    a1 = b/a, a2 = c/a, a3 = d/a;
+      long double    Q = (a1*a1 - 3.0*a2)/9.0;
+      long double R = (2.0*a1*a1*a1 - 9.0*a1*a2 + 27.0*a3)/54.0;
+      double    R2_Q3 = R*R - Q*Q*Q;
+
+      double    theta;
+
+      if (R2_Q3 <= 0)
+      {
+            *solutions = 3;
+            theta = acos(R/sqrt(Q*Q*Q));
+            x[0] = -2.0*sqrt(Q)*cos(theta/3.0) - a1/3.0;
+            x[1] = -2.0*sqrt(Q)*cos((theta+2.0*PI)/3.0) - a1/3.0;
+            x[2] = -2.0*sqrt(Q)*cos((theta+4.0*PI)/3.0) - a1/3.0;
+      }
+      else
+      {
+            *solutions = 1;
+            x[0] = pow(sqrt(R2_Q3)+fabs(R), 1/3.0);
+            x[0] += Q/x[0];
+            x[0] *= (R < 0.0) ? 1 : -1;
+            x[0] -= a1/3.0;
+      }
+}
+
+#ifdef TEST
+
+int main(void)
+{
+      double  a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0;
+      double  a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0;
+      double  x[3];
+      int     solutions;
+
+      SolveCubic(a1, b1, c1, d1, &solutions, x);
+
+      /* should get 3 solutions: 2, 6 & 2.5   */
+
+      SolveCubic(a2, b2, c2, d2, &solutions, x);
+
+      /* should get 1 solution: 2.5           */
+
+      return 0;
+}
+
+#endif /* TEST */

lib/CPUs/MIPS/bsp/examples/dbg.c

@@ -3,7 +3,7 @@
 #include <string.h>
 #include "irq.h"
 #include "libsys.h"
-#include "mipsdis.h"
+#include "mips_dis.h"
 
 #define	MAX_USER_BP				16
 #define	BP_MASK_ID				0x00FFF
@@ -28,6 +28,7 @@ typedef struct _sbp_t
 	UINT32 instr;
 } bp_t;
 
+static EXCEPTION_CONTEXT xcp_last;
 static bp_t user_bp[MAX_USER_BP];
 static bp_t mgmt_bp_ss[2];
 static bp_t mgmt_bp_ru[2];
@@ -44,68 +45,82 @@ UINT32 BreakGetType(UINT32 instr)
 	return (instr >> 6) & BP_MASK_TYPE;
 }
 
+char* reg_changed(UINT32 reg1, UINT32 reg2)
+{
+	static char chg_str[2] = {0};
+
+	if (reg1 != reg2)
+		chg_str[0] = '*';
+	else
+		chg_str[0] = ' ';
+
+	return chg_str;
+}
+
 void dbg_handler(struct xcptcontext * xcp)
 {
 
  	UINT32 bp_addr, bp_index = 0, branch_addr, reg, result, bp_type;
     int junk, i, leave_isr, is_branch_shadow, is_user_bp;
-	UINT32 volatile *pBtn = (UINT32*)sys_gpio0;
+	UINT32 volatile *pBtn = (UINT32*)SYS_GPIO0;
 	UINT32 *pInstr, *pAddr_curr, *pAddr_prev, *pAddr_next;
 
 	sputs("\n");
-	PRINT_REG(" Status : ", xcp->sr);
-	PRINT_REG("  Cause : ", xcp->cr);
-	PRINT_REG("    EPC : ", xcp->epc);
-	PRINT_REG("BadAddr : ", xcp->baddr);
+	PRINT_REG_CHG(" Status : ", xcp->sr, reg_changed(xcp->sr, xcp_last.sr));
+	PRINT_REG_CHG("  Cause : ", xcp->cr, reg_changed(xcp->cr, xcp_last.cr));
+	PRINT_REG_CHG("    EPC : ", xcp->epc, reg_changed(xcp->epc, xcp_last.epc));
+	PRINT_REG_CHG("BadAddr : ", xcp->baddr, reg_changed(xcp->baddr, xcp_last.baddr));
 	sputs("\n");
-	PRINT_REG("   MDLO : ", xcp->mdlo);
-	PRINT_REG("   MDHI : ", xcp->mdhi);
+	PRINT_REG_CHG("   MDLO : ", xcp->mdlo, reg_changed(xcp->mdlo, xcp_last.mdlo));
+	PRINT_REG_CHG("   MDHI : ", xcp->mdhi, reg_changed(xcp->mdhi, xcp_last.mdhi));
 
 	sputs("\n");
 
 	sputs("Registers:\n");
-	PRINT_REG(" 0 (ze) : ", xcp->regs[0]);
-	PRINT_REG(" 1 (at) : ", xcp->regs[1]);
-	PRINT_REG(" 2 (v0) : ", xcp->regs[2]);
-	PRINT_REG(" 3 (v1) : ", xcp->regs[3]);
+	PRINT_REG_CHG(" 0 (ze) : ", xcp->regs[0], reg_changed(xcp->regs[0], xcp_last.regs[0]));
+	PRINT_REG_CHG(" 1 (at) : ", xcp->regs[1], reg_changed(xcp->regs[1], xcp_last.regs[1]));
+	PRINT_REG_CHG(" 2 (v0) : ", xcp->regs[2], reg_changed(xcp->regs[2], xcp_last.regs[2]));
+	PRINT_REG_CHG(" 3 (v1) : ", xcp->regs[3], reg_changed(xcp->regs[3], xcp_last.regs[3]));
 	sputs("\n");
-	PRINT_REG(" 4 (a0) : ", xcp->regs[4]);
-	PRINT_REG(" 5 (a1) : ", xcp->regs[5]);
-	PRINT_REG(" 6 (a2) : ", xcp->regs[6]);
-	PRINT_REG(" 7 (a3) : ", xcp->regs[7]);
+	PRINT_REG_CHG(" 4 (a0) : ", xcp->regs[4], reg_changed(xcp->regs[4], xcp_last.regs[4]));
+	PRINT_REG_CHG(" 5 (a1) : ", xcp->regs[5], reg_changed(xcp->regs[5], xcp_last.regs[5]));
+	PRINT_REG_CHG(" 6 (a2) : ", xcp->regs[6], reg_changed(xcp->regs[6], xcp_last.regs[6]));
+	PRINT_REG_CHG(" 7 (a3) : ", xcp->regs[7], reg_changed(xcp->regs[7], xcp_last.regs[7]));
 	sputs("\n");
-	PRINT_REG(" 8 (t0) : ", xcp->regs[8]);
-	PRINT_REG(" 9 (t1) : ", xcp->regs[9]);
-	PRINT_REG("10 (t2) : ", xcp->regs[10]);
-	PRINT_REG("11 (t3) : ", xcp->regs[11]);
+	PRINT_REG_CHG(" 8 (t0) : ", xcp->regs[8], reg_changed(xcp->regs[8], xcp_last.regs[8]));
+	PRINT_REG_CHG(" 9 (t1) : ", xcp->regs[9], reg_changed(xcp->regs[9], xcp_last.regs[9]));
+	PRINT_REG_CHG("10 (t2) : ", xcp->regs[10], reg_changed(xcp->regs[10], xcp_last.regs[10]));
+	PRINT_REG_CHG("11 (t3) : ", xcp->regs[11], reg_changed(xcp->regs[11], xcp_last.regs[11]));
 	sputs("\n");
-	PRINT_REG("12 (t4) : ", xcp->regs[12]);
-	PRINT_REG("13 (t5) : ", xcp->regs[13]);
-	PRINT_REG("14 (t6) : ", xcp->regs[14]);
-	PRINT_REG("15 (t7) : ", xcp->regs[15]);
+	PRINT_REG_CHG("12 (t4) : ", xcp->regs[12], reg_changed(xcp->regs[12], xcp_last.regs[12]));
+	PRINT_REG_CHG("13 (t5) : ", xcp->regs[13], reg_changed(xcp->regs[13], xcp_last.regs[13]));
+	PRINT_REG_CHG("14 (t6) : ", xcp->regs[14], reg_changed(xcp->regs[14], xcp_last.regs[14]));
+	PRINT_REG_CHG("15 (t7) : ", xcp->regs[15], reg_changed(xcp->regs[15], xcp_last.regs[15]));
 	sputs("\n");
-	PRINT_REG("16 (s0) : ", xcp->regs[16]);
-	PRINT_REG("17 (s1) : ", xcp->regs[17]);
-	PRINT_REG("18 (s2) : ", xcp->regs[18]);
-	PRINT_REG("19 (s3) : ", xcp->regs[19]);
+	PRINT_REG_CHG("16 (s0) : ", xcp->regs[16], reg_changed(xcp->regs[16], xcp_last.regs[16]));
+	PRINT_REG_CHG("17 (s1) : ", xcp->regs[17], reg_changed(xcp->regs[17], xcp_last.regs[17]));
+	PRINT_REG_CHG("18 (s2) : ", xcp->regs[18], reg_changed(xcp->regs[18], xcp_last.regs[18]));
+	PRINT_REG_CHG("19 (s3) : ", xcp->regs[19], reg_changed(xcp->regs[19], xcp_last.regs[19]));
 	sputs("\n");
-	PRINT_REG("20 (s4) : ", xcp->regs[20]);
-	PRINT_REG("21 (s5) : ", xcp->regs[21]);
-	PRINT_REG("22 (s6) : ", xcp->regs[22]);
-	PRINT_REG("23 (s7) : ", xcp->regs[23]);
+	PRINT_REG_CHG("20 (s4) : ", xcp->regs[20], reg_changed(xcp->regs[20], xcp_last.regs[20]));
+	PRINT_REG_CHG("21 (s5) : ", xcp->regs[21], reg_changed(xcp->regs[21], xcp_last.regs[21]));
+	PRINT_REG_CHG("22 (s6) : ", xcp->regs[22], reg_changed(xcp->regs[22], xcp_last.regs[22]));
+	PRINT_REG_CHG("23 (s7) : ", xcp->regs[23], reg_changed(xcp->regs[23], xcp_last.regs[23]));
 	sputs("\n");
-	PRINT_REG("24 (t8) : ", xcp->regs[24]);
-	PRINT_REG("25 (t9) : ", xcp->regs[25]);
-	PRINT_REG("26 (k0) : ", xcp->regs[26]);
-	PRINT_REG("27 (k1) : ", xcp->regs[27]);
+	PRINT_REG_CHG("24 (s8) : ", xcp->regs[24], reg_changed(xcp->regs[24], xcp_last.regs[24]));
+	PRINT_REG_CHG("25 (s9) : ", xcp->regs[25], reg_changed(xcp->regs[25], xcp_last.regs[25]));
+	PRINT_REG_CHG("26 (k0) : ", xcp->regs[26], reg_changed(xcp->regs[26], xcp_last.regs[26]));
+	PRINT_REG_CHG("27 (k1) : ", xcp->regs[27], reg_changed(xcp->regs[27], xcp_last.regs[27]));
 	sputs("\n");
-	PRINT_REG("28 (gp) : ", xcp->regs[28]);
-	PRINT_REG("29 (sp) : ", xcp->regs[29]);
-	PRINT_REG("30 (fp) : ", xcp->regs[30]);
-	PRINT_REG("31 (ra) : ", xcp->regs[31]);
+	PRINT_REG_CHG("28 (gp) : ", xcp->regs[28], reg_changed(xcp->regs[28], xcp_last.regs[28]));
+	PRINT_REG_CHG("29 (sp) : ", xcp->regs[29], reg_changed(xcp->regs[29], xcp_last.regs[29]));
+	PRINT_REG_CHG("30 (fp) : ", xcp->regs[30], reg_changed(xcp->regs[30], xcp_last.regs[30]));
+	PRINT_REG_CHG("31 (ra) : ", xcp->regs[31], reg_changed(xcp->regs[31], xcp_last.regs[31]));
 	sputs("\n");
 	sputs("\n");
 
+	memcpy(&xcp_last, xcp, sizeof(EXCEPTION_CONTEXT));
+
 	is_user_bp = 0;
 	pAddr_curr = (UINT32*)xcp->epc;
 	is_branch_shadow = ((xcp->cr & 0x80000000) == 0x80000000);
@@ -124,12 +139,12 @@ void dbg_handler(struct xcptcontext * xcp)
 			case BP_MGMT_BASE_SS:
 
 			// Restore original instructions after single-step
-			sputs("1. Restore after single-step at ");print_word((long)mgmt_bp_ss[0].pAddr);sputs("\n");
+//			sputs("1. Restore after single-step at ");print_word((long)mgmt_bp_ss[0].pAddr);sputs("\n");
 			*(mgmt_bp_ss[0].pAddr) = mgmt_bp_ss[0].instr;
 			ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr);
 			if (mgmt_bp_ss[1].pAddr)
 			{
-				sputs("2. Restore after single-step at ");print_word((long)mgmt_bp_ss[1].pAddr);sputs("\n");
+//				sputs("2. Restore after single-step at ");print_word((long)mgmt_bp_ss[1].pAddr);sputs("\n");
 				*(mgmt_bp_ss[1].pAddr) = mgmt_bp_ss[1].instr;
 				ICACHE_invalidate_at(mgmt_bp_ss[1].pAddr);
 			}
@@ -139,19 +154,19 @@ void dbg_handler(struct xcptcontext * xcp)
 			case BP_MGMT_BASE_RU:
 
 			bp_index = BP_GET_ID(*pAddr_curr);
-			sputs("Restore user break at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n");
+//			sputs("Restore user break at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n");
 
 			*(user_bp[bp_index].pAddr) = BP_USER(bp_index);
 			ICACHE_invalidate_at(user_bp[bp_index].pAddr);
 
 			*(mgmt_bp_ru[0].pAddr) = mgmt_bp_ru[0].instr;
 			ICACHE_invalidate_at(mgmt_bp_ru[0].pAddr);
-			sputs("1. Restore after RU at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n");
+//			sputs("1. Restore after RU at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n");
 			if (mgmt_bp_ru[1].pAddr)
 			{
 				*(mgmt_bp_ru[1].pAddr) = mgmt_bp_ru[1].instr;
 				ICACHE_invalidate_at(mgmt_bp_ru[1].pAddr);
-				sputs("2. Restore after RU at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n");
+//				sputs("2. Restore after RU at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n");
 			}
 			if (!g_is_ss)
 				return;
@@ -162,12 +177,13 @@ void dbg_handler(struct xcptcontext * xcp)
 
 			is_user_bp = 1;
 			bp_index = BP_GET_ID(*pAddr_curr);
-			sputs("Restore instruction at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n");
+//			sputs("Restore instruction at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n");
 			*(user_bp[bp_index].pAddr) = user_bp[bp_index].instr;
 			ICACHE_invalidate_at(user_bp[bp_index].pAddr);
 			break;
 
 			default:
+//			sputs("Found ordinary break at ");print_word((long)pAddr_curr);sputs("\n");
 			break;
 
 		}
@@ -209,7 +225,7 @@ void dbg_handler(struct xcptcontext * xcp)
 		ICACHE_invalidate_at(mgmt_bp_ru[0].pAddr);
 		mgmt_bp_ru[1].pAddr = NULL;
 		mgmt_bp_ru[1].pAddr = 0;
-		sputs("1. Insert RU-break at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n");
+//		sputs("1. Insert RU-break at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n");
 
 		// We have two possible management breaks, if previous instruction was branch or jump
 		if (is_branch_shadow)
@@ -226,18 +242,25 @@ void dbg_handler(struct xcptcontext * xcp)
 			// Replace instruction with managment breakpoint
 			*(mgmt_bp_ru[1].pAddr) = BP_MGMT_RU(bp_index);
 			ICACHE_invalidate_at(mgmt_bp_ru[1].pAddr);
-			sputs("2. Insert RU-break at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n");
+//			sputs("2. Insert RU-break at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n");
 		}
 	}
 
 	do
 	{
 		leave_isr = 0;
-		switch(readchar())
+		switch(_getchar())
 		{
 			case 'g':
 			leave_isr = 1;
 			g_is_ss = 0;
+			if (IsBreak(*pAddr_curr))
+			{
+				if (BreakGetType(*pAddr_curr) != BP_USER_BASE)
+				{
+					xcp->epc += 4;		// Skip ordinary program breaks
+				}
+			}
 			break;
 
 			case 'b':
@@ -258,12 +281,23 @@ void dbg_handler(struct xcptcontext * xcp)
 			g_is_ss = 1;
 			leave_isr = 1;
 			// Don't overwrite RU breaks
+//			printf("is_user_bp = %d, IsBreak = %d, pAddr_curr = %08X, *pAddr_curr = %08X\n", is_user_bp, IsBreak(*pAddr_curr), pAddr_curr, *pAddr_curr);
+
 			if (is_user_bp)
 				break;
-			// Don't overwrite user breaks
-			if (IsBreak(*pInstr) && (BreakGetType(*pInstr) == BP_USER_BASE))
-				break;
 
+			// Don't overwrite user breaks
+			if (IsBreak(*pAddr_curr))
+			{
+				if (BreakGetType(*pAddr_curr) == BP_USER_BASE)
+				{
+					break;
+				}
+				else
+				{
+					xcp->epc += 4;		// Skip ordinary program breaks
+				}
+			}
 			// Save original instruction
 			mgmt_bp_ss[0].pAddr = pAddr_next;
 			mgmt_bp_ss[0].instr = *(mgmt_bp_ss[0].pAddr);
@@ -297,7 +331,7 @@ void dbg_handler(struct xcptcontext * xcp)
 			if (is_user_bp)
 				break;
 			// Don't overwrite user breaks
-			if (IsBreak(*pInstr) && (BreakGetType(*pInstr) == BP_USER_BASE))
+			if (IsBreak(*pAddr_curr) && (BreakGetType(*pAddr_curr) == BP_USER_BASE))
 				break;
 
 			// Save original instruction
@@ -332,7 +366,7 @@ int debug_break(struct xcptcontext * xcp)
 
 void dbg_init(void)
 {
-
+	memset(&xcp_last, 0, sizeof(EXCEPTION_CONTEXT));
 	interrupt_register(2, debug_int);
 	interrupt_enable(2);
 

lib/CPUs/MIPS/bsp/examples/delay_mips.c

@@ -0,0 +1,15 @@
+// MIPS delay.
+
+void __inline__ delay(int loops)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		"1:bnez	%[loops], 1b\n"
+		"addiu	%[loops], -1\n"
+		".set	reorder\n"
+		:
+		: [loops] "r" (loops)
+	);
+}
+

lib/CPUs/MIPS/bsp/examples/demo.c

@@ -0,0 +1,67 @@
+/*
+*   Byte-oriented AES-256 implementation.
+*   All lookup tables replaced with 'on the fly' calculations.
+*
+*   Copyright (c) 2007 Ilya O. Levin, http://www.literatecode.com
+*
+*   Permission to use, copy, modify, and distribute this software for any
+*   purpose with or without fee is hereby granted, provided that the above
+*   copyright notice and this permission notice appear in all copies.
+*
+*   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+*   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+*   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+*   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+*   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+*   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+*   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+#include <stdlib.h>
+#include <stdio.h>
+#include <time.h>
+#include <sys/times.h>
+#include <sys/time.h>
+#include "aes256.h"
+
+#define DUMP(s, i, buf, sz)  {printf(s);                   \
+                              for (i = 0; i < (sz);i++)    \
+                                  printf("%02x ", buf[i]); \
+                              printf("\n");}
+
+
+int main (int argc, char *argv[])
+{
+    aes256_context ctx;
+    uint8_t key[32];
+    uint8_t buf[16], i;
+	long start, end, j;
+
+    /* put a test vector */
+    for (i = 0; i < sizeof(buf);i++) buf[i] = i * 16 + i;
+    for (i = 0; i < sizeof(key);i++) key[i] = i;
+
+    DUMP("txt: ", i, buf, sizeof(buf));
+    DUMP("key: ", i, key, sizeof(key));
+    printf("---\n");
+
+    aes256_init(&ctx, key);
+	start = clock();
+	for (j=0; j < 1000; j++)
+	{
+	    aes256_encrypt_ecb(&ctx, buf);
+  	}
+	end = clock();
+
+	printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC));
+
+    DUMP("enc: ", i, buf, sizeof(buf));
+    printf("tst: 8e a2 b7 ca 51 67 45 bf ea fc 49 90 4b 49 60 89\n");
+
+    aes256_init(&ctx, key);
+    aes256_decrypt_ecb(&ctx, buf);
+    DUMP("dec: ", i, buf, sizeof(buf));
+
+    aes256_done(&ctx);
+
+    return 0;
+} /* main */

lib/CPUs/MIPS/bsp/examples/gunzip.c

@@ -19,8 +19,8 @@ volatile int file_len;
 
 void handler3(void)
 {
-	volatile UINT32 *pUART_stat = (UINT32*)sys_uart0_stat;
-	volatile UINT32 *pUART_data = (UINT32*)sys_uart0_data;
+	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART0_STAT;
+	volatile UINT32 *pUART_data = (UINT32*)SYS_UART0_DATA;
 
 	while(0x200 & *pUART_stat)
 	{
@@ -45,7 +45,7 @@ int READBYTE(z_stream *zs) {
 #define MAX_BUFOUT	16*1024*1024
 int main(int argc, char **argv)
 {
-	volatile UINT32 *pUART_stat = (UINT32*)sys_uart0_stat;
+	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART0_STAT;
 	unsigned char outData[MAX_BUFOUT];
 	FILE *infp;
 	int i, gpflags, tmp[4];

lib/CPUs/MIPS/bsp/examples/hashtest.c

@@ -0,0 +1,323 @@
+/********************************************************************\
+ *
+ *      FILE:     hashtest.c
+ *
+ *      CONTENTS: test file for sample C-implementation of
+ *                RIPEMD-160 and RIPEMD128
+ *        * command line arguments:
+ *           filename  -- compute hash code of file read binary
+ *           -sstring  -- print string & hashcode
+ *           -t        -- perform time trial
+ *           -x        -- execute standard test suite, ASCII input
+ *        * for linkage with rmd128.c: define RMDsize as 128
+ *          for linkage with rmd160.c: define RMDsize as 160 (default)
+ *      TARGET:   any computer with an ANSI C compiler
+ *
+ *      AUTHOR:   Antoon Bosselaers, ESAT-COSIC
+ *      DATE:     18 April 1996
+ *      VERSION:  1.1
+ *      HISTORY:  bug in RMDonemillion() corrected
+ *
+ *      Copyright (c) Katholieke Universiteit Leuven
+ *      1996, All Rights Reserved
+ *
+ *  Conditions for use of the RIPEMD-160 Software
+ *
+ *  The RIPEMD-160 software is freely available for use under the terms and
+ *  conditions described hereunder, which shall be deemed to be accepted by
+ *  any user of the software and applicable on any use of the software:
+ *
+ *  1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for
+ *     all purposes be considered the owner of the RIPEMD-160 software and of
+ *     all copyright, trade secret, patent or other intellectual property
+ *     rights therein.
+ *  2. The RIPEMD-160 software is provided on an "as is" basis without
+ *     warranty of any sort, express or implied. K.U.Leuven makes no
+ *     representation that the use of the software will not infringe any
+ *     patent or proprietary right of third parties. User will indemnify
+ *     K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities
+ *     which may arise as a result of its use of the software. In no
+ *     circumstances K.U.Leuven R&D will be held liable for any deficiency,
+ *     fault or other mishappening with regard to the use or performance of
+ *     the software.
+ *  3. User agrees to give due credit to K.U.Leuven in scientific publications
+ *     or communications in relation with the use of the RIPEMD-160 software
+ *     as follows: RIPEMD-160 software written by Antoon Bosselaers,
+ *     available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/.
+ *
+\********************************************************************/
+#ifndef RMDsize
+#define RMDsize 160
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <time.h>
+#include <string.h>
+#if RMDsize == 128
+#include "rmd128.h"
+#elif RMDsize == 160
+#include "rmd160.h"
+#endif
+
+#define TEST_BLOCK_SIZE 8000
+#define TEST_BLOCKS 1250
+#define TEST_BYTES ((long)TEST_BLOCK_SIZE * (long)TEST_BLOCKS)
+
+/********************************************************************/
+
+byte *RMD(byte *message)
+/*
+ * returns RMD(message)
+ * message should be a string terminated by '\0'
+ */
+{
+   dword         MDbuf[RMDsize/32];   /* contains (A, B, C, D(, E))   */
+   static byte   hashcode[RMDsize/8]; /* for final hash-value         */
+   dword         X[16];               /* current 16-word chunk        */
+   unsigned int  i;                   /* counter                      */
+   dword         length;              /* length in bytes of message   */
+   dword         nbytes;              /* # of bytes not yet processed */
+
+   /* initialize */
+   MDinit(MDbuf);
+   length = (dword)strlen((char *)message);
+
+   /* process message in 16-word chunks */
+   for (nbytes=length; nbytes > 63; nbytes-=64) {
+      for (i=0; i<16; i++) {
+         X[i] = BYTES_TO_DWORD(message);
+         message += 4;
+      }
+      compress(MDbuf, X);
+   }                                    /* length mod 64 bytes left */
+
+   /* finish: */
+   MDfinish(MDbuf, message, length, 0);
+
+   for (i=0; i<RMDsize/8; i+=4) {
+      hashcode[i]   =  MDbuf[i>>2];         /* implicit cast to byte  */
+      hashcode[i+1] = (MDbuf[i>>2] >>  8);  /*  extracts the 8 least  */
+      hashcode[i+2] = (MDbuf[i>>2] >> 16);  /*  significant bits.     */
+      hashcode[i+3] = (MDbuf[i>>2] >> 24);
+   }
+
+   return (byte *)hashcode;
+}
+
+/********************************************************************/
+
+byte *RMDbinary(char *fname)
+/*
+ * returns RMD(message in file fname)
+ * fname is read as binary data.
+ */
+{
+   FILE         *mf;                  /* pointer to file <fname>      */
+   byte          data[1024];          /* contains current mess. block */
+   dword         nbytes;              /* length of this block         */
+   dword         MDbuf[RMDsize/32];   /* contains (A, B, C, D(, E))   */
+   static byte   hashcode[RMDsize/8]; /* for final hash-value         */
+   dword         X[16];               /* current 16-word chunk        */
+   unsigned int  i, j;                /* counters                     */
+   dword         length[2];           /* length in bytes of message   */
+   dword         offset;              /* # of unprocessed bytes at    */
+                                      /*          call of MDfinish    */
+
+   /* initialize */
+   if ((mf = fopen(fname, "rb")) == NULL) {
+      fprintf(stderr, "\nRMDbinary: cannot open file \"%s\".\n",
+              fname);
+      exit(1);
+   }
+   MDinit(MDbuf);
+   length[0] = 0;
+   length[1] = 0;
+
+   while ((nbytes = fread(data, 1, 1024, mf)) != 0) {
+      /* process all complete blocks */
+      for (i=0; i<(nbytes>>6); i++) {
+         for (j=0; j<16; j++)
+            X[j] = BYTES_TO_DWORD(data+64*i+4*j);
+         compress(MDbuf, X);
+      }
+      /* update length[] */
+      if (length[0] + nbytes < length[0])
+         length[1]++;                  /* overflow to msb of length */
+      length[0] += nbytes;
+   }
+
+   /* finish: */
+   offset = length[0] & 0x3C0;   /* extract bytes 6 to 10 inclusive */
+   MDfinish(MDbuf, data+offset, length[0], length[1]);
+
+   for (i=0; i<RMDsize/8; i+=4) {
+      hashcode[i]   =  MDbuf[i>>2];
+      hashcode[i+1] = (MDbuf[i>>2] >>  8);
+      hashcode[i+2] = (MDbuf[i>>2] >> 16);
+      hashcode[i+3] = (MDbuf[i>>2] >> 24);
+   }
+
+   fclose(mf);
+
+   return (byte *)hashcode;
+}
+
+/********************************************************************/
+
+void speedtest(void)
+/*
+ * A time trial routine, to measure the speed of ripemd.
+ * Measures processor time required to process TEST_BLOCKS times
+ *  a message of TEST_BLOCK_SIZE characters.
+ */
+{
+   clock_t      t0, t1;
+   byte        *data;
+   byte         hashcode[RMDsize/8];
+   dword        X[16];
+   dword        MDbuf[RMDsize/32];
+   unsigned int i, j, k;
+
+   srand(time(NULL));
+
+   /* allocate and initialize test data */
+   if ((data = (byte*)malloc(TEST_BLOCK_SIZE)) == NULL) {
+      fprintf(stderr, "speedtest: allocation error\n");
+      exit(1);
+   }
+   for (i=0; i<TEST_BLOCK_SIZE; i++)
+      data[i] = (byte)(rand() >> 7);
+
+   /* start timer */
+   printf("\n\nRIPEMD-%u time trial. Processing %ld characters...\n",
+          RMDsize, TEST_BYTES);
+   t0 = clock();
+
+   /* process data */
+   MDinit(MDbuf);
+   for (i=0; i<TEST_BLOCKS; i++) {
+      for (j=0; j<TEST_BLOCK_SIZE; j+=64) {
+         for (k=0; k<16; k++)
+            X[k] = BYTES_TO_DWORD(data+j+4*k);
+         compress(MDbuf, X);
+      }
+   }
+   MDfinish(MDbuf, data, TEST_BYTES, 0);
+
+   /* stop timer, get time difference */
+   t1 = clock();
+   printf("\nTest input processed in %g seconds.\n",
+          (double)(t1-t0)/(double)CLOCKS_PER_SEC);
+   printf("Characters processed per second: %g\n",
+          (double)CLOCKS_PER_SEC*TEST_BYTES/((double)t1-t0));
+
+	printf("\n=> %3.2f Mbit/s\n\n", 8*(double)CLOCKS_PER_SEC*TEST_BYTES/((double)t1-t0)/(1024*1024));
+
+   for (i=0; i<RMDsize/8; i+=4) {
+      hashcode[i]   =  MDbuf[i>>2];
+      hashcode[i+1] = (MDbuf[i>>2] >>  8);
+      hashcode[i+2] = (MDbuf[i>>2] >> 16);
+      hashcode[i+3] = (MDbuf[i>>2] >> 24);
+   }
+   printf("\nhashcode: ");
+   for (i=0; i<RMDsize/8; i++)
+      printf("%02x", hashcode[i]);
+   printf("\n");
+
+   free(data);
+   return;
+}
+
+/********************************************************************/
+
+void RMDonemillion(void)
+/*
+ * returns RMD() of message consisting of 1 million 'a' characters
+ */
+{
+   dword         MDbuf[RMDsize/32];   /* contains (A, B, C, D(, E)) */
+   static byte   hashcode[RMDsize/8]; /* for final hash-value       */
+   dword         X[16];               /* current 16-word chunk      */
+   unsigned int  i;                   /* counter                    */
+
+   MDinit(MDbuf);
+   memcpy(X, "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa", 32);
+   memcpy(X+8, X, 32);
+   for (i=15625; i>0; i--)
+      compress(MDbuf, X);
+   MDfinish(MDbuf, NULL, 1000000UL, 0);
+   for (i=0; i<RMDsize/8; i+=4) {
+      hashcode[i]   =  MDbuf[i>>2];
+      hashcode[i+1] = (MDbuf[i>>2] >>  8);
+      hashcode[i+2] = (MDbuf[i>>2] >> 16);
+      hashcode[i+3] = (MDbuf[i>>2] >> 24);
+   }
+   printf("\n* message: 1 million times \"a\"\n  hashcode: ");
+   for (i=0; i<RMDsize/8; i++)
+      printf("%02x", hashcode[i]);
+
+}
+
+/********************************************************************/
+
+void RMDstring(char *message, char *print)
+{
+   unsigned int  i;
+   byte         *hashcode;
+
+   hashcode = RMD((byte *)message);
+   printf("\n* message: %s\n  hashcode: ", print);
+   for (i=0; i<RMDsize/8; i++)
+      printf("%02x", hashcode[i]);
+}
+
+/********************************************************************/
+
+void testsuite (void)
+/*
+ *   standard test suite
+ */
+{
+   printf("\n\nRIPEMD-%u test suite results (ASCII):\n", RMDsize);
+
+   RMDstring("", "\"\" (empty string)");
+   RMDstring("a", "\"a\"");
+   RMDstring("abc", "\"abc\"");
+   RMDstring("message digest", "\"message digest\"");
+   RMDstring("abcdefghijklmnopqrstuvwxyz", "\"abcdefghijklmnopqrstuvwxyz\"");
+   RMDstring("abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
+             "\"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq\"");
+   RMDstring("ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789",
+             "\"A...Za...z0...9\"");
+   RMDstring("1234567890123456789012345678901234567890"
+             "1234567890123456789012345678901234567890",
+             "8 times \"1234567890\"");
+   RMDonemillion();
+   printf("\n");
+
+   return;
+}
+
+/********************************************************************/
+
+main (int argc, char *argv[])
+/*
+ *  main program. calls one or more of the test routines depending
+ *  on command line arguments. see the header of this file.
+ *
+ */
+{
+	while(1)
+	{
+//		testsuite ();
+//		printf("\n");
+		speedtest ();
+		printf("\n");
+	}
+
+	return 0;
+}
+
+/********************** end of file hashtest.c **********************/
+

lib/CPUs/MIPS/bsp/examples/hpi.c

@@ -0,0 +1,949 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include "libsys.h"
+#include "hpi.h"
+
+static volatile UINT32 _g_int_active;
+static volatile UINT32 _g_mbx_return;
+static volatile UINT32 _g_mbx_in_flag;
+
+// ---------------------------------------------------------
+// Globals
+// ---------------------------------------------------------
+typedef struct _susb_t
+{
+	fp_t fptr_ept[USB_MAX_NUM_EPT];
+	void *aptr_ept[USB_MAX_NUM_EPT];
+
+	fp_t fptr_rst;
+	void *aptr_rst;
+
+	fp_t fptr_sof;
+	void *aptr_sof;
+
+	fp_t fptr_cfg;
+	void *aptr_cfg;
+
+	fp_t fptr_sus;
+	void *aptr_sus;
+
+	fp_t fptr_id;
+	void *aptr_id;
+
+	fp_t fptr_vbus;
+	void *aptr_vbus;
+
+} usb_t;
+
+static usb_t _g_usb[USB_MAX_NUM_PORTS];
+//static usb_irp_t *_g_usb_irp_ptr[USB_MAX_NUM_PORTS][USB_MAX_NUM_EPT];
+
+// ---------------------------------------------------------
+// HPI ISR
+// ---------------------------------------------------------
+void cy67k3_isr(void)
+{
+	INT32 i;
+	UINT16 sie_msg, hpi_status;
+	UINT32 port, siemsg_handled, int_handled;
+	_g_int_active = 1;
+//	sputs("--------------------------------------------------------\n");
+//	sputs("USB-Interrupt(4)\n");
+//	sputs("HPI Status   : ");
+	hpi_status = cy67k3_read_HPI_STATUS();
+//	print_word(hpi_status);
+//	sputs("\n");
+
+//	sputs("MAILBOX (REG): ");
+
+//	cy67k3_write(HPI_ADDRESS, HPI_REG_MAILBOX);
+//	print_word(cy67k3_read_HPI_DATA());
+//	sputs("\n");
+
+	int_handled = 0;
+	if (hpi_status & HPI_STATUS_MBX_IN)
+	{
+		int_handled = 1;
+//		sputs("MAILBOX (HPI): ");
+		_g_mbx_return = cy67k3_read_HPI_MAILBOX();
+		_g_mbx_in_flag = 1;
+//		print_word(_g_mbx_return);
+//		sputs("\n");
+	}
+
+	if (hpi_status & HPI_STATUS_RESET1)
+	{
+		int_handled = 1;
+		hpi_read_reg(SUSB1_REG_STATUS);
+		hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 1);
+//		sputs("RESET 1\n");
+	}
+
+	if (hpi_status & HPI_STATUS_RESET2)
+	{
+		int_handled = 1;
+		hpi_read_reg(SUSB2_REG_STATUS);
+		hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 2);
+//		sputs("RESET 2\n");
+	}
+
+	if (hpi_status & HPI_STATUS_DONE1)
+	{
+		int_handled = 1;
+//		sputs("DONE 1\n");
+	}
+
+	if (hpi_status & HPI_STATUS_DONE2)
+	{
+		int_handled = 1;
+//		sputs("DONE 2\n");
+	}
+
+	if (hpi_status & HPI_STATUS_SOFEOP1)
+	{
+		int_handled = 1;
+		hpi_read_reg(SUSB1_REG_STATUS);
+//		sputs("SOF/EOP 1\n");
+	}
+
+	if (hpi_status & HPI_STATUS_SOFEOP2)
+	{
+		int_handled = 1;
+		hpi_read_reg(SUSB2_REG_STATUS);
+//		sputs("SOF/EOP 2\n");
+	}
+
+	port = 0;
+	siemsg_handled = 0;
+	if (hpi_status & HPI_STATUS_SIEMSG1)
+	{
+		int_handled = 1;
+		sie_msg = hpi_read_reg(HPI_REG_SIE1MSG);
+
+		// Reset message register
+		hpi_write_reg(HPI_REG_SIE1MSG, 0x0000);
+
+		if (sie_msg & SUSB_RST_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_rst)
+				(_g_usb[port].fptr_rst)(_g_usb[port].aptr_rst);
+		}
+
+		if (sie_msg & SUSB_SOF_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_sof)
+				(_g_usb[port].fptr_sof)(_g_usb[port].aptr_sof);
+		}
+
+		if (sie_msg & SUSB_CFG_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_cfg)
+				(_g_usb[port].fptr_cfg)(_g_usb[port].aptr_cfg);
+		}
+
+		if (sie_msg & SUSB_SUS_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_sus)
+				(_g_usb[port].fptr_sus)(_g_usb[port].aptr_sus);
+		}
+
+		if (sie_msg & SUSB_ID_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_id)
+				(_g_usb[port].fptr_id)(_g_usb[port].aptr_id);
+		}
+
+		if (sie_msg & SUSB_VBUS_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_vbus)
+				(_g_usb[port].fptr_vbus)(_g_usb[port].aptr_vbus);
+		}
+
+		for (i=0; i < 8; i++)
+		{
+			if (sie_msg & (SUSB_EP0_MSG << i))
+			{
+				siemsg_handled = 1;
+				if (_g_usb[port].fptr_ept[i])
+					(_g_usb[port].fptr_ept[i])(_g_usb[port].aptr_ept[i]);
+			}
+		}
+		if (!siemsg_handled)
+		{
+			sputs("Unhandled SIE1 message ");
+			print_word(sie_msg);
+			sputs("!\n");
+		}
+
+	}
+	port = 1;
+	siemsg_handled = 0;
+	if (hpi_status & HPI_STATUS_SIEMSG2)
+	{
+		int_handled = 1;
+		sie_msg = hpi_read_reg(HPI_REG_SIE2MSG);
+
+		// Reset message register
+		hpi_write_reg(HPI_REG_SIE2MSG, 0x0000);
+
+		if (sie_msg & SUSB_RST_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_rst)
+				(_g_usb[port].fptr_rst)(_g_usb[port].aptr_rst);
+		}
+
+		if (sie_msg & SUSB_SOF_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_sof)
+				(_g_usb[port].fptr_sof)(_g_usb[port].aptr_sof);
+		}
+
+		if (sie_msg & SUSB_CFG_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_cfg)
+				(_g_usb[port].fptr_cfg)(_g_usb[port].aptr_cfg);
+		}
+
+		if (sie_msg & SUSB_SUS_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_sus)
+				(_g_usb[port].fptr_sus)(_g_usb[port].aptr_sus);
+		}
+
+		if (sie_msg & SUSB_ID_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_id)
+				(_g_usb[port].fptr_id)(_g_usb[port].aptr_id);
+		}
+
+		if (sie_msg & SUSB_VBUS_MSG)
+		{
+			siemsg_handled = 1;
+			if (_g_usb[port].fptr_vbus)
+				(_g_usb[port].fptr_vbus)(_g_usb[port].aptr_vbus);
+		}
+
+		for (i=0; i < 8; i++)
+		{
+			if (sie_msg & (SUSB_EP0_MSG << i))
+			{
+				siemsg_handled = 1;
+				if (_g_usb[port].fptr_ept[i])
+					(_g_usb[port].fptr_ept[i])(_g_usb[port].aptr_ept[i]);
+			}
+		}
+		if (!siemsg_handled)
+		{
+			sputs("Unhandled SIE2 message ");
+			print_word(sie_msg);
+			sputs("!\n");
+		}
+
+	}
+	if (!int_handled)
+	{
+		sputs("Unhandled interrupt (status = ");
+		print_word(hpi_status);
+		sputs(")!\n");
+	}
+
+//	sputs("--------------------------------------------------------\n");
+	_g_int_active = 0;
+}
+
+// ---------------------------------------------------------
+// CY7C67300 low-level routines
+// ---------------------------------------------------------
+void cy67k3_reset(void)
+{
+	int i;
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_CTRL;
+
+	*pHpi = 3;
+	for (i=0; i <160; i++)
+	{
+		__asm __volatile
+		(
+			".set	noreorder\n"
+			"nop\n"
+			"nop\n"
+			"nop\n"
+			"nop\n"
+			".set	reorder\n"
+		);
+	}
+
+	*pHpi = 2;
+
+}
+
+UINT16 cy67k3_read_HPI_DATA(void)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_DATA;
+
+	return (UINT16)*pHpi;
+}
+
+UINT16 cy67k3_read_HPI_MAILBOX(void)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_MBX;
+
+	return (UINT16)*pHpi;
+}
+
+UINT16 cy67k3_read_HPI_ADDRESS(void)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_ADDR;
+
+	return (UINT16)*pHpi;
+}
+
+UINT16 cy67k3_read_HPI_STATUS(void)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_STATUS;
+
+	return (UINT16)*pHpi;
+}
+
+void cy67k3_write_HPI_DATA(UINT16 data)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_DATA;
+
+	*pHpi = (UINT32)data;
+}
+
+void cy67k3_write_HPI_MAILBOX(UINT16 data)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_MBX;
+
+	*pHpi = (UINT32)data;
+}
+
+void cy67k3_write_HPI_ADDRESS(UINT16 data)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_ADDR;
+
+	*pHpi = (UINT32)data;
+}
+
+void cy67k3_write_HPI_STATUS(UINT16 data)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_STATUS;
+
+	*pHpi = (UINT32)data;
+}
+
+// ---------------------------------------------------------
+// HPI API
+// ---------------------------------------------------------
+UINT32 hpi_init(void)
+{
+	volatile UINT32 *pHpi = (UINT32*)SYS_USB_CTRL;
+	int i;
+	UINT16 reg;
+
+	// ToDo: Enable HPI interrupt
+	_g_int_active = 0;
+
+	hpi_write_reg(HPI_REG_SIE1MSG, 0x0000);
+	hpi_write_reg(HPI_REG_SIE2MSG, 0x0000);
+	hpi_write_reg(SUSB1_REG_STATUS, 0xFFFF);
+	hpi_write_reg(SUSB2_REG_STATUS, 0xFFFF);
+
+	// Init 1
+	for(i=0; i < USB_MAX_NUM_EPT; i++)
+	{
+		hpi_write_reg(SUSB1_REG_EP_ADDR0 + 16*i, 0);
+		hpi_write_reg(SUSB1_REG_EP_CNTRES0 + 16*i, 0);
+		hpi_write_reg(SUSB1_REG_EP_COUNT0 + 16*i, 0);
+		hpi_write_reg(SUSB1_REG_EP_CTRL0 + 16*i, 0);
+		hpi_write_reg(SUSB1_REG_EP_STATUS0 + 16*i, 0);
+	}
+	// Init 2
+	for(i=0; i < USB_MAX_NUM_EPT; i++)
+	{
+		hpi_write_reg(SUSB2_REG_EP_ADDR0 + 16*i, 0);
+		hpi_write_reg(SUSB2_REG_EP_CNTRES0 + 16*i, 0);
+		hpi_write_reg(SUSB2_REG_EP_COUNT0 + 16*i, 0);
+		hpi_write_reg(SUSB2_REG_EP_CTRL0 + 16*i, 0);
+		hpi_write_reg(SUSB2_REG_EP_STATUS0 + 16*i, 0);
+	}
+
+	hpi_write_reg(HPI_REG_INTROUTE, 0x0000);
+	reg = hpi_read_reg(HPI_REG_INTROUTE);
+//	hpi_write_reg(HPI_REG_INTROUTE, reg | 0x0202);	// Route reset {1,2} to HPI only
+//	hpi_write_reg(HPI_REG_INTROUTE, reg | 0x2800);	// Route SOF/EOP {1,2} to HPI only
+//	hpi_write_reg(HPI_REG_INTROUTE, reg | 0x1400);	// Route SOF/EOP {1,2} to CY16 only
+	hpi_write_reg(HPI_REG_INTROUTE, reg | 0x3C00);	// Route SOF/EOP {1,2} to HPI and CY16
+
+
+	interrupt_register(4, cy67k3_isr);
+	interrupt_enable(4);
+	*pHpi = 0x02;
+
+	return HPI_NOERROR;
+}
+
+void hpi_mbx_write(UINT16 msgcode)
+{
+	_g_mbx_in_flag = 0;
+	cy67k3_write_HPI_MAILBOX(msgcode);
+}
+
+UINT32 hpi_mbx_read(void)
+{
+	UINT32 err;
+	UINT16 cy_return;
+
+	if (_g_int_active)
+	{
+		while (!(cy67k3_read_HPI_STATUS() & HPI_STATUS_MBX_IN));
+		cy_return = cy67k3_read_HPI_MAILBOX();
+	}
+	else
+	{
+		while(!_g_mbx_in_flag);
+		cy_return = _g_mbx_return;
+	}
+
+	switch (cy_return)
+	{
+		case COMM_ACK:
+			err = cy_return;
+		break;
+
+		case COMM_NAK:
+		case COMM_ASYNC:
+			err = HPI_ERR_PREFIX_MBX | cy_return;
+		break;
+
+		default:
+			err = HPI_ERR_PREFIX_MBX | cy_return;
+		break;
+	}
+	return err;
+}
+
+UINT32 hpi_check_addr(UINT16 addr)
+{
+	if ((addr >= 0x0000) && (addr < 0x4000))
+		return 0;
+
+	if ((addr >= 0xC080) && (addr < 0xC0BC))
+		return 0;
+
+	if (addr >= 0xE000)
+		return 0;
+
+	sputs("Invalid address for HPI direct access! Use LCP-command instead!\n");
+	return HPI_ERR_INVPARAM;
+}
+
+UINT32 hpi_read_reg(UINT16 addr)
+{
+	UINT32 result;
+
+	result = hpi_check_addr(addr);
+	if (IS_ERROR(result))
+		return result;
+
+	cy67k3_write_HPI_ADDRESS(addr);
+	return cy67k3_read_HPI_DATA();
+}
+
+UINT32 hpi_write_reg(UINT16 addr, UINT16 data)
+{
+	UINT32 result;
+
+	result = hpi_check_addr(addr);
+	if (IS_ERROR(result))
+		return result;
+
+	cy67k3_write_HPI_ADDRESS(addr);
+	cy67k3_write_HPI_DATA(data);
+}
+
+UINT32 hpi_write_ram(UINT16 addr, UINT16 *pData, UINT32 len)
+{
+	int i, num_words;
+
+	if (addr > 0x3FFE)
+		return HPI_ERR_INVPARAM;
+
+	if (addr & 1)				// Not 16bit aligned?
+		return HPI_ERR_INVPARAM;
+
+	cy67k3_write_HPI_ADDRESS(addr);
+
+	num_words = len/2;
+	if (len % 2)
+		num_words++;
+
+	for (i=0; i < num_words; i++)
+		cy67k3_write_HPI_DATA(pData[i]);
+
+	return len;
+}
+
+UINT32 hpi_read_ram(UINT16 addr, UINT16 *pData, UINT32 len)
+{
+	int i, num_words;
+
+	if (addr > 0x3FFE)
+		return HPI_ERR_INVPARAM;
+
+	if (addr & 1)				// Not 16bit aligned?
+		return HPI_ERR_INVPARAM;
+
+	cy67k3_write_HPI_ADDRESS(addr);
+
+	num_words = len/2;
+	if (len % 2)
+		num_words++;
+
+	for (i=0; i < num_words; i++)
+		pData[i] = cy67k3_read_HPI_DATA();
+
+	return len;
+}
+
+UINT32 hpi_comm_reset(void)
+{
+	hpi_mbx_write(COMM_RESET);
+
+	return hpi_mbx_read();
+}
+
+UINT32 hpi_comm_jump2code(UINT16 addr)
+{
+	cy67k3_write_HPI_ADDRESS(addr);
+	hpi_mbx_write(COMM_JUMP2CODE);
+
+	return hpi_mbx_read();
+}
+
+UINT32 hpi_comm_callcode(UINT16 addr)
+{
+	hpi_write_reg(COMM_CODE_ADDR, addr);
+
+	hpi_mbx_write(COMM_CALL_CODE);
+
+	return hpi_mbx_read();
+}
+
+UINT32 hpi_comm_write_ctrl_reg(UINT16 addr, UINT16 data, UINT16 logic)
+{
+
+	hpi_write_reg(COMM_CTRL_REG_ADDR, addr);
+	hpi_write_reg(COMM_CTRL_REG_DATA, data);
+	hpi_write_reg(COMM_CTRL_REG_LOGIC, logic);
+
+	hpi_mbx_write(COMM_WRITE_CTRL_REG);
+
+	return hpi_mbx_read();
+}
+
+UINT32 hpi_comm_read_ctrl_reg(UINT16 addr)
+{
+	UINT32 result;
+
+	hpi_write_reg(COMM_CTRL_REG_ADDR, addr);
+
+	hpi_mbx_write(COMM_READ_CTRL_REG);
+
+	result = hpi_mbx_read();
+	if (IS_ERROR(result))
+		return result;
+
+	cy67k3_write_HPI_ADDRESS(COMM_CTRL_REG_DATA);
+	return (UINT32)cy67k3_read_HPI_DATA();
+
+}
+
+UINT32 hpi_comm_write_xmem(UINT16 addr, UINT8 *pData, UINT16 len)
+{
+	return HPI_ERR_NOTIMPL;
+
+}
+
+UINT32 hpi_comm_read_xmem(UINT16 addr, UINT8 *pData, UINT16 len)
+{
+	return HPI_ERR_NOTIMPL;
+
+}
+
+typedef struct _sreg_param_t
+{
+	UINT32 id;
+	UINT16 val;
+
+} reg_param_t;
+
+UINT32 hpi_comm_exec_int(UINT16 intnum, UINT32 nargs, ...)
+{
+	int i;
+	UINT32 result;
+	va_list args;
+	reg_param_t reg_param[MAX_NUM_REGS];
+
+	va_start(args, nargs);
+
+	if (nargs > MAX_NUM_REGS)
+	{
+		fprintf(stderr, "hpi_comm_exec_int(): Number (%d), of arguments exceeds %d!\n", nargs, MAX_NUM_REGS);
+		return HPI_ERR_INVPARAM;
+	}
+
+	for (i=0; i < nargs; i++)
+	{
+		reg_param[i].id = va_arg(args, UINT32);
+		if (reg_param[i].id > MAX_NUM_REGS)
+		{
+			fprintf(stderr, "hpi_comm_exec_int(): Invalid register R%d!\n", reg_param[i].id);
+			return HPI_ERR_INVPARAM;
+		}
+
+		reg_param[i].val = (UINT16)va_arg(args, UINT32);
+	}
+	va_end(args);
+
+	hpi_write_reg(COMM_INT_NUM, intnum);
+
+	for (i=0; i < nargs; i++)
+	{
+		hpi_write_reg(COMM_R0 + 2*reg_param[i].id, reg_param[i].val);
+	}
+
+	hpi_mbx_write(COMM_EXEC_INT);
+
+	result = hpi_mbx_read();
+	if (IS_ERROR(result))
+		return result;
+
+	return (UINT32)hpi_read_reg(COMM_R0);
+}
+
+UINT32 usb_init(void)
+{
+	INT32 i;
+
+	for (i=0; i < USB_MAX_NUM_PORTS; i++)
+	{
+		memset(&_g_usb[i], 0, sizeof(usb_t));
+	}
+	return 0;
+}
+
+UINT32 usb_callback_register(UINT32 port, UINT32 type, fp_t pFunc, void *pArg)
+{
+	UINT32 result;
+	if (port >= USB_MAX_NUM_PORTS)
+		return -1;
+
+	result = 0;
+	switch (type)
+	{
+		case SUSB_EP0_MSG:
+		_g_usb[port].fptr_ept[0] = pFunc;
+		_g_usb[port].aptr_ept[0] = pArg;
+		break;
+
+		case SUSB_EP1_MSG:
+		_g_usb[port].fptr_ept[1] = pFunc;
+		_g_usb[port].aptr_ept[1] = pArg;
+		break;
+
+		case SUSB_EP2_MSG:
+		_g_usb[port].fptr_ept[2] = pFunc;
+		_g_usb[port].aptr_ept[2] = pArg;
+		break;
+
+		case SUSB_EP3_MSG:
+		_g_usb[port].fptr_ept[3] = pFunc;
+		_g_usb[port].aptr_ept[3] = pArg;
+		break;
+
+		case SUSB_EP4_MSG:
+		_g_usb[port].fptr_ept[4] = pFunc;
+		_g_usb[port].aptr_ept[4] = pArg;
+		break;
+
+		case SUSB_EP5_MSG:
+		_g_usb[port].fptr_ept[5] = pFunc;
+		_g_usb[port].aptr_ept[5] = pArg;
+		break;
+
+		case SUSB_EP6_MSG:
+		_g_usb[port].fptr_ept[6] = pFunc;
+		_g_usb[port].aptr_ept[6] = pArg;
+		break;
+
+		case SUSB_EP7_MSG:
+		_g_usb[port].fptr_ept[7] = pFunc;
+		_g_usb[port].aptr_ept[7] = pArg;
+		break;
+
+		case SUSB_RST_MSG:
+		_g_usb[port].fptr_rst = pFunc;
+		_g_usb[port].aptr_rst = pArg;
+		break;
+
+		case SUSB_SOF_MSG:
+		_g_usb[port].fptr_sof = pFunc;
+		_g_usb[port].aptr_sof = pArg;
+		break;
+
+		case SUSB_CFG_MSG:
+		_g_usb[port].fptr_cfg = pFunc;
+		_g_usb[port].aptr_cfg = pArg;
+		break;
+
+		case SUSB_SUS_MSG:
+		_g_usb[port].fptr_sus = pFunc;
+		_g_usb[port].aptr_sus = pArg;
+		break;
+
+		case SUSB_ID_MSG:
+		_g_usb[port].fptr_id = pFunc;
+		_g_usb[port].aptr_id = pArg;
+		break;
+
+		case SUSB_VBUS_MSG:
+		_g_usb[port].fptr_vbus = pFunc;
+		_g_usb[port].aptr_vbus = pArg;
+		break;
+
+		default:
+		result = -1;
+		break;
+	}
+
+	return result;
+}
+
+UINT32 usb_irp_register(usb_irp_t *pIRP, UINT32 port, UINT32 ept, UINT32 size, UINT32 is_out)
+{
+
+	if (!pIRP)
+		return -1;
+
+	if (port >= USB_MAX_NUM_PORTS)
+		return -1;
+
+	if (ept >= USB_MAX_NUM_EPT)
+		return -1;
+
+	if (size >= USB_MAX_IMG_SIZE)
+		return -1;
+
+	memset(pIRP, 0, sizeof(usb_irp_t));
+	pIRP->is_out = is_out;
+	pIRP->is_in = !is_out;
+	pIRP->tsize = size;
+	pIRP->port = port;
+	pIRP->ept = ept;
+	pIRP->cy_irp_addr = USB_IRP_BASE + port*USB_MAX_NUM_EPT*sizeof(cy_req_t) + ept*sizeof(cy_req_t);
+	pIRP->cy_req.next = 0;
+	pIRP->cy_req.addr = USB_IMG_BASE + port*USB_MAX_NUM_EPT*USB_MAX_IMG_SIZE + ept*USB_MAX_IMG_SIZE;
+	pIRP->cy_req.size = size;
+	pIRP->cy_req.callback = 0;
+	fifo_alloc(&pIRP->fifo, 8*USB_MAX_IMG_SIZE);
+
+	return 0;
+}
+
+UINT32 usb_irp_enqueue(usb_irp_t *pIRP)
+{
+	UINT32 result;
+
+	if (!pIRP)
+	{
+//		sputs ("usb_irp_enqueue(): Invalid IRP!\n");
+		return -1;
+	}
+
+//	printf("cy_addr: %4.4X, Next: %4.4X, Addr: %4.4X, Size: %4.4X, CB: %4.4X\n", pIRP->cy_irp_addr, pIRP->cy_req.next, pIRP->cy_req.addr, pIRP->cy_req.size, pIRP->cy_req.callback);
+
+	if (pIRP->is_out)
+	{
+		hpi_write_ram(pIRP->cy_irp_addr, (UINT16*)&pIRP->cy_req, sizeof(cy_req_t));
+		if (pIRP->port == 0)
+			result = hpi_comm_exec_int(SUSB1_RECEIVE_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr);
+
+		if (pIRP->port == 1)
+			result = hpi_comm_exec_int(SUSB2_RECEIVE_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr);
+	}
+	if (pIRP->is_in)
+	{
+		pIRP->tx_in_progress = 1;
+		hpi_write_ram(pIRP->cy_irp_addr, (UINT16*)&pIRP->cy_req, sizeof(cy_req_t));
+		if (pIRP->port == 0)
+			result = hpi_comm_exec_int(SUSB1_SEND_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr);
+
+		if (pIRP->port == 1)
+			result = hpi_comm_exec_int(SUSB2_SEND_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr);
+	}
+
+//	if (result)
+//		printf ("usb_irp_enqueue(): Result = %8.8X\n", result);
+
+	return result;
+
+}
+
+UINT32 fifo_alloc(fifo_t *pObj, UINT32 size)
+{
+	pObj->pBuf = (UINT8*)malloc(size);
+	if (!pObj->pBuf)
+	{
+//		printf ("fifo_alloc(): Error allocating memory!\n");
+		return -1;
+	}
+//	printf ("fifo_alloc(): pBuf at %8.8X\n", (UINT32)pObj->pBuf);
+	pObj->size = size;
+	pObj->pPtr_wr = pObj->pBuf;
+	pObj->pPtr_rd = pObj->pBuf;
+
+	return 0;
+}
+
+UINT32 fifo_free(fifo_t *pObj)
+{
+	if (pObj->pBuf)
+		free(pObj->pBuf);
+
+	return 0;
+}
+
+UINT32 fifo_flush(fifo_t *pObj)
+{
+	pObj->pPtr_wr = pObj->pBuf;
+	pObj->pPtr_rd = pObj->pBuf;
+
+	return 0;
+}
+
+UINT32 fifo_is_empty(fifo_t *pObj)
+{
+	return (pObj->pPtr_wr == pObj->pPtr_rd);
+}
+
+UINT32 fifo_is_full(fifo_t *pObj)
+{
+	UINT8 *pNext, *pEnd;
+
+	pEnd = pObj->pBuf + pObj->size;
+	pNext = pObj->pPtr_wr + 1;
+	if (pNext == pEnd)
+		pNext = pObj->pBuf;
+
+	return (pNext == pObj->pPtr_rd);
+}
+
+UINT32 fifo_read(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block)
+{
+	UINT32 i;
+	UINT32 wait_4ever, timeout_cnt, cnt;
+	UINT8 *pEnd;
+
+	pEnd = pObj->pBuf + pObj->size;
+	wait_4ever = (timeout == 0);
+
+	cnt = 0;
+	while(size)
+	{
+		timeout_cnt = timeout;
+
+		while(fifo_is_empty(pObj))
+		{
+			if (!do_block)
+				return cnt;
+
+			if (!wait_4ever)
+			{
+				if (timeout_cnt)
+				{
+					timeout_cnt--;
+					sleep(1);
+				}
+				else
+				{
+					return cnt;
+				}
+			}
+		}
+
+		if (pData)
+			pData[cnt] = *(pObj->pPtr_rd);
+
+		cnt++;
+		pObj->pPtr_rd++;
+		if (pObj->pPtr_rd == pEnd)
+			pObj->pPtr_rd = pObj->pBuf;
+
+		size--;
+	}
+
+	return cnt;
+}
+
+UINT32 fifo_write(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block)
+{
+	UINT32 wait_4ever, timeout_cnt, cnt;
+	UINT8 *pEnd;
+
+	pEnd = pObj->pBuf + pObj->size;
+	wait_4ever = (timeout == 0);
+
+	cnt = 0;
+	while(size)
+	{
+		timeout_cnt = timeout;
+
+		while(fifo_is_full(pObj))
+		{
+			if (!do_block)
+				return cnt;
+
+			if (!wait_4ever)
+			{
+				if (timeout_cnt)
+				{
+					timeout_cnt--;
+					sleep(1);
+				}
+				else
+				{
+					return cnt;
+				}
+			}
+		}
+
+		if (pData)
+			*(pObj->pPtr_wr) = pData[cnt];
+
+		cnt++;
+		pObj->pPtr_wr++;
+		if (pObj->pPtr_wr == pEnd)
+			pObj->pPtr_wr = pObj->pBuf;
+
+		size--;
+	}
+
+	return cnt;
+}
+
+// ---------------------------------------------------------

lib/CPUs/MIPS/bsp/examples/hpi.h

@@ -0,0 +1,384 @@
+#ifndef HPI_H
+#define HPI_H
+
+// ---------------------------------------------------------
+// API related
+// ---------------------------------------------------------
+//#define	IS_ERROR(e)			(0 != (e & HPI_ERROR))
+#define	HPI_NOERROR			0
+#define	HPI_ERROR			0x80000000
+#define	HPI_ERR_NOTIMPL		(HPI_ERROR + 1)
+#define	HPI_ERR_INVPARAM	(HPI_ERROR + 2)
+#define	HPI_ERR_TIMEOUT		(HPI_ERROR + 3)
+#define	HPI_ERR_PREFIX_MBX	(HPI_ERROR + 0x00010000)
+
+#define	MAX_NUM_REGS		14
+#define R0					0
+#define R1					1
+#define R2					2
+#define R3					3
+#define R4					4
+#define R5					5
+#define R6					6
+#define R7					7
+#define R8					8
+#define R9					9
+#define R10					10
+#define R11					11
+#define R12					12
+#define R13					13
+
+#define USB_MAX_NUM_PORTS	2
+#define USB_MAX_NUM_EPT		8
+#define USB_MAX_IMG_SIZE	512
+#define USB_IRP_BASE		0x0F80
+#define USB_IMG_BASE		0x1000
+
+typedef void (*fp_t)(void*);
+
+// Receive buffer on EP
+typedef struct _scy_req_t
+{
+	UINT16 next;
+	UINT16 addr;
+	UINT16 size;
+	UINT16 callback;
+} cy_req_t;
+
+typedef struct _sfifo_t
+{
+	UINT32 size;
+	UINT8 *pBuf;
+	UINT8 * volatile pPtr_wr, * volatile pPtr_rd;
+
+} fifo_t;
+
+typedef struct _susb_irp_t
+{
+	UINT16 tsize;
+	UINT32 is_in, is_out;
+	UINT32 port, ept;
+	UINT16 cy_irp_addr;
+	fifo_t fifo;
+	UINT32 tx_in_progress;
+	cy_req_t cy_req;
+} usb_irp_t;
+
+// ---------------------------------------------------------
+// CY7C67300 related
+// ---------------------------------------------------------
+#define	HPI_WAITACK			1
+#define	HPI_NOWAIT			0
+
+// ---------------------------------------------------------
+// HPI status flags
+#define	HPI_STATUS_MBX_IN	0x0001
+#define	HPI_STATUS_RESET1	0x0002
+#define	HPI_STATUS_DONE1	0x0004
+#define	HPI_STATUS_DONE2	0x0008
+#define	HPI_STATUS_SIEMSG1	0x0010
+#define	HPI_STATUS_SIEMSG2	0x0020
+#define	HPI_STATUS_RESUME1	0x0040
+#define	HPI_STATUS_RESUME2	0x0080
+#define	HPI_STATUS_MBX_OUT	0x0100
+#define	HPI_STATUS_RESET2	0x0200
+#define	HPI_STATUS_SOFEOP1	0x0400
+#define	HPI_STATUS_SOFEOP2	0x1000
+#define	HPI_STATUS_ID		0x4000
+#define	HPI_STATUS_VBUS		0x8000
+
+// ---------------------------------------------------------
+// LCP command codes
+#define COMM_RESET			0xFA50
+#define COMM_JUMP2CODE		0xCE00
+#define COMM_EXEC_INT		0xCE01
+#define COMM_READ_CTRL_REG	0xCE02
+#define COMM_WRITE_CTRL_REG	0xCE03
+#define COMM_CALL_CODE		0xCE04
+#define COMM_READ_XMEM		0xCE05
+#define COMM_WRITE_XMEM		0xCE06
+#define C0MM_CONFIG			0xCE07
+#define COMM_READ_MEM		0xCE08
+#define COMM_WRITE_MEM		0xCE09
+// LCP response codes
+#define COMM_ACK			0x0FED
+#define COMM_NAK			0xDEAD
+#define COMM_ASYNC			0xF00D
+
+// ---------------------------------------------------------
+// LCP memory addresses
+#define COMM_PORT_CMD		0x01BA	// For PORT Command
+#define COMM_MEM_ADDR		0x01BC	// Address for COMM_RD/WR_MEM
+#define COMM_MEM_LEN		0x01BE	// Address for COMM_RD/WR_MEM
+#define COMM_LAST_DATA		0x01C0	// memory pointer for xmem
+#define COMM_CTRL_REG_ADDR	0x01BC	// Address for COMM_RD/WR_CTRL_REG
+#define COMM_CTRL_REG_DATA	0x01BE	// Address for COMM_RD/WR_CTRL_REG
+#define COMM_CTRL_REG_LOGIC	0x01C0	// Address used for AND/OR
+#define REG_WRITE_FLG		0x0000	// Value for COMM_CTRL_REG_LOGIC
+#define REG_AND_FLG			0x0001	// Value for COMM_CTRL_REG_LOGIC
+#define REG_OR_FLG			0x0002	// Value for COMM_CTRL_REG_LOGIC
+#define COMM_TIMEOUT		0x01BE	// Address setting Timeout for sending response to host
+#define COMM_CODE_ADDR		0x01BC	// Address for COMM_CALL_CODE and COMM_JUMP2CODE
+#define COMM_INT_NUM		0x01C2	// Address used for COMM_EXEC_INT
+#define COMM_R0				0x01C4	// CY16-R0 register
+#define COMM_R1				0x01C6	// CY16-R1 register
+#define COMM_R2				0x01C8	// CY16-R2 register
+#define COMM_R3				0x01CA	// CY16-R3 register
+#define COMM_R4				0x01CC	// CY16-R4 register
+#define COMM_R5				0x01CE	// CY16-R5 register
+#define COMM_R6				0x01D0	// CY16-R6 register
+#define COMM_R7				0x01D2	// CY16-R7 register
+#define COMM_R8				0x01D4	// CY16-R8 register
+#define COMM_R9				0x01D6	// CY16-R9 register
+#define COMM_R10			0x01D8	// CY16-R10 register
+#define COMM_R11			0x01DA	// CY16-R11 register
+#define COMM_R12			0x01DC	// CY16-R12 register
+#define COMM_R13			0x01DE	// CY16-R13 register
+
+// for COMM_CTRL_REG_LOGIC
+#define	LOGIC_DIRECT		0
+#define	LOGIC_AND			1
+#define	LOGIC_OR			2
+
+// ---------------------------------------------------------
+// Software interrupts
+#define	SUSB_INIT_INT							113
+// USB 1
+#define	SUSB1_DEVICE_DESCRIPTOR_VEC				90
+#define	SUSB1_CONFIGURATION_DESCRIPTOR_VEC		91
+#define	SUSB1_STRING_DESCRIPTOR_VEC				92
+#define	SUSB1_FINISH_INT						89
+#define	SUSB1_STALL_INT							82
+#define	SUSB1_STANDARD_INT						83
+#define	SUSB1_SEND_INT							80
+#define	SUSB1_RECEIVE_INT						81
+#define	SUSB1_VENDOR_INT						85
+#define	SUSB1_CLASS_INT							87
+#define	SUSB1_LOADER_INT						94
+#define	SUSB1_DELTA_CONFIG_INT					95
+
+// USB 2
+#define	SUSB2_DEVICE_DESCRIPTOR_VEC				106
+#define	SUSB2_CONFIGURATION_DESCRIPTOR_VEC		107
+#define	SUSB2_STRING_DESCRIPTOR_VEC				108
+#define	SUSB2_FINISH_INT						105
+#define	SUSB2_STALL_INT							98
+#define	SUSB2_STANDARD_INT						99
+#define	SUSB2_SEND_INT							96
+#define	SUSB2_RECEIVE_INT						97
+#define	SUSB2_VENDOR_INT						101
+#define	SUSB2_CLASS_INT							103
+#define	SUSB2_LOADER_INT						110
+#define	SUSB2_DELTA_CONFIG_INT					111
+
+// ---------------------------------------------------------
+// General USB Registers
+#define	USB_REG_FLAGS							0xC000	// CPU Flags
+#define	USB_REG_BANK							0xC002	// Register Bank
+#define	USB_REG_REVISON							0xC004	// Hardware Revision
+#define	USB_REG_SPEED							0xC008	// CPU Speed
+#define	USB_REG_PWRCTRL							0xC00A	// Power Control
+#define	USB_REG_INTEN							0xC00E	// Interrupt Enable
+#define	USB_REG_BP								0xC014	// Breakpoint
+#define	USB_REG_USBDIAG							0xC03C	// USB Diagnostic
+#define	USB_REG_MEMDIAG							0xC03E	// Memory Diagnostic
+
+// HPI registers
+#define	HPI_REG_BP								0x0140	// HPI Breakpoint
+#define	HPI_REG_INTROUTE						0x0142	// Interrupt Routing
+#define	HPI_REG_SIE1MSG							0x0144	// SIE1msg
+#define	HPI_REG_SIE2MSG							0x0148	// SIE2msg
+#define	HPI_REG_MAILBOX							0xC0C6	// HPI Mailbox
+
+// ---------------------------------------------------------
+// General Device Registers
+// Device 1
+#define	SUSB1_REG_PORTSEL						0xC084	// Port select
+#define	SUSB1_REG_USBCTRL						0xC08A	// USB control
+#define	SUSB1_REG_INTEN							0xC08C	// Interrupt enable
+#define	SUSB1_REG_ADDR							0xC08E	// Address
+#define	SUSB1_REG_STATUS						0xC090	// Status
+#define	SUSB1_REG_FRAMENUM						0xC092	// Frame number
+#define	SUSB1_REG_SOFEOPCNT						0xC094	// SOF/EOP count
+
+// Device 2
+#define	SUSB2_REG_PORTSEL						0xC0A4	// Port select
+#define	SUSB2_REG_USBCTRL						0xC0AA	// USB control
+#define	SUSB2_REG_INTEN							0xC0AC	// Interrupt enable
+#define	SUSB2_REG_ADDR							0xC0AE	// Address
+#define	SUSB2_REG_STATUS						0xC0B0	// Status
+#define	SUSB2_REG_FRAMENUM						0xC0B2	// Frame number
+#define	SUSB2_REG_SOFEOPCNT						0xC0B4	// SOF/EOP count
+
+// ---------------------------------------------------------
+// Endpoint Registers
+// Device 1 Control
+#define	SUSB1_REG_EP_CTRL0						0x0200
+#define	SUSB1_REG_EP_CTRL1						0x0210
+#define	SUSB1_REG_EP_CTRL2						0x0220
+#define	SUSB1_REG_EP_CTRL3						0x0230
+#define	SUSB1_REG_EP_CTRL4						0x0240
+#define	SUSB1_REG_EP_CTRL5						0x0250
+#define	SUSB1_REG_EP_CTRL6						0x0260
+#define	SUSB1_REG_EP_CTRL7						0x0270
+// Device 1 Address
+#define	SUSB1_REG_EP_ADDR0						0x0202
+#define	SUSB1_REG_EP_ADDR1						0x0212
+#define	SUSB1_REG_EP_ADDR2						0x0222
+#define	SUSB1_REG_EP_ADDR3						0x0232
+#define	SUSB1_REG_EP_ADDR4						0x0242
+#define	SUSB1_REG_EP_ADDR5						0x0252
+#define	SUSB1_REG_EP_ADDR6						0x0262
+#define	SUSB1_REG_EP_ADDR7						0x0272
+// Device 1 Count
+#define	SUSB1_REG_EP_COUNT0						0x0204
+#define	SUSB1_REG_EP_COUNT1						0x0214
+#define	SUSB1_REG_EP_COUNT2						0x0224
+#define	SUSB1_REG_EP_COUNT3						0x0234
+#define	SUSB1_REG_EP_COUNT4						0x0244
+#define	SUSB1_REG_EP_COUNT5						0x0254
+#define	SUSB1_REG_EP_COUNT6						0x0264
+#define	SUSB1_REG_EP_COUNT7						0x0274
+// Device 1 Status
+#define	SUSB1_REG_EP_STATUS0					0x0206
+#define	SUSB1_REG_EP_STATUS1					0x0216
+#define	SUSB1_REG_EP_STATUS2					0x0226
+#define	SUSB1_REG_EP_STATUS3					0x0236
+#define	SUSB1_REG_EP_STATUS4					0x0246
+#define	SUSB1_REG_EP_STATUS5					0x0256
+#define	SUSB1_REG_EP_STATUS6					0x0266
+#define	SUSB1_REG_EP_STATUS7					0x0276
+// Device 1 Count result
+#define	SUSB1_REG_EP_CNTRES0					0x0208
+#define	SUSB1_REG_EP_CNTRES1					0x0218
+#define	SUSB1_REG_EP_CNTRES2					0x0228
+#define	SUSB1_REG_EP_CNTRES3					0x0238
+#define	SUSB1_REG_EP_CNTRES4					0x0248
+#define	SUSB1_REG_EP_CNTRES5					0x0258
+#define	SUSB1_REG_EP_CNTRES6					0x0268
+#define	SUSB1_REG_EP_CNTRES7					0x0278
+
+// Device 2 Control
+#define	SUSB2_REG_EP_CTRL0						0x0280
+#define	SUSB2_REG_EP_CTRL1						0x0290
+#define	SUSB2_REG_EP_CTRL2						0x02A0
+#define	SUSB2_REG_EP_CTRL3						0x02B0
+#define	SUSB2_REG_EP_CTRL4						0x02C0
+#define	SUSB2_REG_EP_CTRL5						0x02D0
+#define	SUSB2_REG_EP_CTRL6						0x02E0
+#define	SUSB2_REG_EP_CTRL7						0x02F0
+// Device 2 Address
+#define	SUSB2_REG_EP_ADDR0						0x0282
+#define	SUSB2_REG_EP_ADDR1						0x0292
+#define	SUSB2_REG_EP_ADDR2						0x02A2
+#define	SUSB2_REG_EP_ADDR3						0x02B2
+#define	SUSB2_REG_EP_ADDR4						0x02C2
+#define	SUSB2_REG_EP_ADDR5						0x02D2
+#define	SUSB2_REG_EP_ADDR6						0x02E2
+#define	SUSB2_REG_EP_ADDR7						0x02F2
+// Device 2 Count
+#define	SUSB2_REG_EP_COUNT0						0x0284
+#define	SUSB2_REG_EP_COUNT1						0x0294
+#define	SUSB2_REG_EP_COUNT2						0x02A4
+#define	SUSB2_REG_EP_COUNT3						0x02B4
+#define	SUSB2_REG_EP_COUNT4						0x02C4
+#define	SUSB2_REG_EP_COUNT5						0x02D4
+#define	SUSB2_REG_EP_COUNT6						0x02E4
+#define	SUSB2_REG_EP_COUNT7						0x02F4
+// Device 2 Status
+#define	SUSB2_REG_EP_STATUS0					0x0286
+#define	SUSB2_REG_EP_STATUS1					0x0296
+#define	SUSB2_REG_EP_STATUS2					0x02A6
+#define	SUSB2_REG_EP_STATUS3					0x02B6
+#define	SUSB2_REG_EP_STATUS4					0x02C6
+#define	SUSB2_REG_EP_STATUS5					0x02D6
+#define	SUSB2_REG_EP_STATUS6					0x02E6
+#define	SUSB2_REG_EP_STATUS7					0x02F6
+// Device 2 Count result
+#define	SUSB2_REG_EP_CNTRES0					0x0288
+#define	SUSB2_REG_EP_CNTRES1					0x0298
+#define	SUSB2_REG_EP_CNTRES2					0x02A8
+#define	SUSB2_REG_EP_CNTRES3					0x02B8
+#define	SUSB2_REG_EP_CNTRES4					0x02C8
+#define	SUSB2_REG_EP_CNTRES5					0x02D8
+#define	SUSB2_REG_EP_CNTRES6					0x02E8
+#define	SUSB2_REG_EP_CNTRES7					0x02F8
+
+// ---------------------------------------------------------
+// others
+#define HUSB_TDLISTDONE		0x1000
+#define HUSB_SOF			0x2000
+#define HUSB_ARMV			0x0001
+#define HUSB_AINS_FS		0x0002
+#define HUSB_AINS_LS		0x0004
+#define HUSB_AWAKEUP		0x0008
+#define HUSB_BRMV			0x0010
+#define HUSB_BINS_FS		0x0020
+#define HUSB_BINS_LS		0x0040
+#define HUSB_BWAKEUP		0x0080
+
+#define SUSB_EP0_MSG		0x0001
+#define SUSB_EP1_MSG		0x0002
+#define SUSB_EP2_MSG		0x0004
+#define SUSB_EP3_MSG		0x0008
+#define SUSB_EP4_MSG		0x0010
+#define SUSB_EP5_MSG		0x0020
+#define SUSB_EP6_MSG		0x0040
+#define SUSB_EP7_MSG		0x0080
+#define SUSB_RST_MSG		0x0100
+#define SUSB_SOF_MSG		0x0200
+#define SUSB_CFG_MSG		0x0400
+#define SUSB_SUS_MSG		0x0800
+#define SUSB_ID_MSG			0x4000
+#define SUSB_VBUS_MSG		0x8000
+
+// ---------------------------------------------------------
+// Functions
+// ---------------------------------------------------------
+
+// HPI low-level routines
+void cy67k3_isr(void);
+void cy67k3_reset(void);
+UINT16 cy67k3_read_HPI_DATA(void);
+UINT16 cy67k3_read_HPI_MAILBOX(void);
+UINT16 cy67k3_read_HPI_ADDRESS(void);
+UINT16 cy67k3_read_HPI_STATUS(void);
+void cy67k3_write_HPI_DATA(UINT16 data);
+void cy67k3_write_HPI_MAILBOX(UINT16 data);
+void cy67k3_write_HPI_ADDRESS(UINT16 data);
+void cy67k3_write_HPI_STATUS(UINT16 data);
+
+// HPI API
+UINT32 hpi_init(void);
+void hpi_mbx_write(UINT16 msgcode);
+UINT32 hpi_mbx_read(void);
+UINT32 hpi_read_reg(UINT16 addr);
+UINT32 hpi_write_reg(UINT16 addr, UINT16 data);
+UINT32 hpi_write_ram(UINT16 addr, UINT16 *pData, UINT32 num_words);
+UINT32 hpi_read_ram(UINT16 addr, UINT16 *pData, UINT32 num_words);
+UINT32 hpi_comm_reset(void);
+UINT32 hpi_comm_jump2code(UINT16 addr);
+UINT32 hpi_comm_callcode(UINT16 addr);
+UINT32 hpi_comm_write_ctrl_reg(UINT16 addr, UINT16 data, UINT16 logic);
+UINT32 hpi_comm_read_ctrl_reg(UINT16 addr);
+UINT32 hpi_comm_write_xmem(UINT16 addr, UINT8 *pData, UINT16 len);
+UINT32 hpi_comm_read_xmem(UINT16 addr, UINT8 *pData, UINT16 len);
+UINT32 hpi_comm_exec_int(UINT16 intnum, UINT32 nargs, ...);
+
+// USB API
+UINT32 usb_init(void);
+UINT32 usb_irp_register(usb_irp_t *pIRP, UINT32 port, UINT32 ept, UINT32 size, UINT32 is_out);
+UINT32 usb_irp_enqueue(usb_irp_t *pIRP);
+UINT32 usb_callback_register(UINT32 port, UINT32 type, fp_t pFunc, void *pArg);
+
+#define	FIFO_BLOCK		1
+#define	FIFO_NONBLOCK	0
+UINT32 fifo_alloc(fifo_t *pObj, UINT32 size);
+UINT32 fifo_free(fifo_t *pObj);
+UINT32 fifo_flush(fifo_t *pObj);
+UINT32 fifo_is_full(fifo_t *pObj);
+UINT32 fifo_is_empty(fifo_t *pObj);
+UINT32 fifo_read(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block);
+UINT32 fifo_write(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block);
+
+#endif // HPI_H