jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- change instructionamesfor nop and illegal

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@997 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-10 17:24:44 +00:00
parent dcea9c36b7
commit ae123fadc7
3 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_instr.vhd
+1 -1
View File
@@ -157,7 +157,7 @@ package body mips_instr is
rt := to_integer(extract_rt(instr));
rs := to_integer(extract_rs(instr));
result := reserved;
result := op_illegal;
case opc is
lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+6 -6
View File
@@ -485,7 +485,7 @@ proc_stage_ID_EX_1:
begin
if rising_edge(clk_1) then
if stage_rst(1) = '1' then
EX_stage.op <= NOP;
EX_stage.op <= op_nop;
EX_stage.IR <= (others => '0');
EX_stage.ctrl <= ctrl_lines_default;
EX_stage.reg_write <= '0';
@@ -504,7 +504,7 @@ proc_stage_ID_EX_1:
EX_stage.pcn <= ID_stage.pcn;
EX_stage.epc <= ID_stage.epc;
if sdu.EX_nop = '1' then
EX_stage.op <= NOP;
EX_stage.op <= op_nop;
EX_stage.IR <= (others => '0');
EX_stage.ctrl <= ctrl_lines_default;
EX_stage.reg_write <= '0';
@@ -744,7 +744,7 @@ proc_stage_MEM_n:
begin
if rising_edge(clk_1) then
if stage_rst(2) = '1' then
MEM_stage.op <= NOP;
MEM_stage.op <= op_nop;
MEM_stage.wreg_we <= '0';
MEM_stage.ctrl <= ctrl_lines_default;
MEM_stage.pa_off <= (others => '0');
@@ -775,7 +775,7 @@ proc_stage_MEM_n:
MEM_stage.ex_result <= EX_stage.result;
end if;
if sdu.MEM_nop = '1' then
MEM_stage.op <= NOP;
MEM_stage.op <= op_nop;
MEM_stage.wreg_we <= '0';
MEM_stage.ctrl <= ctrl_lines_default;
else
@@ -835,7 +835,7 @@ proc_stage_WB_p:
begin
if rising_edge(clk_1) then
if stage_rst(3) = '1' then
WB_stage.op <= NOP;
WB_stage.op <= op_nop;
WB_stage.wreg_we <= '1';
WB_stage.reg_wptr <= (others => '0');
WB_stage.data <= (others => '0');
@@ -854,7 +854,7 @@ proc_stage_WB_p:
end if;
WB_stage.nop <= sdu.WB_nop;
if sdu.WB_nop = '1' then
WB_stage.op <= NOP;
WB_stage.op <= op_nop;
WB_stage.wreg_we <= '0';
else
WB_stage.bd <= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works
lib/CPUs/MIPS/src/core/mips_types.vhd
+2 -2
View File
@@ -45,8 +45,8 @@ package mips_types is
type op_t is
(
reserved,
nop,
op_illegal,
op_nop,
op_sll,
op_srl,
op_sra,