Initial revision
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@969 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,19 @@
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## NOTE: Do not edit this file.
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## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
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##
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vlib work
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vcom -explicit -93 "../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
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||||
vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
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||||
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
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||||
vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd"
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vcom -explicit -93 "../src/busmaster_sync.vhd"
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vcom -explicit -93 "../src/tb_busmaster_sync.vhd"
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vsim -t 1ps -lib work tb_busmaster_sync
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view wave
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do {tb_busmaster_sync.wdo}
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view structure
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view signals
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run 20us
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@@ -0,0 +1,61 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/clk
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/rst
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/read_reg
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||||
add wave -noupdate -format Literal /tb_busmaster_sync/state
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||||
add wave -noupdate -divider J-BUS
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/ack_i
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/mdat_i
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/mdat_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/addr_o
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||||
add wave -noupdate -format Literal /tb_busmaster_sync/inst_busmaster_sync/sel_o
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/we_o
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cyc_o
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/stb_o
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/mrdy_o
|
||||
add wave -noupdate -divider Busmaster
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cycle_busy
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||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_cycle_finished
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_cycle_en
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_rdy
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/cmd_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/cmd_addr
|
||||
add wave -noupdate -format Literal /tb_busmaster_sync/inst_busmaster_sync/cmd_sel
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_rw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/cmd_dout
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_dout_vld
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_dout_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_re
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_we
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_full
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busout_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busin_fifo_re
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busin_fifo_we
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busin_fifo_full
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/busin_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_en
|
||||
add wave -noupdate -format Logic /tb_busmaster_sync/inst_busmaster_sync/cmd_read_en
|
||||
add wave -noupdate -format Literal /tb_busmaster_sync/inst_busmaster_sync/read_cnt
|
||||
add wave -noupdate -divider RAM
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_sync/ram64
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {19057675 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
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||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
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||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
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||||
configure wave -timeline 0
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||||
update
|
||||
WaveRestoreZoom {0 ps} {21 us}
|
||||
@@ -0,0 +1,169 @@
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||||
-----------------------------------------------------------------------
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||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.1 2013-05-25 16:55:29 jens Exp $
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||||
-----------------------------------------------------------------------
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||||
library IEEE;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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||||
use IEEE.NUMERIC_STD.ALL;
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||||
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||||
use work.utils_pkg.all;
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||||
|
||||
------------------------------------------------------------------
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entity busmaster_sync is
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||||
Generic
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||||
(
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||||
DATA_WIDTH : natural := 32;
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FIFO_DEPTH : natural := 4
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||||
);
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||||
Port
|
||||
(
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||||
clk : in std_logic;
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||||
rst : in std_logic;
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||||
|
||||
cmd_cycle_finished : out std_logic;
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||||
cmd_cycle_en : in std_logic;
|
||||
cmd_rdy : out std_logic;
|
||||
cmd_we : in std_logic;
|
||||
cmd_din : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
cmd_addr : in unsigned(31 downto 0);
|
||||
cmd_sel : in unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
cmd_rw : in std_logic;
|
||||
|
||||
cmd_dout : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
cmd_dout_vld : out std_logic;
|
||||
cmd_dout_re : in std_logic;
|
||||
|
||||
-- J-BUS signals
|
||||
ACK_I : in std_logic;
|
||||
SRDY_I : in std_logic;
|
||||
MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
|
||||
MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
|
||||
WE_O : out std_logic;
|
||||
CYC_O : out std_logic;
|
||||
STB_O : out std_logic;
|
||||
MRDY_O : out std_logic
|
||||
);
|
||||
end busmaster_sync;
|
||||
|
||||
architecture Behavioral of busmaster_sync is
|
||||
|
||||
-- Bus output FIFO
|
||||
signal busout_fifo_din : unsigned(DATA_WIDTH+32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal busout_fifo_dout : unsigned(DATA_WIDTH+32+DATA_WIDTH/8+1-1 downto 0);
|
||||
signal busout_fifo_re : std_logic;
|
||||
signal busout_fifo_we : std_logic;
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||||
signal busout_fifo_full : std_logic;
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||||
signal busout_fifo_empty : std_logic;
|
||||
|
||||
-- Bus input FIFO
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||||
signal busin_fifo_re : std_logic;
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||||
signal busin_fifo_we : std_logic;
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||||
signal busin_fifo_full : std_logic;
|
||||
signal busin_fifo_empty : std_logic;
|
||||
signal cycle_busy : std_logic;
|
||||
signal cmd_en : std_logic;
|
||||
signal cmd_read_en : std_logic;
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||||
signal read_cnt : integer range 0 to 65535;
|
||||
|
||||
begin
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||||
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||||
cmd_en <= cmd_cycle_en and cmd_we and not busout_fifo_full;
|
||||
cmd_read_en <= cmd_en and not cmd_rw;
|
||||
|
||||
cmd_dout_vld <= not busin_fifo_empty;
|
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MRDY_O <= not busin_fifo_full;
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||||
busin_fifo_we <= ACK_I and cycle_busy;
|
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busin_fifo_re <= cmd_dout_re;
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ADDR_O <= busout_fifo_dout(31 downto 0);
|
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MDAT_O <= busout_fifo_dout(DATA_WIDTH+32-1 downto 32);
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SEL_O <= busout_fifo_dout(DATA_WIDTH+32+DATA_WIDTH/8-1 downto DATA_WIDTH+32);
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WE_O <= busout_fifo_dout(DATA_WIDTH+32+DATA_WIDTH/8);
|
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|
||||
busout_fifo_din <= cmd_rw & cmd_sel & cmd_din & cmd_addr;
|
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|
||||
cmd_rdy <= not busout_fifo_full;
|
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|
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busout_fifo_we <= cmd_en;
|
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busout_fifo_re <= SRDY_I and cycle_busy;
|
||||
|
||||
|
||||
STB_O <= not busout_fifo_empty;
|
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CYC_O <= cycle_busy;
|
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cmd_cycle_finished <= not cycle_busy;
|
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|
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proc_bus_read_counter:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
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if rst = '1' then
|
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read_cnt <= 0;
|
||||
elsif cmd_read_en = '1' and busin_fifo_we = '0' then
|
||||
read_cnt <= read_cnt + 1;
|
||||
elsif cmd_read_en = '0' and busin_fifo_we = '1' then
|
||||
read_cnt <= read_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_cycle_busy:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
cycle_busy <= '0';
|
||||
elsif cmd_cycle_en = '1' then
|
||||
if cmd_we = '1' then
|
||||
cycle_busy <= '1';
|
||||
end if;
|
||||
elsif read_cnt = 0 and busout_fifo_empty = '1' then
|
||||
cycle_busy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
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-- Bus input FIFO
|
||||
inst_BM_IN_FIFO: entity work.fifo_sync
|
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GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
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||||
data_width => DATA_WIDTH,
|
||||
do_last_read_update => true
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => busin_fifo_we,
|
||||
re => busin_fifo_re,
|
||||
fifo_full => busin_fifo_full,
|
||||
fifo_empty => busin_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => MDAT_I,
|
||||
data_r => cmd_dout
|
||||
);
|
||||
|
||||
-- Bus output FIFO
|
||||
inst_BM_OUT_FIFO: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => NextExpBaseTwo(FIFO_DEPTH),
|
||||
data_width => busout_fifo_din'length,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => busout_fifo_we,
|
||||
re => busout_fifo_re,
|
||||
fifo_full => busout_fifo_full,
|
||||
fifo_empty => busout_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => busout_fifo_din,
|
||||
data_r => busout_fifo_dout
|
||||
);
|
||||
|
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end Behavioral;
|
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@@ -0,0 +1,436 @@
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||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.1 2013-05-25 16:55:29 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY tb_busmaster_sync IS
|
||||
END tb_busmaster_sync;
|
||||
|
||||
ARCHITECTURE behavior OF tb_busmaster_sync IS
|
||||
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
-- Master
|
||||
signal INT_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal WE_O : std_logic;
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic := '0';
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I_32 : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_O_32 : unsigned(31 downto 0) := (others => '-');
|
||||
signal MDAT_I : unsigned(63 downto 0) := (others => '-');
|
||||
signal MDAT_O : unsigned(63 downto 0) := (others => '-');
|
||||
|
||||
signal cmd_cycle_finished : std_logic;
|
||||
signal cmd_cycle_en : std_logic := '0';
|
||||
signal cmd_rdy : std_logic;
|
||||
signal cmd_we : std_logic := '0';
|
||||
signal cmd_din : unsigned(DATA_WIDTH-1 downto 0) := (others => '-');
|
||||
signal cmd_addr : unsigned(31 downto 0) := (others => '-');
|
||||
signal cmd_sel : unsigned(DATA_WIDTH/8-1 downto 0) := (others => '-');
|
||||
signal cmd_rw : std_logic := '0';
|
||||
|
||||
signal cmd_dout : unsigned(DATA_WIDTH-1 downto 0);
|
||||
signal cmd_dout_vld : std_logic;
|
||||
signal cmd_dout_re : std_logic := '0';
|
||||
|
||||
signal rdy : std_logic := '0';
|
||||
signal read_reg : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
type ram_t is array (0 to 127) of unsigned(63 downto 0);
|
||||
|
||||
signal ram64 : ram_t :=
|
||||
(
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000",
|
||||
X"0000_0000_0000_0000"
|
||||
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
MDAT_I_32 <= MDAT_I(31 downto 0);
|
||||
MDAT_O <= MDAT_O_32 & MDAT_O_32;
|
||||
|
||||
inst_busmaster_sync : entity work.busmaster_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
FIFO_DEPTH => 4,
|
||||
DATA_WIDTH => DATA_WIDTH
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
rst => RST_O,
|
||||
clk => CLK_O,
|
||||
|
||||
cmd_cycle_finished => cmd_cycle_finished,
|
||||
cmd_cycle_en => cmd_cycle_en,
|
||||
cmd_rdy => cmd_rdy,
|
||||
cmd_we => cmd_we,
|
||||
cmd_din => cmd_din,
|
||||
cmd_addr => cmd_addr,
|
||||
cmd_sel => cmd_sel,
|
||||
cmd_rw => cmd_rw,
|
||||
|
||||
cmd_dout => cmd_dout,
|
||||
cmd_dout_vld => cmd_dout_vld,
|
||||
cmd_dout_re => cmd_dout_re,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
MRDY_O => MRDY_O,
|
||||
ADDR_O => ADDR_O,
|
||||
MDAT_I => MDAT_I_32,
|
||||
MDAT_O => MDAT_O_32
|
||||
);
|
||||
|
||||
rdy_GEN: process
|
||||
begin
|
||||
-- wait for 3*CLK_PERIOD/2;
|
||||
wait until rising_edge(CLK_O);
|
||||
rdy <= not rdy;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
-- Slave
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
process(CLK_O)
|
||||
variable res: unsigned(63 downto 0);
|
||||
variable ram_data : unsigned(63 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
else
|
||||
ACK_I <= '0';
|
||||
if (CYC_O and STB_O) = '1' then
|
||||
if WE_O = '0' then
|
||||
ACK_I <= '1';
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
if ADDR_O(2) = '0' then
|
||||
res := ram_data;
|
||||
else
|
||||
res := ram_data(31 downto 0) & ram_data(63 downto 32);
|
||||
end if;
|
||||
else -- WE=1
|
||||
ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
|
||||
ram_data := (others => '-');
|
||||
if ADDR_O(2) = '0' then
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O;
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O(63 downto 32) & ram_data(31 downto 0);
|
||||
end if;
|
||||
else
|
||||
if SEL_O = "11111111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O(31 downto 0) & MDAT_O(63 downto 32);
|
||||
elsif SEL_O = "00001111" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O(31 downto 0) & ram_data(31 downto 0);
|
||||
elsif SEL_O = "11110000" then
|
||||
ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O(63 downto 32);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
MDAT_I <= res;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if RST_O = '1' then
|
||||
read_reg <= X"00000000";
|
||||
elsif cmd_dout_vld = '1' then
|
||||
read_reg <= cmd_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
cmd_dout_re <= cmd_dout_vld;
|
||||
|
||||
-- Master
|
||||
STIMULUS: process
|
||||
|
||||
variable result : unsigned(31 downto 0);
|
||||
|
||||
procedure cmd_write_single(addr, sel, data : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_rw <= '1';
|
||||
cmd_sel <= sel;
|
||||
cmd_addr <= addr;
|
||||
cmd_din <= data;
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_write_single;
|
||||
|
||||
procedure cmd_read_single(addr : unsigned) is
|
||||
begin
|
||||
|
||||
cmd_rw <= '0';
|
||||
cmd_sel <= (others => '0');
|
||||
cmd_addr <= addr;
|
||||
cmd_din <= (others => '0');
|
||||
cmd_we <= '1';
|
||||
wait until rising_edge(CLK_O) and cmd_rdy = '1';
|
||||
cmd_we <= '0';
|
||||
|
||||
end procedure cmd_read_single;
|
||||
|
||||
begin
|
||||
|
||||
wait for 6*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
state <= IDLE;
|
||||
|
||||
for i in 0 to 9 loop
|
||||
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
|
||||
cmd_read_single(X"0000_0000");
|
||||
cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
|
||||
cmd_read_single(X"0000_0008");
|
||||
cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
|
||||
cmd_read_single(X"0000_0010");
|
||||
cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
|
||||
cmd_read_single(X"0000_0018");
|
||||
cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
|
||||
cmd_read_single(X"0000_0020");
|
||||
cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
|
||||
cmd_read_single(X"0000_0028");
|
||||
cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
|
||||
cmd_read_single(X"0000_0030");
|
||||
cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
|
||||
cmd_read_single(X"0000_0038");
|
||||
cmd_cycle_en <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
wait until rising_edge(CLK_O);
|
||||
cmd_cycle_en <= '1';
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
|
||||
cmd_read_single(X"0000_0100");
|
||||
cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
|
||||
cmd_read_single(X"0000_0108");
|
||||
cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
|
||||
cmd_read_single(X"0000_0110");
|
||||
cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
|
||||
cmd_read_single(X"0000_0118");
|
||||
cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
|
||||
cmd_read_single(X"0000_0120");
|
||||
cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
|
||||
cmd_read_single(X"0000_0128");
|
||||
cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
|
||||
cmd_read_single(X"0000_0130");
|
||||
cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
|
||||
cmd_read_single(X"0000_0138");
|
||||
cmd_cycle_en <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and cmd_cycle_finished = '1';
|
||||
wait for 60*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
|
||||
end loop;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
Reference in New Issue
Block a user