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- added MII loopback

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git-svn-id: http://moon:8086/svn/vhdl/trunk@870 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-04-07 15:29:20 +00:00
parent edc389931a
commit 615b776ead
1 changed files with 8 additions and 1 deletions
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projects/mips_sys/src/tb_mips_sys.vhd
+8 -1
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@@ -40,7 +40,8 @@ ARCHITECTURE behavior OF tb_mips_sys IS
constant CLK_PERIOD : time := 10 ns;
constant AC97_CLK_PERIOD : time := 83 ns;
constant ETH_CLK_PERIOD : time := 40.7 ns;
constant ETH_CLK_PERIOD : time := 7.7 ns;
constant LOOP_BACK_EN : std_logic := '1';
signal sys_rst_n_in : std_logic := '0';
signal sys_clk_in : std_logic := '1';
signal dip : unsigned(7 downto 0) := (others => '0');
@@ -237,6 +238,12 @@ uut: entity work.mips_sys
sys_error => sys_error
);
sys_phy_rx <= sys_phy_tx when LOOP_BACK_EN = '1' else X"00";
sys_phy_rx_dv <= sys_phy_tx_en when LOOP_BACK_EN = '1' else '0';
sys_phy_rx_er <= sys_phy_tx_er when LOOP_BACK_EN = '1' else '0';
sys_phy_crs <= '0';
sys_phy_col <= '0';
inst_ssram : entity work.cy7c1354
PORT MAP
(