- m�nor changes
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@974 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -10,9 +10,9 @@ vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/busmaster_types.vhd"
|
||||
vcom -explicit -93 "../src/busmaster_sync.vhd"
|
||||
vcom -explicit -93 "../src/dma.vhd"
|
||||
vcom -explicit -93 "../src/tb_dma.vhd"
|
||||
vsim -t 1ps -lib work tb_dma
|
||||
vcom -explicit -93 "../src/dmac.vhd"
|
||||
vcom -explicit -93 "../src/tb_dmac.vhd"
|
||||
vsim -t 1ps -lib work tb_dmac
|
||||
view wave
|
||||
do {tb_dma.wdo}
|
||||
view structure
|
||||
|
||||
+13
-13
@@ -5,9 +5,7 @@ add wave -noupdate -format Literal /tb_dma/dma_master_req
|
||||
add wave -noupdate -format Literal /tb_dma/dma_master_gnt
|
||||
add wave -noupdate -format Literal /tb_dma/dma_req_rdy
|
||||
add wave -noupdate -format Literal /tb_dma/dma_req_en
|
||||
add wave -noupdate -format Literal /tb_dma/dma_req_rw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/dma_req_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/dma_req_addr_inc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/dma_req_num_xfers
|
||||
add wave -noupdate -format Literal /tb_dma/dma_req_complete
|
||||
add wave -noupdate -format Literal /tb_dma/dma_req_complete_ack
|
||||
@@ -79,12 +77,13 @@ add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/rst
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/master_req
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/master_gnt
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_active
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_rdy
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_rw
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uut/req_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uut/req_addr_inc
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_rw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uut/req_addr_start
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uut/req_num_xfers
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_addr_auto_inc
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_complete
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_complete_ack
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/bus_cyc_complete
|
||||
@@ -95,9 +94,9 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uu
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/start_en
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/finish_en
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/complete
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/rw
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/addr_inc_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uut/addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uut/addr_incr
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/rw
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__0/inst_uut/req_count_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uut/req_count
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__0/inst_uut/req_count_next
|
||||
@@ -113,12 +112,13 @@ add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/clk
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/rst
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/master_req
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/master_gnt
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_active
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_rdy
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_rw
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uut/req_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uut/req_addr_inc
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_rw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uut/req_addr_start
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uut/req_num_xfers
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_addr_auto_inc
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_complete
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_complete_ack
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/bus_cyc_complete
|
||||
@@ -129,9 +129,9 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uu
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/start_en
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/finish_en
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/complete
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/rw
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/addr_inc_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uut/addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uut/addr_incr
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/rw
|
||||
add wave -noupdate -format Logic /tb_dma/gen_uut__1/inst_uut/req_count_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uut/req_count
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/gen_uut__1/inst_uut/req_count_next
|
||||
@@ -156,7 +156,7 @@ add wave -noupdate -divider RAM
|
||||
add wave -noupdate -format Literal /tb_dma/state
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_dma/ram64
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {2164007 ps} 0}
|
||||
WaveRestoreCursors {{Cursor 1} {3159968 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
|
||||
+23
-38
@@ -1,5 +1,5 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dma.vhd,v 1.2 2013-05-27 21:31:15 jens Exp $
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dma.vhd,v 1.3 2013-05-28 10:13:18 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
@@ -9,7 +9,7 @@ use work.utils_pkg.all;
|
||||
use work.busmaster_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity dma is
|
||||
entity dmac is
|
||||
Generic
|
||||
(
|
||||
DATA_WIDTH : natural := 32;
|
||||
@@ -23,18 +23,19 @@ entity dma is
|
||||
master_req : out std_logic;
|
||||
master_gnt : in std_logic;
|
||||
|
||||
dma_active : out std_logic;
|
||||
|
||||
req_rdy : out std_logic;
|
||||
req_rw : in std_logic;
|
||||
req_en : in std_logic;
|
||||
req_addr : in unsigned(31 downto 0);
|
||||
req_addr_inc : in unsigned(31 downto 0);
|
||||
req_rw : in std_logic;
|
||||
req_addr_start : in unsigned(31 downto 0);
|
||||
req_num_xfers : in unsigned(31 downto 0);
|
||||
req_addr_auto_inc : in std_logic;
|
||||
|
||||
req_complete : out std_logic;
|
||||
req_complete_ack : in std_logic;
|
||||
|
||||
-- busmaster control
|
||||
bus_din_re : out std_logic;
|
||||
bus_cyc_complete : in std_logic;
|
||||
bus_cmd_rdy : in std_logic;
|
||||
bus_cmd_we : out std_logic;
|
||||
@@ -43,16 +44,16 @@ entity dma is
|
||||
-- busmaster command
|
||||
bus_cmd_out : out bm_cmd_t
|
||||
);
|
||||
end dma;
|
||||
end dmac;
|
||||
|
||||
architecture Behavioral of dma is
|
||||
architecture Behavioral of dmac is
|
||||
|
||||
signal start_en : std_logic;
|
||||
signal finish_en : std_logic;
|
||||
signal complete : std_logic;
|
||||
signal rw : std_logic;
|
||||
signal addr_inc_en : std_logic;
|
||||
signal addr : unsigned(31 downto 0);
|
||||
signal addr_incr : unsigned(31 downto 0);
|
||||
signal rw : std_logic;
|
||||
|
||||
signal req_count_en : std_logic;
|
||||
signal req_count : unsigned(31 downto 0);
|
||||
@@ -65,13 +66,13 @@ architecture Behavioral of dma is
|
||||
signal chunk_count_next : unsigned(32 downto 0);
|
||||
signal chunk_count_rdy : std_logic;
|
||||
|
||||
type state_t is (INIT, READY, SETUP, XFER_WRITE, XFER_READ, FINISH);
|
||||
type state_t is (INIT, READY, SETUP, XFER, FINISH);
|
||||
signal s, sn : state_t;
|
||||
|
||||
begin
|
||||
|
||||
bus_cmd_out.addr <= addr;
|
||||
bus_cmd_out.sel <= "1111";
|
||||
bus_cmd_out.sel <= (others => '1');
|
||||
bus_cmd_out.rw <= rw;
|
||||
req_complete <= complete;
|
||||
|
||||
@@ -88,7 +89,7 @@ state_next:
|
||||
end process;
|
||||
|
||||
state:
|
||||
process(s, req_en, rw, master_gnt, req_count_rdy, chunk_count_rdy, bus_cyc_complete, bus_cmd_rdy)
|
||||
process(s, req_en, master_gnt, req_count_rdy, chunk_count_rdy, bus_cyc_complete, bus_cmd_rdy)
|
||||
begin
|
||||
|
||||
bus_cmd_cycle_en <= '0';
|
||||
@@ -100,7 +101,7 @@ state:
|
||||
chunk_count_rst <= '0';
|
||||
chunk_count_en <= '0';
|
||||
master_req <= '0';
|
||||
bus_din_re <= '0';
|
||||
dma_active <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
@@ -120,27 +121,11 @@ state:
|
||||
if req_count_rdy = '1' then
|
||||
sn <= READY;
|
||||
elsif master_gnt = '1' and bus_cyc_complete = '1' then
|
||||
if rw = '1' then
|
||||
sn <= XFER_WRITE;
|
||||
else
|
||||
sn <= XFER_READ;
|
||||
end if;
|
||||
sn <= XFER;
|
||||
end if;
|
||||
|
||||
when XFER_WRITE =>
|
||||
master_req <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
bus_cmd_cycle_en <= '1';
|
||||
req_count_en <= bus_cmd_rdy;
|
||||
chunk_count_en <= bus_cmd_rdy;
|
||||
bus_din_re <= '1';
|
||||
if req_count_rdy = '1' then
|
||||
sn <= FINISH;
|
||||
elsif chunk_count_rdy = '1' then
|
||||
sn <= SETUP;
|
||||
end if;
|
||||
|
||||
when XFER_READ =>
|
||||
when XFER =>
|
||||
dma_active <= '1';
|
||||
master_req <= '1';
|
||||
bus_cmd_we <= '1';
|
||||
bus_cmd_cycle_en <= '1';
|
||||
@@ -170,11 +155,11 @@ addr_gen:
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if start_en = '1' then
|
||||
addr <= req_addr;
|
||||
addr_incr <= req_addr_inc;
|
||||
rw <= req_rw;
|
||||
elsif req_count_en = '1' then
|
||||
addr <= addr + addr_incr;
|
||||
rw <= req_rw;
|
||||
addr <= req_addr_start;
|
||||
addr_inc_en <= req_addr_auto_inc;
|
||||
elsif req_count_en = '1' and addr_inc_en = '1' then
|
||||
addr <= addr + DATA_WIDTH/8;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
+58
-73
@@ -1,5 +1,5 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dma.vhd,v 1.2 2013-05-27 21:31:15 jens Exp $
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dma.vhd,v 1.3 2013-05-28 10:13:18 jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
@@ -8,14 +8,19 @@ USE ieee.numeric_std.ALL;
|
||||
|
||||
use work.busmaster_types.all;
|
||||
|
||||
ENTITY tb_dma IS
|
||||
END tb_dma;
|
||||
ENTITY tb_dmac IS
|
||||
END tb_dmac;
|
||||
|
||||
ARCHITECTURE behavior OF tb_dma IS
|
||||
ARCHITECTURE behavior OF tb_dmac IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
|
||||
constant DMA_NUM_CHANNEL : integer := 2;
|
||||
constant DATA_WIDTH : integer := 32;
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant DMA_CH_WRITE : integer := 0;
|
||||
constant DMA_CH_READ : integer := 1;
|
||||
constant DMA_RW_CONF : unsigned(DMA_NUM_CHANNEL-1 downto 0) := "01";
|
||||
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
|
||||
@@ -39,17 +44,16 @@ ARCHITECTURE behavior OF tb_dma IS
|
||||
signal dma_master_req : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_master_gnt : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
signal dma_req_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_req_rw : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
signal dma_req_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
signal dma_req_addr_auto_inc : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
type array32_t is array (0 to DMA_NUM_CHANNEL-1) of unsigned(31 downto 0);
|
||||
signal dma_req_addr : array32_t;
|
||||
signal dma_req_addr_inc : array32_t;
|
||||
signal dma_req_num_xfers : array32_t;
|
||||
|
||||
signal dma_req_complete : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_req_complete_ack : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
|
||||
signal dma_bus_din_re : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_req_active : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_bus_cmd_cycle_finished : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
signal dma_bus_cmd_cycle_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
|
||||
signal dma_bus_cmd_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0);
|
||||
@@ -268,65 +272,62 @@ arbiter_mux:
|
||||
process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en)
|
||||
variable v_bus_cmd_we : std_logic;
|
||||
variable v_bus_cmd_cycle_en : std_logic;
|
||||
variable v_bus_din_re : std_logic;
|
||||
begin
|
||||
v_bus_cmd_we := '0';
|
||||
v_bus_cmd_cycle_en := '0';
|
||||
v_bus_din_re := '0';
|
||||
for i in 0 to DMA_NUM_CHANNEL-1 loop
|
||||
v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i);
|
||||
v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i);
|
||||
v_bus_din_re := v_bus_din_re or dma_bus_din_re(i);
|
||||
if dma_master_gnt(i) = '1' then
|
||||
bus_cmd <= dma_bus_cmd(i);
|
||||
end if;
|
||||
end loop;
|
||||
bus_cmd_we <= v_bus_cmd_we;
|
||||
bus_cmd_cycle_en <= v_bus_cmd_cycle_en;
|
||||
bus_din_re <= v_bus_din_re;
|
||||
end process;
|
||||
|
||||
|
||||
gen_uut:
|
||||
for i in 0 to DMA_NUM_CHANNEL-1 generate
|
||||
|
||||
dma_bus_cmd_cycle_finished(i) <= bus_cmd_cycle_finished;
|
||||
dma_bus_cmd_rdy(i) <= bus_cmd_rdy;
|
||||
|
||||
inst_uut : entity work.dma
|
||||
Generic map
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
XFER_CHUNK_SIZE => 64
|
||||
)
|
||||
Port map
|
||||
(
|
||||
clk => CLK_O,
|
||||
rst => RST_O,
|
||||
inst_uut : entity work.dmac
|
||||
Generic map
|
||||
(
|
||||
DATA_WIDTH => 32,
|
||||
XFER_CHUNK_SIZE => 8
|
||||
)
|
||||
Port map
|
||||
(
|
||||
clk => CLK_O,
|
||||
rst => RST_O,
|
||||
|
||||
master_req => dma_master_req(i),
|
||||
master_gnt => dma_master_gnt(i),
|
||||
master_req => dma_master_req(i),
|
||||
master_gnt => dma_master_gnt(i),
|
||||
|
||||
req_rdy => dma_req_rdy(i),
|
||||
req_rw => dma_req_rw(i),
|
||||
req_en => dma_req_en(i),
|
||||
req_addr => dma_req_addr(i),
|
||||
req_addr_inc => dma_req_addr_inc(i),
|
||||
req_num_xfers => dma_req_num_xfers(i),
|
||||
req_rdy => dma_req_rdy(i),
|
||||
req_en => dma_req_en(i),
|
||||
req_rw => DMA_RW_CONF(i),
|
||||
req_addr_auto_inc => dma_req_addr_auto_inc(i),
|
||||
req_addr_start => dma_req_addr(i),
|
||||
req_num_xfers => dma_req_num_xfers(i),
|
||||
|
||||
req_complete => dma_req_complete(i),
|
||||
req_complete_ack => dma_req_complete_ack(i),
|
||||
req_complete => dma_req_complete(i),
|
||||
req_complete_ack => dma_req_complete_ack(i),
|
||||
|
||||
-- busmaster control
|
||||
bus_din_re => dma_bus_din_re(i),
|
||||
dma_active => dma_active(i),
|
||||
|
||||
bus_cyc_complete => dma_bus_cmd_cycle_finished(i),
|
||||
bus_cmd_rdy => dma_bus_cmd_rdy(i),
|
||||
bus_cmd_we => dma_bus_cmd_we(i),
|
||||
bus_cmd_cycle_en => dma_bus_cmd_cycle_en(i),
|
||||
-- busmaster control
|
||||
bus_cyc_complete => dma_bus_cmd_cycle_finished(i),
|
||||
bus_cmd_rdy => dma_bus_cmd_rdy(i),
|
||||
bus_cmd_we => dma_bus_cmd_we(i),
|
||||
bus_cmd_cycle_en => dma_bus_cmd_cycle_en(i),
|
||||
|
||||
-- busmaster command
|
||||
bus_cmd_out => dma_bus_cmd(i)
|
||||
);
|
||||
-- busmaster command
|
||||
bus_cmd_out => dma_bus_cmd(i)
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
@@ -409,10 +410,10 @@ CLK_GEN: process
|
||||
SRDY_I <= CYC_O;
|
||||
|
||||
bus_dout_re <= '1' when dma_write_source = DATA_GEN else not read_fifo_full;
|
||||
bus_din_vld <= bus_din_re when dma_write_source = DATA_GEN else (bus_din_re and not read_fifo_empty);
|
||||
bus_din_vld <= dma_active(DMA_CH_WRITE) when dma_write_source = DATA_GEN else (dma_active(DMA_CH_WRITE) and not read_fifo_empty);
|
||||
bus_din <= data_gen_reg when dma_write_source = DATA_GEN else read_fifo_dout;
|
||||
data_gen_reg_inc <= (bus_din_rdy and bus_din_re) when dma_write_source = DATA_GEN else '0';
|
||||
read_fifo_re <= (bus_din_rdy and bus_din_re) when dma_write_source = READ_FIFO else '0';
|
||||
data_gen_reg_inc <= (bus_din_rdy and dma_active(DMA_CH_WRITE)) when dma_write_source = DATA_GEN else '0';
|
||||
read_fifo_re <= (bus_din_rdy and dma_active(DMA_CH_WRITE)) when dma_write_source = READ_FIFO else '0';
|
||||
read_fifo_we <= bus_dout_vld;
|
||||
read_fifo_din <= bus_dout;
|
||||
|
||||
@@ -497,35 +498,19 @@ STIMULUS: process
|
||||
|
||||
end procedure dma_wait_xfer_complete;
|
||||
|
||||
procedure dma_request_write(ch : integer; addr_start, addr_incr, num_xfers : unsigned) is
|
||||
procedure dma_request(ch : integer; addr_start, num_xfers : unsigned) is
|
||||
begin
|
||||
|
||||
dma_req_addr(ch) <= addr_start;
|
||||
dma_req_addr_inc(ch) <= addr_incr;
|
||||
dma_req_num_xfers(ch) <= num_xfers;
|
||||
dma_req_addr_auto_inc(ch) <= '1';
|
||||
dma_req_addr(ch) <= addr_start;
|
||||
dma_req_num_xfers(ch) <= num_xfers;
|
||||
|
||||
dma_req_rw(ch) <= '1';
|
||||
dma_req_en(ch) <= '1';
|
||||
dma_req_en(ch) <= '1';
|
||||
|
||||
wait until rising_edge(CLK_O) and dma_req_rdy(ch) = '1';
|
||||
dma_req_en(ch) <= '0';
|
||||
|
||||
end procedure dma_request_write;
|
||||
|
||||
procedure dma_request_read(ch : integer; addr_start, addr_incr, num_xfers : unsigned) is
|
||||
begin
|
||||
|
||||
dma_req_addr(ch) <= addr_start;
|
||||
dma_req_addr_inc(ch) <= addr_incr;
|
||||
dma_req_num_xfers(ch) <= num_xfers;
|
||||
|
||||
dma_req_rw(ch) <= '0';
|
||||
dma_req_en(ch) <= '1';
|
||||
|
||||
wait until rising_edge(CLK_O) and dma_req_rdy(ch) = '1';
|
||||
dma_req_en(ch) <= '0';
|
||||
|
||||
end procedure dma_request_read;
|
||||
end procedure dma_request;
|
||||
|
||||
begin
|
||||
|
||||
@@ -535,13 +520,13 @@ STIMULUS: process
|
||||
wait until rising_edge(CLK_O);
|
||||
state <= IDLE;
|
||||
|
||||
dma_request_write(0, X"00000000", X"00000004", X"00000040");
|
||||
dma_wait_xfer_complete(0);
|
||||
dma_request_read(1, X"00000000", X"00000004", X"00000040");
|
||||
dma_wait_xfer_complete(1);
|
||||
dma_request(DMA_CH_WRITE, X"00000000", X"00000040");
|
||||
-- dma_wait_xfer_complete(DMA_CH_WRITE);
|
||||
dma_request(DMA_CH_READ, X"00000000", X"00000040");
|
||||
dma_wait_xfer_complete(DMA_CH_READ);
|
||||
dma_write_source <= READ_FIFO;
|
||||
dma_request_write(0, X"00000100", X"00000004", X"00000040");
|
||||
dma_wait_xfer_complete(0);
|
||||
dma_request(DMA_CH_WRITE, X"00000100", X"00000040");
|
||||
-- dma_wait_xfer_complete(DMA_CH_WRITE);
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user