- SDR-Clock now derived from clk_in, instead of sys_clk_fx

Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@948 cc03376c-175c-47c8-b038-4cd826a8556b
2013-04-26 10:42:07 +00:00
parent 2361b4a440
commit e349fbcecf
1 changed files with 1 additions and 1 deletions
@@ -231,7 +231,7 @@ inst_DCM_SDRCLK_0 : DCM_BASE
 		CLKFX180 => open, -- 180 degree CLK synthesis out
 		LOCKED => sdr0_lock,     -- DCM LOCK status output
 		CLKFB => sdr0_clk_fb_in,       -- DCM clock feedback
-		CLKIN => sys_clkfx_bufg,       -- Clock input (from IBUFG, BUFG or DCM)
+		CLKIN => sys_clk0_bufg,       -- Clock input (from IBUFG, BUFG or DCM)
 		RST => dcm_rst(1)            -- DCM asynchronous reset input
 	);