- reg_uart_tx is also written in simulation mode. Good for debugging.

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git-svn-id: http://moon:8086/svn/vhdl/trunk@987 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/uart_wb.vhd

@@ -102,6 +102,7 @@ registers_write:
 				case ADDR_I(5 downto 2) is
 				
 				when "0000" =>
+					reg_uart_tx		<= DAT_I(7 downto 0);
 					if simulate_tx then
 						if DAT_I(7 downto 0) /= X"0D" then
 							write(L, character'val(to_integer(DAT_I(7 downto 0))));
@@ -111,7 +112,6 @@ registers_write:
 						end if;
 					else	
 						reg_we_uart_tx	<= '1';
-						reg_uart_tx		<= DAT_I(7 downto 0);
 					end if;
 					
 				when "0001" =>