- avoid of undefined data in forwarding logic during simulation.

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git-svn-id: http://moon:8086/svn/vhdl/trunk@982 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/core/mips_pipeline.vhd

@@ -394,7 +394,15 @@ proc_stage_fwd_a:
 		elsif hdu.alu_fwd_a_wb then
 			data 	:= WB_stage.data;
 		end if;
-		ID_stage.reg_a	<= to_01(data) after 2 ns;
+		
+		for i in 0 to 31 loop
+			if data(i) = '1' then
+				ID_stage.reg_a(i)	<= '1' after 2 ns;
+			else 
+				ID_stage.reg_a(i)	<= '0' after 2 ns;
+			end if;
+		end loop;
+
 	end process;
 
 proc_stage_fwd_b:
@@ -409,7 +417,15 @@ proc_stage_fwd_b:
 		elsif hdu.alu_fwd_b_wb then
 			data	:= WB_stage.data;
 		end if;
-		ID_stage.reg_b	<= to_01(data) after 2 ns;
+
+		for i in 0 to 31 loop
+			if data(i) = '1' then
+				ID_stage.reg_b(i)	<= '1' after 2 ns;
+			else 
+				ID_stage.reg_b(i)	<= '0' after 2 ns;
+			end if;
+		end loop;
+
 	end process;
 	
 proc_imm_mux: