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git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1012 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-18 09:07:16 +00:00
parent e59d0f2904
commit a3b0766258
4 changed files with 142 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/tb_mips_biu.vhd
+11 -9
View File
@@ -7,10 +7,10 @@ use work.mips_types.all;
use work.mips_util_pkg.all;
use work.busmaster_types.all;
ENTITY tb_biu_tlb IS
END tb_biu_tlb;
ENTITY tb_biu IS
END tb_biu;
ARCHITECTURE behavior OF tb_biu_tlb IS
ARCHITECTURE behavior OF tb_biu IS
constant DATA_WIDTH : integer := 32;
constant CLK_PERIOD : time := 10 ns;
@@ -72,10 +72,12 @@ BEGIN
inst_biu: entity work.biu
GENERIC MAP
(
icache_size => 1024, -- words
icache_line => 8, -- words
dcache_size => 1024, -- words
dcache_line => 8 -- words
ICACHE_SIZE => 1024, -- words
ICACHE_LINE => 8, -- words
DCACHE_SIZE => 1024, -- words
DCACHE_LINE => 8, -- words
WRITE_FIFO_SIZE => 4, -- words
WITH_TLB => true
)
PORT MAP
(
@@ -192,12 +194,12 @@ STIMULUS: process
ctrl_in.itlb.entry_hi.vpn <= vpn;
ctrl_in.itlb.entry_hi.asid <= asid;
ctrl_in.itlb.entry_hi.g <= g;
ctrl_in.itlb.entry_lo.pfn <= pfn;
ctrl_in.itlb.entry_lo.n <= n;
ctrl_in.itlb.entry_lo.d <= d;
ctrl_in.itlb.entry_lo.v <= v;
ctrl_in.itlb.entry_lo.g <= g;
ctrl_in.itlb.entry_we <= '1';
wait until rising_edge(CLK);
@@ -213,12 +215,12 @@ STIMULUS: process
ctrl_in.dtlb.entry_hi.vpn <= vpn;
ctrl_in.dtlb.entry_hi.asid <= asid;
ctrl_in.dtlb.entry_hi.g <= g;
ctrl_in.dtlb.entry_lo.pfn <= pfn;
ctrl_in.dtlb.entry_lo.n <= n;
ctrl_in.dtlb.entry_lo.d <= d;
ctrl_in.dtlb.entry_lo.v <= v;
ctrl_in.dtlb.entry_lo.g <= g;
ctrl_in.dtlb.entry_we <= '1';
wait until rising_edge(CLK);
lib/CPUs/MIPS/src/tb_mips_cam.vhd
+125 -21
View File
@@ -23,7 +23,8 @@ ARCHITECTURE behavior OF tb_cam IS
signal cam_rdy : std_logic := '-';
signal cam_addr : unsigned(lg2(CAM_NUM_ENTRIES)-1 downto 0) := (others => '0');
signal cam_data : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
signal cam_rtag : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
signal cam_wtag : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
signal cam_hit : unsigned (CAM_NUM_ENTRIES-1 downto 0);
signal cam_hit_vld : std_logic := '-';
@@ -40,19 +41,21 @@ inst_cam: entity work.cam
)
PORT MAP
(
rst => RST_O,
clk => CLK_O,
rst => RST_O,
clk => CLK_O,
clk_rd => CLK_O,
rdy => cam_rdy,
rdy => cam_rdy,
re => cam_re,
we => cam_we,
vld => cam_vld,
addr => cam_addr,
din => cam_data,
re => cam_re,
we => cam_we,
vld => cam_vld,
addr => cam_addr,
tag_rd => cam_rtag,
tag_wr => cam_wtag,
hit => cam_hit,
hit_vld => cam_hit_vld
hit_vld => cam_hit_vld,
hit => cam_hit
);
@@ -65,12 +68,12 @@ CLK_GEN: process
STIMULUS: process
variable result : unsigned(31 downto 0);
variable tag : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
procedure cam_entry_write(index : integer; data : unsigned; valid : std_logic) is
begin
cam_data <= data;
cam_wtag <= data;
cam_addr <= to_unsigned(index, lg2(CAM_NUM_ENTRIES));
cam_vld <= valid;
cam_we <= '1';
@@ -82,7 +85,7 @@ STIMULUS: process
procedure cam_lookup(data : unsigned) is
begin
cam_data <= data;
cam_rtag <= data;
cam_re <= '1';
wait until rising_edge(CLK_O) and cam_rdy = '1';
cam_re <= '0';
@@ -97,17 +100,118 @@ STIMULUS: process
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
-----------------------
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_entry_write(i, tag, '1');
tag := tag + X"0100_0";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_lookup(tag);
tag := tag + X"0100_0";
end loop;
cam_entry_write(1, X"CAFE_1", '1');
cam_entry_write(2, X"CAFE_2", '1');
wait for 8*CLK_PERIOD;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
cam_lookup(X"CAFE_1");
cam_lookup(X"CAFE_2");
wait for 8*CLK_PERIOD;
RST_O <= '1';
wait for 6*CLK_PERIOD;
wait until rising_edge(CLK_O);
RST_O <= '0';
wait until rising_edge(CLK_O) and cam_rdy = '1';
-----------------------
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_entry_write(i, tag, '1');
tag := tag + X"0010_0";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_lookup(tag);
tag := tag + X"0010_0";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
RST_O <= '1';
wait for 6*CLK_PERIOD;
wait until rising_edge(CLK_O);
RST_O <= '0';
wait until rising_edge(CLK_O) and cam_rdy = '1';
-----------------------
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_entry_write(i, tag, '1');
tag := tag + X"0001_0";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_lookup(tag);
tag := tag + X"0001_0";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
RST_O <= '1';
wait for 6*CLK_PERIOD;
wait until rising_edge(CLK_O);
RST_O <= '0';
wait until rising_edge(CLK_O) and cam_rdy = '1';
-----------------------
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_entry_write(i, tag, '1');
tag := tag + X"0000_1";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_lookup(tag);
tag := tag + X"0000_1";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
RST_O <= '1';
wait for 6*CLK_PERIOD;
wait until rising_edge(CLK_O);
RST_O <= '0';
wait until rising_edge(CLK_O) and cam_rdy = '1';
-----------------------
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_entry_write(i, tag, '1');
tag := tag + X"0102_3";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
tag := X"CAF0_0";
for i in 0 to CAM_NUM_ENTRIES-1 loop
cam_lookup(tag);
tag := tag + X"0102_3";
end loop;
wait for 60*CLK_PERIOD;
wait until rising_edge(CLK_O) and cam_rdy = '1';
RST_O <= '1';
wait for 6*CLK_PERIOD;
wait until rising_edge(CLK_O);
RST_O <= '0';
wait until rising_edge(CLK_O) and cam_rdy = '1';
-----------------------
-- overwrite
cam_entry_write(2, X"BEEF_2", '1');
wait for 8*CLK_PERIOD;
lib/CPUs/MIPS/src/tb_mips_dcache.vhd
+3 -3
View File
@@ -7,10 +7,10 @@ use work.mips_types.all;
use work.mips_util_pkg.all;
use work.busmaster_types.all;
ENTITY tb_dcache_tlb IS
END tb_dcache_tlb;
ENTITY tb_dcache IS
END tb_dcache;
ARCHITECTURE behavior OF tb_dcache_tlb IS
ARCHITECTURE behavior OF tb_dcache IS
constant DATA_WIDTH : integer := 32;
constant CLK_PERIOD : time := 10 ns;
lib/CPUs/MIPS/src/tb_mips_icache.vhd
+3 -3
View File
@@ -7,10 +7,10 @@ use work.mips_types.all;
use work.mips_util_pkg.all;
use work.busmaster_types.all;
ENTITY tb_icache_tlb IS
END tb_icache_tlb;
ENTITY tb_icache IS
END tb_icache;
ARCHITECTURE behavior OF tb_icache_tlb IS
ARCHITECTURE behavior OF tb_icache IS
constant DATA_WIDTH : integer := 32;
constant CLK_PERIOD : time := 10 ns;