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- debug output is now record

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git-svn-id: http://moon:8086/svn/vhdl/trunk@999 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-18 07:07:27 +00:00
parent ae123fadc7
commit c0bf39885e
5 changed files with 23 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_top.vhd
+3 -3
View File
@@ -38,7 +38,7 @@ entity mips_top is
);
Port
(
debug : out unsigned(1 downto 0);
debug : out chip_debug_t;
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
@@ -189,8 +189,8 @@ architecture rtl of mips_top is
begin
-------------------------------------------------------------------
debug(0) <= imem_err;
debug(1) <= dmem_err;
debug.imem_err <= imem_err;
debug.dmem_err <= dmem_err;
process(CLK_I)
variable reset_delay : unsigned (31 downto 0);
lib/CPUs/MIPS/src/core/mips_types.vhd
+5
View File
@@ -43,6 +43,11 @@ package mips_types is
subtype sa_t is natural range 0 to 63;
subtype func_t is unsigned(5 downto 0);
type chip_debug_t is record
imem_err : std_logic;
dmem_err : std_logic;
end record;
type op_t is
(
op_illegal,
lib/CPUs/MIPS/src/tb_mips_top.vhd
+5 -6
View File
@@ -42,7 +42,7 @@ ARCHITECTURE behavior OF tb_mips_top IS
constant SRAM_ADDR_WIDTH : integer := 17; -- bits
constant FLASH_ADDR_WIDTH : integer := 17; -- bits
signal debug : unsigned(1 downto 0);
signal debug : chip_debug_t;
-- Master
signal nmi : STD_LOGIC := '0';
@@ -399,8 +399,9 @@ SRAM_WRITE:
FLASH_READ:
process(rst, flash_cs_n, flash_oe_n, flash_a)
type file_t is file of integer;
file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
-- file load_flash : file_t open read_mode is "test_timer.flash.bin";
-- file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
-- file load_flash : file_t open read_mode is "test_dcache.flash.bin";
variable instr : integer;
variable index : natural;
variable temp : signed(31 downto 0);
@@ -441,9 +442,7 @@ STIMULUS: process
begin
gpi_0(23 downto 16) <= "00000000";
gpi_0(28 downto 24) <= "00000";
gpi_0(31) <= 'H';
gpi_0 <= X"00000000";
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
rst <= '0';
projects/mips_sys/src/mips_sys.vhd
+6 -3
View File
@@ -157,7 +157,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT mips_top
Port
(
debug : out unsigned(1 downto 0);
debug : out chip_debug_t;
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
@@ -185,6 +185,7 @@ ARCHITECTURE behavior OF mips_sys IS
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
@@ -486,7 +487,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal usb_inten : std_logic;
signal phy_inten : std_logic;
signal debug : unsigned(1 downto 0);
signal debug : chip_debug_t;
-- DDR SDRAM
constant BURST_LEN : natural := 2;
@@ -538,7 +539,8 @@ BEGIN
sys_phy_mdio <= gpo_0(31);
eb <= sys_dip(7);
sys_error <= debug;
sys_error(0) <= debug.imem_err;
sys_error(1) <= debug.dmem_err;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0);
sys_flash_byten <= '1';
@@ -752,6 +754,7 @@ inst_rom_wb : rom_wb
RST_I => RST_O,
CYC_I => CYC_I_rom,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_rom,
MRDY_I => MRDY_O,
SRDY_O => SRDY_O_rom,
projects/mips_sys/src/mips_sys_sim.vhd
+4 -2
View File
@@ -317,7 +317,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal usb_inten : std_logic;
signal phy_inten : std_logic;
signal debug : unsigned(1 downto 0);
signal debug : chip_debug_t;
-- DDR SDRAM
constant BURST_LEN : natural := 2;
@@ -362,7 +362,8 @@ BEGIN
sys_phy_mdio <= gpo_0(31);
eb <= sys_dip(7);
sys_error <= debug;
sys_error(0) <= debug.imem_err;
sys_error(1) <= debug.dmem_err;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
sys_flash_byten <= '1';
@@ -597,6 +598,7 @@ inst_rom_wb : entity work.rom_wb
RST_I => RST_O,
CYC_I => CYC_I_rom,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_rom,
MRDY_I => MRDY_O,
SRDY_O => SRDY_O_rom,