jens 81698e2391 - integrated ITLB and DTLB into pipeline. ...

TLB queries come from pipeline if generic PIPE_ITLB or  PIPE_DTLB is true. Cache query is then disabled.
  If generic PIPE_ITLB or  PIPE_DTLB set to false queries come from cache.
  Piped TLB queries are piped translations with latency of two clocks. Piped translation allow physically indexed and physically tagged caches
- reworked PC logic
- prepared for individual BCUs in EX, MEM and WB stage
- changed LTS and LTU generation in ALU

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git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1015 cc03376c-175c-47c8-b038-4cd826a8556b

2013-08-18 18:56:42 +00:00

lib/CPUs/MIPS

- integrated ITLB and DTLB into pipeline.

2013-08-18 18:56:42 +00:00

projects/mips_sys

This commit was manufactured by cvs2svn to create branch 'BRANCH_MIPS_TLB'.

2013-08-18 07:07:28 +00:00

S

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23 MiB

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VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%