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base: jens/vhdl:R3
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jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
..
compare: jens/vhdl:MIPS_R9
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
226 Commits
R3 .. MIPS_R9
Author SHA1 Message Date
jens a67fbb643b This commit was manufactured by cvs2svn to create tag 'MIPS_R9'. 
git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R9@271 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-20 21:26:49 +00:00
jens 25e3d4f36f - changed to rev.9 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@270 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-20 21:26:48 +00:00
jens 3db7aa0fb4 - removed commented lines 
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git-svn-id: http://moon:8086/svn/vhdl/trunk@269 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-20 21:19:41 +00:00
jens 523e216793 - removed PCK_FIO (not needed) 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@268 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-19 10:05:43 +00:00
jens bd4b69206f - Minor changes 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@267 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:36:15 +00:00
jens 61e740cc1d - deleted 
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git-svn-id: http://moon:8086/svn/vhdl/trunk@266 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:27:29 +00:00
jens 592c158275 Initial version 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@265 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:25:52 +00:00
jens 791e97a873 - update 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@264 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:20:49 +00:00
jens 0b5b8ceed7 - removed duplicate entry 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@263 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:20:32 +00:00
jens 31bd88a707 - major changes 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@262 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:15:12 +00:00
jens 739921d7a9 - rename 'page' to 'bank' 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@261 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:14:40 +00:00
jens cfb87bf755 - Minor changes 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@260 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:08:26 +00:00
jens 73f7a85646 - added ac97 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@259 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:08:13 +00:00
jens 03780653b8 - changes on async_port 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@258 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:07:48 +00:00
jens 0dcb62d6ff - put async_types to lib/misc/async_types 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@257 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 22:07:25 +00:00
jens 8534d570e0 - added SEL_I and multiple write-enables on async port 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@256 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 21:44:57 +00:00
jens 60bb979bb7 Initial version 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@255 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 21:44:26 +00:00
jens 5681bf5693 Initial version 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@254 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 14:39:34 +00:00
jens 1a26f8176a - Minor changes 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@253 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 14:39:23 +00:00
jens 9ef46952e2 - added flashgen build 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@252 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 14:39:03 +00:00
jens 06bb5f8f0d - deleted 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@251 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-18 10:01:07 +00:00
jens 987f426a57 - update 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@249 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:40:07 +00:00
jens 6c03c853f6 - renamed bui, icache and dcache 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@248 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:34:55 +00:00
jens d63cdf3cb1 - renamed bui to biu 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@247 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:33:18 +00:00
jens 4c482f1cda - renamed 
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@246 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:33:06 +00:00
jens 9f7547c68e - deleted 
git-svn-id: http://moon:8086/svn/vhdl/trunk@245 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 07:47:24 +00:00
jens dd6bd675f1 - changed to J-Bus interface 
git-svn-id: http://moon:8086/svn/vhdl/trunk@244 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-15 07:07:51 +00:00
jens c882f1d469 - changed read, write order (should have no effect) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@243 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 20:26:29 +00:00
jens 9163ced247 - uses common fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@242 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:43:36 +00:00
jens 0c8a1c2ec5 - removed reference to mix_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@241 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:41:01 +00:00
jens f053756416 - deleted 
git-svn-id: http://moon:8086/svn/vhdl/trunk@240 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:37:07 +00:00
jens 70645de004 - uses common fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@239 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:36:50 +00:00
jens e91134a95f - uses common fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@238 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:28:39 +00:00
jens d9030dc07c - removed decimation in m-script (which is done in CFIR) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@237 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-13 10:08:17 +00:00
jens 1417d6f5cd - bugfix 'x_out' register 
git-svn-id: http://moon:8086/svn/vhdl/trunk@236 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-13 09:55:05 +00:00
jens ef9b538769 - fir_stage_sys only uses pipe_latency as parameter 
git-svn-id: http://moon:8086/svn/vhdl/trunk@235 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-13 09:29:45 +00:00
jens 6a1d8f729f Initial version 
git-svn-id: http://moon:8086/svn/vhdl/trunk@234 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-12 10:11:09 +00:00
jens bcefe4639e - removed adding of one bit to cic_stages 
git-svn-id: http://moon:8086/svn/vhdl/trunk@233 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-12 09:56:08 +00:00
jens cf548fd893 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@232 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 19:08:23 +00:00
jens 89723cf6d0 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@231 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 18:47:33 +00:00
jens 308d0d8f4a - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@230 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 18:30:36 +00:00
jens 5483606f74 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@229 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 18:14:31 +00:00
jens 4e2cb68237 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@228 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 17:08:38 +00:00
jens 8d0bb58b5d - Coeff RAMs have no 'ce' for read 
git-svn-id: http://moon:8086/svn/vhdl/trunk@227 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 16:58:36 +00:00
jens bce7ba16b7 - Uses decimating CFIR (decimate by 2) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@226 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 15:44:07 +00:00
jens 7649b3fff0 deleted 
git-svn-id: http://moon:8086/svn/vhdl/trunk@225 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 15:31:42 +00:00
jens 16e7312df1 Initial version 
git-svn-id: http://moon:8086/svn/vhdl/trunk@224 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 15:31:32 +00:00
jens dd42e17b18 - decimating is now working 
git-svn-id: http://moon:8086/svn/vhdl/trunk@223 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 12:57:26 +00:00
jens 748bd9e52a - removed 'ce' 
git-svn-id: http://moon:8086/svn/vhdl/trunk@222 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 12:57:06 +00:00
jens c403b3b22d - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@221 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 21:16:38 +00:00
jens 9c45912627 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@220 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 19:22:25 +00:00
jens 170a65237b - Prepared with FIFO for decimating FIR 
git-svn-id: http://moon:8086/svn/vhdl/trunk@219 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 19:22:15 +00:00
jens 937e129a55 - reverted to 1.10 
- kept signal 'start' to trigger FIR process


git-svn-id: http://moon:8086/svn/vhdl/trunk@218 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 19:15:23 +00:00
jens d059cf8109 - new signal 'start' to trigger FIR process 
use din_vld for data load. This permits decimation FIR filtering


git-svn-id: http://moon:8086/svn/vhdl/trunk@217 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 17:40:32 +00:00
jens ffa4eb81ca - Lowpass prototype: omega is fraction of fs/2 
git-svn-id: http://moon:8086/svn/vhdl/trunk@216 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 08:56:38 +00:00
jens 04e1b6fcbf - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@215 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-09 11:50:57 +00:00
jens 8106295641 - added unfiltered output at ddc for eval 
git-svn-id: http://moon:8086/svn/vhdl/trunk@214 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-09 11:50:40 +00:00
jens 5f40d70789 - coef input registered 
git-svn-id: http://moon:8086/svn/vhdl/trunk@213 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-08 10:25:45 +00:00
jens 83a9b4c417 - changed iterative CFIR wirh semi-parallel version 
git-svn-id: http://moon:8086/svn/vhdl/trunk@212 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-06 21:20:29 +00:00
jens a98a8bb0ba - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@211 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-06 21:15:45 +00:00
jens 590734078c - added assertion check for min coef_latency 
git-svn-id: http://moon:8086/svn/vhdl/trunk@210 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-06 10:14:38 +00:00
jens 0ed5461442 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@209 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 10:54:55 +00:00
jens c46a1caaf5 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@208 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 10:15:53 +00:00
jens 9c12bc9640 - added RAM-based architecture 
git-svn-id: http://moon:8086/svn/vhdl/trunk@207 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 10:06:37 +00:00
jens 90a889a5f8 - use RAM-based delayline 
git-svn-id: http://moon:8086/svn/vhdl/trunk@206 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 10:06:14 +00:00
jens 245c01ad45 - fixed missing CE at yout 
git-svn-id: http://moon:8086/svn/vhdl/trunk@205 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 09:32:43 +00:00
jens 9832fbfac9 - added dedicated DPRAM for COEFFS 
git-svn-id: http://moon:8086/svn/vhdl/trunk@204 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 09:32:27 +00:00
jens 650e5db110 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@203 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 16:34:02 +00:00
jens 58257266ad - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@202 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 16:14:14 +00:00
jens c10463c961 - removed reset from fir_stage_sys 
git-svn-id: http://moon:8086/svn/vhdl/trunk@201 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 16:13:58 +00:00
jens e4dc3e69a1 - fixed rdy-signal 
git-svn-id: http://moon:8086/svn/vhdl/trunk@200 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 15:31:46 +00:00
jens 9a756d4ca8 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@199 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 15:31:20 +00:00
jens f05c6bb829 - input data rate can be lower than filter 
git-svn-id: http://moon:8086/svn/vhdl/trunk@198 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 15:16:06 +00:00
jens fe60d9d7a4 - added shift_en input 
git-svn-id: http://moon:8086/svn/vhdl/trunk@197 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 15:15:54 +00:00
jens 9675773b2a - added ce 
git-svn-id: http://moon:8086/svn/vhdl/trunk@196 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 14:00:06 +00:00
jens 1738a6c0b6 - minor mods to accu_ld_pipe 
git-svn-id: http://moon:8086/svn/vhdl/trunk@195 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 13:56:07 +00:00
jens bc4c015150 - minor mods to vld_pipe 
git-svn-id: http://moon:8086/svn/vhdl/trunk@194 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-03 20:33:42 +00:00
jens d28b2225a7 - uses only fir_pkg and filter_pkg for FIR 
git-svn-id: http://moon:8086/svn/vhdl/trunk@193 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-03 20:13:55 +00:00
jens fcdbc0e601 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@192 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-03 20:06:07 +00:00
jens 690c6c24f6 - bug fix coef-pipe 
git-svn-id: http://moon:8086/svn/vhdl/trunk@191 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-03 20:05:04 +00:00
jens ba703d81df - simplification for coef-array 
git-svn-id: http://moon:8086/svn/vhdl/trunk@190 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:48:36 +00:00
jens 0ed3e397f2 - using fir_stage_sys instead of fir_stage 
git-svn-id: http://moon:8086/svn/vhdl/trunk@189 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:23:04 +00:00
jens eb818a15bb - added coef_latency 
git-svn-id: http://moon:8086/svn/vhdl/trunk@188 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:22:28 +00:00
jens a165d37bb7 - added coef_latency 
- y_dout registered


git-svn-id: http://moon:8086/svn/vhdl/trunk@187 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:22:12 +00:00
jens c574f7f0fd - moved fixed_array_t to fixed_util_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@186 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:21:11 +00:00
jens a10614df0a - fix ntaps_bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@185 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:20:48 +00:00
jens 5f1b2738de - moved real_array_t to fixed_util_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@184 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:20:21 +00:00
jens d7ed0a9fb0 - added CFIR 
git-svn-id: http://moon:8086/svn/vhdl/trunk@183 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:19:08 +00:00
jens 655cfb7f0d - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@182 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:18:38 +00:00
jens 55a702d6bd - moved real_array_t to fixed_util_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@181 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:07:16 +00:00
jens e8ddaf8d98 - added real veriants of NextPower... 
git-svn-id: http://moon:8086/svn/vhdl/trunk@180 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 15:28:01 +00:00
jens 377b8c0993 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@179 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-31 15:54:51 +00:00
jens 8c652af1a7 - removed sproto-calls due to crashes in synth tools 
git-svn-id: http://moon:8086/svn/vhdl/trunk@178 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-31 11:23:50 +00:00
jens 18641b8411 - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@177 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 19:37:56 +00:00
jens dc63b8df76 - Ratio and gain are set at synthesis time (simpler) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@176 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 18:56:12 +00:00
jens 7c7fc19162 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@175 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 18:54:21 +00:00
jens c11d040f68 - added register after scaler 
git-svn-id: http://moon:8086/svn/vhdl/trunk@174 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 06:24:39 +00:00
jens 4cd2e0fd19 - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@173 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 06:04:19 +00:00
jens 61d5c40cd2 - uses ieee_proposed.fixed_pkg 
- din scaled to more fraction precision at integrator input.
  Number of integer bits are the same as din
- min_gain intrduced (reduces complexity of barrel shifter).
 Din always constant scaled by min_gain.


git-svn-id: http://moon:8086/svn/vhdl/trunk@172 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 06:03:56 +00:00
jens 75f8ddd340 - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@171 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 05:35:51 +00:00
jens 8136d54172 - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@170 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 05:21:52 +00:00
jens 50e4d2d32a - combine in/out_width to max_width 
- uses ieee_proposed.fixed_pkg


git-svn-id: http://moon:8086/svn/vhdl/trunk@169 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 04:39:46 +00:00
jens c45b123bdb - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@168 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 04:32:32 +00:00
jens 4fe3a1c636 - combine in/out_width to max_width 
- uses ieee_proposed.fixed_pkg


git-svn-id: http://moon:8086/svn/vhdl/trunk@167 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 04:32:07 +00:00
jens d9ba866ed0 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@166 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-29 14:05:12 +00:00
jens f7e19d3d44 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@165 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 21:43:27 +00:00
jens fb625665d2 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@164 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 19:04:18 +00:00
jens ef5da14068 - uses now fixed_util_pkg for common functions 
git-svn-id: http://moon:8086/svn/vhdl/trunk@163 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:55:15 +00:00
jens f3c6c4c644 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@162 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:49:28 +00:00
jens 64cb0bb426 - uses now fixed_util_pkg for common functions 
git-svn-id: http://moon:8086/svn/vhdl/trunk@161 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:48:15 +00:00
jens 4735454c40 - moved common functions to fixed_util_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@160 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:47:54 +00:00
jens 0e4e1b0fba - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@159 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:41:04 +00:00
jens d9961e9efb - use now non-debug-versions (NCO) for TB 
git-svn-id: http://moon:8086/svn/vhdl/trunk@158 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:35:52 +00:00
jens be85922612 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@157 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:35:44 +00:00
jens 1e9bed13e5 - added CIC-decimator 
git-svn-id: http://moon:8086/svn/vhdl/trunk@156 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:30:56 +00:00
jens 28bd8e959d - use now non-debug-versions (NCO, MIX) for TB 
git-svn-id: http://moon:8086/svn/vhdl/trunk@155 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:30:28 +00:00
jens 860e2984fd - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@154 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:29:13 +00:00
jens 13df4bbf12 - added generic for fractional number of bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@153 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:29:03 +00:00
jens 9a7ffd09ac - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@152 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:28:38 +00:00
jens 21e3023bfb - added generic for fractional number of bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@151 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 10:44:31 +00:00
jens 2903f5b7f1 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@150 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 09:59:41 +00:00
jens 6e65134b53 - added generic for fractional number of bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@149 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 09:57:01 +00:00
jens 4bb7087b60 - added generic for fractional number of bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@148 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 09:39:16 +00:00
jens de9ad2d469 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@147 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 09:38:44 +00:00
jens 988b2ed138 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@146 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 19:54:37 +00:00
jens 50af9fe70d - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@145 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 19:53:00 +00:00
jens bf78b1beef - added debug_mix_t 
git-svn-id: http://moon:8086/svn/vhdl/trunk@144 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 19:52:20 +00:00
jens fbee2fe578 - changed z-range default to 1.0 
git-svn-id: http://moon:8086/svn/vhdl/trunk@143 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 19:51:42 +00:00
jens 080e286b1c - fixed valid_out signal for gain_corr=disabled 
git-svn-id: http://moon:8086/svn/vhdl/trunk@142 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:39:05 +00:00
jens 32e4a933b9 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@141 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:38:05 +00:00
jens 15645ec096 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@140 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:21:10 +00:00
jens 776094e4b2 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@139 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:18:22 +00:00
jens 8e6affa627 - renamed 
git-svn-id: http://moon:8086/svn/vhdl/trunk@138 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:16:09 +00:00
jens 27b1d6a426 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@137 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:15:49 +00:00
jens bb5f153651 - reduced lower spur boundary 
git-svn-id: http://moon:8086/svn/vhdl/trunk@136 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:15:31 +00:00
jens a2e01a7966 - added Tpd to 'dout' for sim 
git-svn-id: http://moon:8086/svn/vhdl/trunk@135 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-11-05 09:34:56 +00:00
jens b4392a5c7a - added AC-97 controller 
git-svn-id: http://moon:8086/svn/vhdl/trunk@134 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-11-01 21:52:59 +00:00
jens 5091040c1d - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@133 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-11-01 21:48:26 +00:00
jens 755b318e7a - added AC-97 controller 
git-svn-id: http://moon:8086/svn/vhdl/trunk@132 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-11-01 21:47:15 +00:00
jens a41b5f572a - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@131 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-27 00:00:12 +00:00
jens ba2d02d4e6 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@130 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 23:52:49 +00:00
jens a14c98c05f - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@129 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 23:36:00 +00:00
jens 529658b710 - fixed some bugs 
git-svn-id: http://moon:8086/svn/vhdl/trunk@128 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 23:17:57 +00:00
jens 11129059e7 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@127 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 21:30:42 +00:00
jens 1f03bb3d41 - fixed some bugs 
git-svn-id: http://moon:8086/svn/vhdl/trunk@126 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 10:04:44 +00:00
jens b0a0e4ae6c - fixed some bugs 
git-svn-id: http://moon:8086/svn/vhdl/trunk@125 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 09:57:32 +00:00
jens c10be79075 - fixed some bugs 
git-svn-id: http://moon:8086/svn/vhdl/trunk@124 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 09:46:49 +00:00
jens 6b38a0acba - removed delay at color output. Fixes image problems. 
git-svn-id: http://moon:8086/svn/vhdl/trunk@123 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 20:11:03 +00:00
jens 84255df928 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@122 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 18:09:39 +00:00
jens 9954268b22 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@120 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:40:42 +00:00
jens 6597bccd01 - using now dpram_1w1r 
git-svn-id: http://moon:8086/svn/vhdl/trunk@119 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:26:07 +00:00
jens a6c7859e22 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@118 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:23:04 +00:00
jens 1c7fd9022e - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@117 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:20:15 +00:00
jens 5120448104 - using bui-generics for cache sizes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@116 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:16:21 +00:00
jens 8e41790680 - added generics for cache sizes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@115 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:16:05 +00:00
jens 08317c7744 - Removed DEADBEEF-garbage 
git-svn-id: http://moon:8086/svn/vhdl/trunk@114 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:09:13 +00:00
jens 9918af8a12 - Removed dirty-bit which is not needed by Direct-Mapped Cache 
git-svn-id: http://moon:8086/svn/vhdl/trunk@113 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:08:37 +00:00
jens 8102a16c3c - Removed linefifo 
- Uses now lib/FIFO/fifo_async.vhd


git-svn-id: http://moon:8086/svn/vhdl/trunk@112 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 12:27:38 +00:00
jens ed47f478f8 - Switched to 64-Bit SDRAM- and VGA-controller 
git-svn-id: http://moon:8086/svn/vhdl/trunk@110 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:48:04 +00:00
jens 7cdfa6929d - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@109 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:26:06 +00:00
jens 16b4f2b138 - Bugfix: changed 'ptr_r' from 'bcnt_r' to 'bnxt_r' to prevent read delay when FIFO is read (re = 1) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@108 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:21:47 +00:00
jens 7ccefbab86 - Removed linefifo 
- Uses now lib/FIFO/fifo_async.vhd


git-svn-id: http://moon:8086/svn/vhdl/trunk@107 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:15:26 +00:00
jens 5abe0f9234 -Removed linefifo.vhd and dpram.vhd 
- Uses now lib/FIFO/fifo_async.vhd


git-svn-id: http://moon:8086/svn/vhdl/trunk@106 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:14:50 +00:00
jens 29eb6a05c3 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@105 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:11:52 +00:00
jens 2c95fae0ab - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@104 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 00:23:56 +00:00
jens 545379c99d - added conversion functions unsigned <=> color_t 
git-svn-id: http://moon:8086/svn/vhdl/trunk@103 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 00:15:29 +00:00
jens 533a0bd328 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@102 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-24 20:56:28 +00:00
jens b81ce94c39 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@101 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-24 20:56:13 +00:00
jens 48c7618752 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@100 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 22:06:41 +00:00
jens 5c63d629a7 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@99 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 22:06:34 +00:00
jens 36e8cd1e00 - Using MODELSIM_HOME environment variable 
git-svn-id: http://moon:8086/svn/vhdl/trunk@98 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 21:21:24 +00:00
jens c90b63d476 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@97 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 21:20:28 +00:00
jens 41593cbc54 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@96 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 09:49:42 +00:00
jens 0bba7d2e10 - added area constraint for "inst_mips_top" 
git-svn-id: http://moon:8086/svn/vhdl/trunk@95 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-22 09:47:34 +00:00
jens a5f0a35f80 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@94 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 19:32:11 +00:00
jens 5bd0c6ea4a - Update 
git-svn-id: http://moon:8086/svn/vhdl/trunk@93 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 19:29:57 +00:00
jens 1929d9374e - Removed User ROM stuff 
git-svn-id: http://moon:8086/svn/vhdl/trunk@92 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 18:52:14 +00:00
jens c9900e509a - Loading app from Flash instead User ROM 
- Removed User ROM


git-svn-id: http://moon:8086/svn/vhdl/trunk@91 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 18:24:56 +00:00
jens 029bf8eb22 - changed some directories 
git-svn-id: http://moon:8086/svn/vhdl/trunk@90 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 18:24:03 +00:00
jens 8060efb864 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@89 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 18:23:29 +00:00
jens 3f62f79d12 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@88 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 17:23:58 +00:00
jens fdc3664187 Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@87 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-20 19:26:51 +00:00
jens 69697d7222 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@86 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-20 19:26:01 +00:00
jens 419ccc4edf Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@85 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-20 19:11:30 +00:00
jens b67911c65d - added TM_NET for DDR-clock 
git-svn-id: http://moon:8086/svn/vhdl/trunk@84 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-20 09:55:32 +00:00
jens e9e132b3e6 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@83 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:53:51 +00:00
jens 32cbb4fc13 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@82 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:29:45 +00:00
jens 9e404bfb06 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@81 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:12:34 +00:00
jens 0ea7ced5e3 - Removed linefifo and clockgen (=> frontend and top) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@80 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:11:46 +00:00
jens de0a8c6e17 Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@79 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:10:51 +00:00
jens f59e4dd7d1 - Added Sync. SRAM 
git-svn-id: http://moon:8086/svn/vhdl/trunk@78 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 20:23:27 +00:00
jens 85bf744892 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@77 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 20:13:28 +00:00
jens 891e764a23 - Added VGA 
git-svn-id: http://moon:8086/svn/vhdl/trunk@76 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 20:03:28 +00:00
jens 20b3bfb41b - Added Sync. SRAM 
git-svn-id: http://moon:8086/svn/vhdl/trunk@75 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 20:02:45 +00:00
jens 8a8adce98e - using now 64-bit SDR interface (2 SDRAMS) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@74 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 13:31:15 +00:00
jens 051b4182f1 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@73 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 12:49:30 +00:00
jens 3685973be8 - using now 64-bit SDR interface (2 SDRAMS) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@72 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 11:37:01 +00:00
jens b656e2890b Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@71 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 11:36:33 +00:00
jens f50a47246a - introduced per-bank activation (avoids multiple activations on same bank) 
- some other improvements


git-svn-id: http://moon:8086/svn/vhdl/trunk@70 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 11:36:07 +00:00
jens c104c6e67d - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@68 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 17:41:44 +00:00
jens c96015bbad - Removed distributed DPRAM reference 
git-svn-id: http://moon:8086/svn/vhdl/trunk@67 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 17:41:15 +00:00
jens fe372f0efa - Removed registered CYC_O (didn't work) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@66 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 17:35:07 +00:00
jens 61b2095bf8 - Shortened read cycles 
- Minor improvements


git-svn-id: http://moon:8086/svn/vhdl/trunk@65 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 14:26:02 +00:00
jens 329c639c1a - Shortened BUS-cycle by one clock 
git-svn-id: http://moon:8086/svn/vhdl/trunk@64 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 14:25:30 +00:00
jens f8962066f0 - Registered CYC_O 
git-svn-id: http://moon:8086/svn/vhdl/trunk@63 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 13:39:07 +00:00
jens 1c499c6b34 - Added VGA master/slave 
git-svn-id: http://moon:8086/svn/vhdl/trunk@62 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-16 23:12:14 +00:00
jens 225e0d5eeb - Added VGA component 
git-svn-id: http://moon:8086/svn/vhdl/trunk@61 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-15 21:55:34 +00:00
jens f960a13953 Simplified 
git-svn-id: http://moon:8086/svn/vhdl/trunk@60 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-15 11:16:47 +00:00
jens c8da959dbb - Moved to lib/FIFO 
git-svn-id: http://moon:8086/svn/vhdl/trunk@59 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 17:12:22 +00:00
jens 78db345b82 - Intital revision 
- Moved from SDRAM v1.5 to here


git-svn-id: http://moon:8086/svn/vhdl/trunk@58 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 17:11:50 +00:00
jens fda12e53c3 - Uses now full capacity of SDRAM (64-Bit interface on ML-402) 
- Removed read data mask


git-svn-id: http://moon:8086/svn/vhdl/trunk@57 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 17:09:30 +00:00
jens 40d96126e7 - Removed read data mask 
git-svn-id: http://moon:8086/svn/vhdl/trunk@56 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 17:07:48 +00:00
jens 959217a81c Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@55 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 14:55:15 +00:00
jens 91347dd60e - Output pre_empty and pre_full for safer DPRAM control 
git-svn-id: http://moon:8086/svn/vhdl/trunk@54 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-12 18:04:36 +00:00
jens 3be3800dc7 Registered rdy (better timing) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@53 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-12 14:12:14 +00:00
jens 0bc9ef0b00 - Simplfied (better timing) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@51 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-12 12:50:01 +00:00
jens 5694dddd9f - Changed we to be 
- Changed r_wn to we


git-svn-id: http://moon:8086/svn/vhdl/trunk@50 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-12 11:02:41 +00:00
jens b47d55d61f Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@49 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-12 11:01:40 +00:00
jens 14489d80e9 Bug fix: Uncached read and buffer write in different state 
git-svn-id: http://moon:8086/svn/vhdl/trunk@48 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-11 20:14:54 +00:00
jens de6bd8f29c Bug fix: Address and data latch only if ready 
git-svn-id: http://moon:8086/svn/vhdl/trunk@47 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-11 20:13:52 +00:00
jens b6309838f1 Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@46 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-10 21:33:10 +00:00
jens 25a276d19b Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@45 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-10 21:31:24 +00:00
jens f1e2601c27 Added bus fifo and write fifo 
git-svn-id: http://moon:8086/svn/vhdl/trunk@44 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-10 21:30:42 +00:00
jens c17d99dc2b Added instant RAW avoidance 
git-svn-id: http://moon:8086/svn/vhdl/trunk@43 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-10 21:28:58 +00:00
jens b3684f6403 deleted 
git-svn-id: http://moon:8086/svn/vhdl/trunk@42 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-10 21:27:32 +00:00
jens 1afb05d18a Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@41 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-10 21:25:58 +00:00
84 changed files with 3340 additions and 18602 deletions
Expand all files Collapse all files
lib/CPUs/MIPS/sim/ModelSim SE .lnk
BIN
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lib/CPUs/MIPS/sim/compile_simprim.do
-6
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@@ -1,6 +0,0 @@
vlib simprim
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
lib/CPUs/MIPS/sim/compile_unisim.do
-6
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@@ -1,6 +0,0 @@
vlib unisim
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo
-13
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@@ -1,13 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/tb_eval_muldiv.vhd"
vsim -t 1ps -lib work tb_eval_muldiv
do {tb_eval_muldiv.wdo}
view wave
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo
-27
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@@ -1,27 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_eval_muldiv/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0}
configure wave -namecolwidth 149
configure wave -valuecolwidth 171
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {2520 ns}
lib/CPUs/MIPS/sim/tb_mips_embedded.fdo
-22
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@@ -1,22 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
vcom -explicit -93 "../src/core/mips_reg.vhd"
vcom -explicit -93 "../src/core/mips_shifter.vhd"
vcom -explicit -93 "../src/core/mips_alu.vhd"
vcom -explicit -93 "../src/core/mips_bcu.vhd"
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
vcom -explicit -93 "../src/core/mips_top.vhd"
vcom -explicit -93 "../src/ram.vhd"
vcom -explicit -93 "../asm/fibonacci.vhd"
vcom -explicit -93 "../src/mips_embedded.vhd"
vcom -explicit -93 "../src/tb_mips_embedded.vhd"
vsim -t 1ps -lib work tb_mips_embedded
do {tb_mips_embedded.wdo}
view wave
view structure
view signals
run 20us
lib/CPUs/MIPS/sim/tb_mips_embedded.wdo
-41
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@@ -1,41 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_embedded/rst
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Logic /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/exception
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_ram/sram
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_dout
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_re
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_din
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/wb_stage
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/hdu
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {624000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {2520 ns}
lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo
-31
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@@ -1,31 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
vcom -explicit -93 "../src/core/mips_reg.vhd"
vcom -explicit -93 "../src/core/mips_shifter.vhd"
vcom -explicit -93 "../src/core/mips_alu.vhd"
vcom -explicit -93 "../src/core/mips_bcu.vhd"
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
vcom -explicit -93 "../src/core/mips_muldiv.vhd"
vcom -explicit -93 "../src/core/mips_cop.vhd"
vcom -explicit -93 "../src/core/mips_bui.vhd"
vcom -explicit -93 "../src/core/mips_top.vhd"
vcom -explicit -93 "../src/core/dcache.vhd"
vcom -explicit -93 "../asm/testbench.ROM.vhd"
vcom -explicit -93 "../src/mips_embedded.vhd"
vcom -explicit -93 "../src/mips_embedded_syn.vhd"
vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../uart/uart_rx.vhd"
vcom -explicit -93 "../../../uart/uart_tx.vhd"
vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd"
vsim -t 1ps -lib work tb_mips_embedded_syn
do {tb_mips_embedded_syn.wdo}
view wave
view structure
view signals
run 100us
lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo
-13
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@@ -1,13 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../syn/ise9/netgen/par/mips_embedded_syn_timesim.vhd"
vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd"
vsim -t 1ps -sdfmax "/uut=../syn/ise9/netgen/par/mips_embedded_syn_timesim.sdf" -lib work tb_mips_embedded_syn
do {tb_mips_embedded_syn.wdo}
view wave
#add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo
-112
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@@ -1,112 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_rx
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_tx
add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_rst_n_in
add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_clk_in
add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_led
add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_dip
add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_btn
add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_error
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_rst
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_run
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_tx
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_ctrl
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_baud
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/uart_status_port
add wave -noupdate -format Literal -radix decimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_sec
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_rdy
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_en
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_re
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_dout
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_bui/s
add wave -noupdate -divider DMEM
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_dout
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_en
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_we
add wave -noupdate -divider IMEM
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/imem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_din
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_en
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc_run
add wave -noupdate -divider PC
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/hdu
add wave -noupdate -divider Stages
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/halt
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_reg_dual_a/reg_mem
add wave -noupdate -divider Cop
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ir_valid
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_id
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_ex
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_ex_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_entered
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/epc
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cause
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/events
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/eflags
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/badvaddr
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/rst
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exception
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_save
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_rest
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_strobe
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ip
add wave -noupdate -divider Stages
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_dout
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/wb_stage
add wave -noupdate -divider Muldiv
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/result
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/start
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/busy
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/hilo_sel
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_hi
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_lo
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1121030000 ps} 0} {{Cursor 2} {1436367 ps} 0} {{Cursor 3} {1122030000 ps} 0}
configure wave -namecolwidth 179
configure wave -valuecolwidth 89
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {1351336 ps} {1583596 ps}
lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo
+1 -1
View File
@@ -12,4 +12,4 @@ view wave
view structure
view signals
run 5000us
run 8ms
lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo
-19
View File
@@ -1,19 +0,0 @@
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit -93 "../syn/eval_muldiv/netgen/translate/muldiv_translate.vhd"
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/tb_mips_muldiv.vhd"
vsim -t 1ps -lib work tb_mips_muldiv
#do {tb_mips_muldiv.udo}
view wave
add wave *
view structure
view signals
run 1000ns
## End
lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo
-19
View File
@@ -1,19 +0,0 @@
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit -93 "../syn/eval_muldiv/netgen/synthesis/muldiv_synthesis.vhd"
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/tb_mips_muldiv.vhd"
vsim -t 1ps -lib work tb_mips_muldiv
do {tb_mips_muldiv.wdo}
view wave
#add wave *
view structure
view signals
run 1000ns
## End
lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo
+5 -6
View File
@@ -6,16 +6,15 @@ add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn
add wave -noupdate -format Logic /tb_mips_muldiv/start
add wave -noupdate -format Logic /tb_mips_muldiv/busy
add wave -noupdate -format Logic /tb_mips_muldiv/s_un
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/result
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/md_result
add wave -noupdate -format Logic /tb_mips_muldiv/check
add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
@@ -62,7 +61,7 @@ add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {1278050000 ps} 0}
WaveRestoreCursors {{Cursor 1} {7735999838 ps} 0} {{Cursor 2} {512321 ps} 0}
configure wave -namecolwidth 149
configure wave -valuecolwidth 171
configure wave -justifyvalue left
@@ -76,4 +75,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {5250 us}
WaveRestoreZoom {0 ps} {8400 us}
lib/CPUs/MIPS/sim/tb_mips_top.fdo
+39 -4
View File
@@ -1,22 +1,57 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
# RAMS
vcom -explicit -93 "../../../misc/dpram_2w2r.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
# FIFOS
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd"
# UART
vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../uart/uart_rx.vhd"
vcom -explicit -93 "../../../uart/uart_tx.vhd"
vcom -explicit -93 "../../../uart/uart_wb.vhd"
# GPIO
vcom -explicit -93 "../../../misc/gpio_wb.vhd"
# Async port
vcom -explicit -93 "../../../misc/async_types.vhd"
vcom -explicit -93 "../../../misc/async_port_wb.vhd"
vcom -explicit -93 "../src/async_defs.vhd"
# ROM
vcom -explicit -93 "../src/bootloader.ROM.vhd"
vcom -explicit -93 "../../../misc/rom_wb.vhd"
# MIPS
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
vcom -explicit -93 "../src/core/mips_reg.vhd"
vcom -explicit -93 "../src/core/mips_shifter.vhd"
vcom -explicit -93 "../src/core/mips_alu.vhd"
vcom -explicit -93 "../src/core/mips_muldiv.vhd"
vcom -explicit -93 "../src/core/mips_cop.vhd"
vcom -explicit -93 "../src/core/mips_icache.vhd"
vcom -explicit -93 "../src/core/mips_dcache.vhd"
vcom -explicit -93 "../src/core/mips_biu.vhd"
vcom -explicit -93 "../src/core/mips_bcu.vhd"
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
vcom -explicit -93 "../src/core/mips_top.vhd"
vcom -explicit -93 "../asm/fibonacci.vhd"
vcom -explicit -93 "../src/ram.vhd"
vcom -explicit -93 "../src/tb_mips_top.vhd"
vsim -t 1ps -lib work tb_mips_top
do {tb_mips_top.wdo}
view wave
view structure
view signals
run 40000ns
run 1600us
lib/CPUs/MIPS/sim/tb_mips_top.mdo
-18
View File
@@ -1,18 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
## Compile Post-Map Model
vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_map.vhd"
vsim -t 1ps -sdfmax "/mips_top=../syn/ise9/netgen/map/mips_top_map.sdf" -lib work mips_top
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/irom_hello.vhd"
vcom -explicit -93 "../src/tb_mips_top.vhd"
vsim -t 1ps -lib work tb_mips_top
do {tb_mips_top.mwdo}
view wave
#add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_mips_top.mwdo
-31
View File
@@ -1,31 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_top/rst
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Logic /tb_mips_top/ce
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
add wave -noupdate -format Logic /tb_mips_top/dmem_we
add wave -noupdate -format Logic /tb_mips_top/dmem_re
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_op2
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_result
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {77481 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {729730 ps}
lib/CPUs/MIPS/sim/tb_mips_top.sdo
-16
View File
@@ -1,16 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../syn/ise9/netgen/synthesis/mips_top_synthesis.vhd"
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/irom_hello.vhd"
vcom -explicit -93 "../src/tb_mips_top.vhd"
vsim -t 1ps -lib work tb_mips_top
#do {tb_mips_top.wdo}
view wave
add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_mips_top.wdo
+37 -21
View File
@@ -1,40 +1,56 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_top/rst
add wave -noupdate -divider {TOP interface}
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Logic /tb_mips_top/cpu_halt
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
add wave -noupdate -format Logic /tb_mips_top/dmem_re
add wave -noupdate -format Logic /tb_mips_top/dmem_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram
add wave -noupdate -format Literal /tb_mips_top/debug
add wave -noupdate -format Logic /tb_mips_top/stb_o
add wave -noupdate -format Logic /tb_mips_top/ack_i
add wave -noupdate -format Logic /tb_mips_top/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
add wave -noupdate -format Logic /tb_mips_top/we_o
add wave -noupdate -format Literal /tb_mips_top/sel_o
add wave -noupdate -format Logic /tb_mips_top/cyc_o
add wave -noupdate -format Logic /tb_mips_top/mrdy_o
add wave -noupdate -format Literal /tb_mips_top/int
add wave -noupdate -divider {External components}
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Logic /tb_mips_top/rx
add wave -noupdate -format Logic /tb_mips_top/tx
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal /tb_mips_top/mem_area
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
add wave -noupdate -divider ALU
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -divider PC
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall
add wave -noupdate -divider PC
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
add wave -noupdate -format Logic /tb_mips_top/clk
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
WaveRestoreCursors {{Cursor 1} {1199854590 ps} 0}
configure wave -namecolwidth 188
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -48,4 +64,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {42 us}
WaveRestoreZoom {0 ps} {1260 us}
lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo
-17
View File
@@ -1,17 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
## Compile Post-Map Model
vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_syn_map.vhd"
vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/map/mips_top_syn_map.sdf" -lib work mips_top_syn
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/irom_hello.vhd"
vcom -explicit -93 "../src/tb_mips_top_syn.vhd"
vsim -t 1ps -lib work tb_mips_top_syn
do {tb_mips_top_syn.wdo}
view wave
#add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo
-17
View File
@@ -1,17 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
## Compile Post-Map Model
vcom -explicit -93 "../syn/ise9/netgen/par/mips_top_syn_timesim.vhd"
vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/par/mips_top_syn_timesim.sdf" -lib work mips_top_syn
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/irom_hello.vhd"
vcom -explicit -93 "../src/tb_mips_top_syn.vhd"
vsim -t 1ps -lib work tb_mips_top_syn
do {tb_mips_top_syn.wdo}
view wave
#add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo
-31
View File
@@ -1,31 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_top_syn/rst
add wave -noupdate -format Logic /tb_mips_top_syn/clk
add wave -noupdate -format Logic /tb_mips_top_syn/ce
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_data
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_addr
add wave -noupdate -format Logic /tb_mips_top_syn/dmem_we
add wave -noupdate -format Logic /tb_mips_top_syn/dmem_re
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_id_stage_boff
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_stage_ex_inst_alu_sum_res
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top_syn/sram
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {118199 ps} 0}
configure wave -namecolwidth 188
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {2520 ns}
lib/CPUs/MIPS/tools/irom.vhd.tpl → lib/CPUs/MIPS/src/async_defs.vhd
+37 -6
View File
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
-- Project: MIPS System controller
-- This file:
--
-- Copyright (C) 2008 J. Ahrensfeld
--
@@ -21,9 +21,40 @@
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-- ROM_INSERT_HERE
use work.async_types.all;
package async_defs is
constant ts_flash : async_timespec_t :=
(
ncyc_access => 1,
ncyc_pulse_rd => 12,
ncyc_pulse_wr => 7,
ncyc_cs_hold => 1,
ncyc_release => 1,
ncyc_pulse_rst => 8,
pol_cs => '0',
pol_oe => '0',
pol_we => '0',
pol_rst => '0'
);
constant ts_sram : async_timespec_t :=
(
ncyc_access => 1,
ncyc_pulse_rd => 12,
ncyc_pulse_wr => 7,
ncyc_cs_hold => 1,
ncyc_release => 1,
ncyc_pulse_rst => 8,
pol_cs => '0',
pol_oe => '0',
pol_we => '0',
pol_rst => '0'
);
end async_defs;
lib/CPUs/MIPS/src/bootloader.ROM.vhd
+2082
View File
File diff suppressed because it is too large Load Diff
lib/CPUs/MIPS/src/core/dcache.vhd
+59 -58
View File
@@ -24,8 +24,8 @@ ENTITY dcache IS
CYC_O : out STD_LOGIC;
en : in STD_LOGIC;
cpu_en : in STD_LOGIC;
cpu_r_wn : in STD_LOGIC;
cpu_we : in unsigned(3 downto 0);
cpu_we : in STD_LOGIC;
cpu_be : in unsigned(3 downto 0);
cpu_addr : in word_t;
cpu_din : in word_t;
cpu_dout : out word_t;
@@ -92,14 +92,13 @@ END COMPONENT;
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
constant tag_parity_width : natural := 3;
constant tram_data_width : natural := 2 + tag_parity_width + tag_width;
constant tram_data_width : natural := 1 + tag_parity_width + tag_width;
constant tram_addr_width : natural := cache_index_width;
subtype tram_data_t is unsigned (tram_data_width-1 downto 0);
type dcache_entry_t is record
valid : std_logic;
dirty : std_logic;
tv_p : unsigned(tag_parity_width-1 downto 0);
tag : unsigned(tag_width-1 downto 0);
end record;
@@ -112,9 +111,8 @@ END COMPONENT;
variable result : dcache_entry_t;
begin
result.valid := x(0);
result.dirty := x(1);
result.tv_p := x(4 downto 2);
result.tag := x(tag_width+4 downto 5);
result.tv_p := x(3 downto 1);
result.tag := x(tag_width+3 downto 4);
return result;
end to_dcache_entry;
@@ -123,19 +121,17 @@ END COMPONENT;
variable result : tram_data_t;
begin
result(0) := x.valid;
result(1) := x.dirty;
result(4 downto 2) := x.tv_p;
result(tag_width+4 downto 5) := x.tag;
result(3 downto 1) := x.tv_p;
result(tag_width+3 downto 4) := x.tag;
return result;
end to_tram_data;
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache, wr_cache);
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
signal s, sn : cache_state_t;
signal cache_busy : std_logic;
signal cache_read_miss : std_logic;
signal cache_write_miss : std_logic;
signal cache_hit : std_logic;
signal tag_match : std_logic;
signal word_index_reg : unsigned(word_index_width-1 downto 0);
signal cache_index_reg : unsigned(cache_index_width-1 downto 0);
@@ -147,15 +143,16 @@ END COMPONENT;
signal cpu_dram_dout : word_t;
signal cpu_dram_din : word_t;
signal cpu_data_reg : word_t;
signal cpu_we_reg : unsigned(3 downto 0);
signal ctrl_force_we : unsigned(3 downto 0);
signal cpu_was_write : std_logic;
signal cpu_be_reg : unsigned(3 downto 0);
signal cpu_we_reg : std_logic;
signal ctrl_dram_en : std_logic;
signal ctrl_dram_addr : unsigned(lg2(cache_size)-1 downto 0);
signal ctrl_dram_din : word_t;
signal ctrl_dram_we : unsigned(3 downto 0);
signal cpu_dram_we : unsigned(3 downto 0);
signal dram_en : std_logic;
signal cpu_was_en : std_logic;
signal cpu_dram_en : std_logic;
signal cpu_en2 : std_logic;
signal cpu_we2 : std_logic;
signal tram_addr_rd : unsigned(cache_index_width-1 downto 0);
signal tram_dout : tram_data_t;
@@ -174,44 +171,64 @@ END COMPONENT;
signal cpu_reg_en : std_logic;
signal was_miss : std_logic;
signal data_write : std_logic;
signal cpu_we2 : std_logic;
signal cpu_hit_we : std_logic;
signal instant_raw : std_logic;
begin
cpu_hit_we <= cpu_we2 and cache_hit;
cpu_index_reg:
cpu_index_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
cache_index_reg <= (others => '0');
tag_index_reg <= (others => '0');
cpu_was_write <= '0';
elsif cpu_reg_en = '1' and en = '1' then
elsif cpu_reg_en = '1' and en = '1' and instant_raw = '0' then
word_index_reg <= cpu_word_index;
cache_index_reg <= cpu_cache_index;
tag_index_reg <= cpu_tag;
cpu_data_reg <= cpu_din;
cpu_we_reg <= cpu_we;
cpu_was_write <= not cpu_r_wn;
end if;
end if;
end process;
cpu_was_wr_reg:
cpu_data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cpu_was_en <= '0';
if RST_I = '1' then
cpu_we_reg <= '0';
elsif cpu_reg_en = '1' and en = '1' then
cpu_data_reg <= cpu_din;
cpu_be_reg <= cpu_be;
cpu_we_reg <= cpu_we;
end if;
end if;
end process;
cpu_was_wr_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cpu_en2 <= '0';
cpu_we2 <= '0';
if cpu_en = '1' and en = '1' then
cpu_we2 <= not cpu_r_wn;
cpu_was_en <= '1';
cpu_we2 <= cpu_we;
cpu_en2 <= '1';
cpu_dram_din <= cpu_din;
end if;
end if;
end process;
instant_raw_logic:
process(CLK_I)
begin
if rising_edge(CLK_I) then
instant_raw <= cpu_hit_we and cpu_en and en and not cpu_we;
end if;
end process;
inst_tag_ram : dpram_1w1r
GENERIC MAP (
addr_width => tram_addr_width,
@@ -241,8 +258,8 @@ gen_data_ram:
PORT MAP (
clk_a => CLK_I,
clk_b => CLK_I,
en_a => '1',
en_b => dram_en,
en_a => ctrl_dram_en,
en_b => '1',
we_a => ctrl_dram_we(i),
we_b => cpu_dram_we(i),
addr_a => ctrl_dram_addr,
@@ -266,24 +283,24 @@ cache_state_next:
end if;
end process;
cpu_busy <= cache_busy;
cpu_busy <= cache_busy or instant_raw;
cpu_dout <= cpu_dram_dout;
tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0';
cache_read_miss <= not (tag_match and cache_entry_out.valid) and not cpu_was_write;
cache_write_miss <= not (tag_match and cache_entry_out.valid and cpu_was_write);
cache_hit <= tag_match and cache_entry_out.valid;
tram_din <= to_tram_data(cache_entry_in);
tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
cache_entry_out <= to_dcache_entry(tram_dout);
cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg);
cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_hit_we = '0' and instant_raw = '0') else (cache_index_reg & word_index_reg);
ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
ctrl_dram_din <= DAT_I;
ctrl_dram_we <= (3 downto 0 => (data_write and ACK_I)) or ctrl_force_we;
cpu_dram_we <= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0');
ctrl_dram_we <= (others => '1');
ctrl_dram_en <= data_write and ACK_I;
cpu_dram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
cache_state:
process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, cpu_r_wn, SRDY_I, cpu_was_en, cpu_was_write, cpu_we_reg)
process(s, instant_raw, cache_hit, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg)
begin
cpu_reg_en <= '0';
cache_busy <= '1';
@@ -294,7 +311,6 @@ cache_state:
mem_index_count_rst <= '0';
CYC_O <= '0';
STB_O <= '0';
dram_en <= '0';
tram_re <= '0';
was_miss <= '0';
data_write <= '0';
@@ -302,8 +318,6 @@ cache_state:
cache_entry_in.tv_p <= (others => '0');
cache_entry_in.tag <= tag_index_reg;
cache_entry_in.valid <= '0';
cache_entry_in.dirty <= '0';
ctrl_force_we <= (others => '0');
sn <= s;
case s is
@@ -312,10 +326,9 @@ cache_state:
when ready =>
cache_busy <= '0';
cpu_reg_en <= '1';
dram_en <= cpu_en or cpu_was_en;
tram_re <= cpu_en;
if cpu_was_en = '1' then
if cache_read_miss = '1' then
if cpu_en2 = '1' then
if cache_hit = '0' and cpu_we_reg = '0' then
sn <= mem_request;
cpu_reg_en <= '0';
cache_busy <= '1';
@@ -332,8 +345,7 @@ cache_state:
sn <= ready;
if cpu_en = '1' then
cpu_reg_en <= '1';
dram_en <= '1';
tram_re <= '1';
tram_re <= '1';
end if;
end if;
when mem_request =>
@@ -362,26 +374,15 @@ cache_state:
end if;
end if;
when upd_cache =>
CYC_O <= '1';
tram_addr_wr <= cache_index_reg;
tram_we <= '1';
cache_entry_in.valid <= '1';
if cpu_was_write = '1' then
sn <= wr_cache;
else
sn <= rd_cache;
end if;
sn <= rd_cache;
when rd_cache =>
tram_re <= '1';
dram_en <= '1';
was_miss <= '1';
sn <= ready;
when wr_cache =>
tram_re <= '1';
ctrl_force_we <= cpu_we_reg;
sn <= ready;
when others =>
sn <= ready;
end case;
lib/CPUs/MIPS/src/core/icache.vhd
-2
View File
@@ -296,14 +296,12 @@ cache_state:
end if;
end if;
when upd_cache =>
CYC_O <= '1';
tag_ram_addr_wr <= cache_index_reg;
tag_ram_we <= '1';
cache_entry_in.valid <= '1';
sn <= rd_cache;
when rd_cache =>
-- CYC_O <= '1';
tag_ram_re <= '1';
data_ram_re <= '1';
was_miss <= '1';
lib/CPUs/MIPS/src/core/mips_bui.vhd
+218 -138
View File
@@ -28,7 +28,12 @@ use IEEE.numeric_std.ALL;
library work;
use work.mips_types.all;
entity bui is
entity biu is
Generic
(
icache_size : natural := 2048; -- words
dcache_size : natural := 2048 -- words
);
Port
(
RST_I : in STD_LOGIC;
@@ -51,21 +56,21 @@ entity bui is
cpu_dmem_err : out STD_LOGIC;
cpu_dmem_rdy : out STD_LOGIC;
cpu_dmem_en : in STD_LOGIC;
cpu_dmem_re : in STD_LOGIC;
cpu_dmem_we : in unsigned(3 downto 0);
cpu_dmem_we : in STD_LOGIC;
cpu_dmem_be : in unsigned(3 downto 0);
cpu_dmem_dout : in word_t;
cpu_dmem_din : out word_t;
cpu_dmem_addr : in word_t
);
end bui;
end biu;
architecture behavior of bui is
architecture behavior of biu is
COMPONENT icache
GENERIC
(
cache_size : natural := 2048; -- words
line_size : natural := 8 -- words
cache_size : natural; -- words
line_size : natural -- words
);
PORT
(
@@ -88,8 +93,8 @@ architecture behavior of bui is
COMPONENT dcache
GENERIC
(
cache_size : natural := 2048; -- words
line_size : natural := 8 -- words
cache_size : natural; -- words
line_size : natural -- words
);
PORT
(
@@ -103,8 +108,8 @@ architecture behavior of bui is
CYC_O : out STD_LOGIC;
en : in STD_LOGIC;
cpu_en : in STD_LOGIC;
cpu_r_wn : in STD_LOGIC;
cpu_we : in unsigned(3 downto 0);
cpu_we : in STD_LOGIC;
cpu_be : in unsigned(3 downto 0);
cpu_addr : in word_t;
cpu_din : in word_t;
cpu_dout : out word_t;
@@ -112,31 +117,36 @@ architecture behavior of bui is
);
END COMPONENT;
type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, uncached_bus_access);
type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish);
signal s, sn : bus_state_t;
signal dmem_we : unsigned(3 downto 0);
signal bus_idle : std_logic;
signal busy : std_logic;
signal dmem_be : unsigned(3 downto 0);
signal dcache_dout : word_t;
signal dcache_mem_gnt : std_logic;
signal icache_mem_gnt : std_logic;
signal dmem_mem_gnt : std_logic;
signal dcache_busy2 : std_logic;
signal dmem_mem_wr_gnt : std_logic;
signal dmem_mem_rd_gnt : std_logic;
signal dcache_busy : std_logic;
signal icache_busy : std_logic;
signal CYC_O_icache : std_logic;
signal CYC_O_dcache : std_logic;
signal CYC_O_dmem : std_logic;
signal CYC_O_dmem_rd : std_logic;
signal CYC_O_dmem_wr : std_logic;
signal SRDY_I_icache : std_logic;
signal SRDY_I_dcache : std_logic;
signal ADDR_O_icache : word_t;
signal ADDR_O_dcache : word_t;
signal ADDR_O_dmem : word_t;
signal ADDR_O_dmem_rd : word_t;
signal ADDR_O_dmem_wr : word_t;
signal STB_O_icache : std_logic;
signal STB_O_dcache : std_logic;
signal STB_O_dmem : std_logic;
signal DAT_I_dmem : word_t;
signal DAT_O_dmem : word_t;
signal SEL_O_dmem : unsigned(3 downto 0);
signal WE_O_dmem : std_logic;
signal STB_O_dmem_rd : std_logic;
signal STB_O_dmem_wr : std_logic;
signal DAT_I_dmem_rd : word_t;
signal DAT_O_dmem_wr : word_t;
signal SEL_O_dmem_wr : unsigned(3 downto 0);
signal dcached : std_logic;
signal dcache_en : std_logic;
signal uncached_access : std_logic;
@@ -145,80 +155,74 @@ architecture behavior of bui is
signal bus_timeout_cnt : timeout_cnt_t;
signal bus_timeout : std_logic;
signal bout_fifo_din : unsigned(68 downto 0);
signal bout_fifo_dout : unsigned(68 downto 0);
signal bout_fifo_re : std_logic;
signal bout_fifo_we : std_logic;
signal bout_fifo_full : std_logic;
signal bout_fifo_empty : std_logic;
signal bout_rdy : std_logic;
alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
alias bout_fifo_data_in is bout_fifo_din(63 downto 32);
alias bout_fifo_sel_in is bout_fifo_din(67 downto 64);
alias bout_fifo_we_in is bout_fifo_din(68);
alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0);
alias bout_fifo_data_out is bout_fifo_dout(63 downto 32);
alias bout_fifo_sel_out is bout_fifo_dout(67 downto 64);
alias bout_fifo_we_out is bout_fifo_dout(68);
signal write_fifo_din : unsigned(67 downto 0);
signal write_fifo_dout : unsigned(67 downto 0);
signal write_fifo_re : std_logic;
signal write_fifo_we : std_logic;
signal write_fifo_full : std_logic;
signal write_fifo_empty : std_logic;
signal write_busy : std_logic;
alias write_fifo_addr_in is write_fifo_din(31 downto 0);
alias write_fifo_data_in is write_fifo_din(63 downto 32);
alias write_fifo_sel_in is write_fifo_din(67 downto 64);
alias write_fifo_addr_out is write_fifo_dout(31 downto 0);
alias write_fifo_data_out is write_fifo_dout(63 downto 32);
alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
signal read_cycle : std_logic;
begin
bus_strobe:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
STB_O <= '0';
elsif dmem_mem_gnt = '1' then
STB_O <= STB_O_dmem;
elsif SRDY_I_dcache = '1' then
STB_O <= STB_O_dcache;
elsif SRDY_I_icache = '1' then
STB_O <= STB_O_icache;
elsif SRDY_I = '1' then
STB_O <= '0';
end if;
end if;
end process;
bus_cycle:
process(CLK_I)
begin
if rising_edge(CLK_I) then
CYC_O <= '0';
if dmem_mem_gnt = '1' then
CYC_O <= CYC_O_dmem;
elsif dcache_mem_gnt = '1' then
CYC_O <= CYC_O_dcache;
elsif icache_mem_gnt = '1' then
CYC_O <= CYC_O_icache;
end if;
end if;
end process;
bus_out:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ADDR_O <= (others => '0');
DAT_O <= (others => '0');
WE_O <= '0';
SEL_O <= (others => '0');
elsif dmem_mem_gnt = '1' then
ADDR_O <= ADDR_O_dmem;
DAT_O <= DAT_O_dmem;
WE_O <= WE_O_dmem;
SEL_O <= SEL_O_dmem;
elsif SRDY_I_dcache = '1' then
ADDR_O <= ADDR_O_dcache;
WE_O <= '0';
SEL_O <= (others => '0');
elsif SRDY_I_icache = '1' then
ADDR_O <= ADDR_O_icache;
WE_O <= '0';
SEL_O <= (others => '0');
end if;
end if;
end process;
MRDY_O <= '1';
SRDY_I_icache <= SRDY_I when icache_mem_gnt = '1' else '0';
SRDY_I_dcache <= SRDY_I when dcache_mem_gnt = '1' else '0';
-- SRDY_I_dmem <= SRDY_I when dmem_mem_gnt = '1' else '0';
read_cyc_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
read_cycle <= '0';
else
read_cycle <= (dmem_mem_rd_gnt and CYC_O_dmem_rd)
or (dcache_mem_gnt and CYC_O_dcache)
or (icache_mem_gnt and CYC_O_icache);
end if;
end if;
end process;
CYC_O <= not bout_fifo_empty or read_cycle;
STB_O <= not bout_fifo_empty;
ADDR_O <= bout_fifo_addr_out;
DAT_O <= bout_fifo_data_out;
SEL_O <= bout_fifo_sel_out;
WE_O <= bout_fifo_we_out;
cpu_imem_rdy <= not icache_busy after 4.5 ns;
cpu_dmem_rdy <= not (CYC_O_dmem or dcache_busy2) after 4.5 ns;
busy <= CYC_O_dmem_rd or dcache_busy or (write_busy);
cpu_dmem_rdy <= not busy after 4.5 ns;
inst_icache : icache
GENERIC MAP
(
cache_size => 2048, -- words
cache_size => icache_size, -- words
line_size => 8
)
PORT MAP
@@ -238,10 +242,12 @@ inst_icache : icache
cpu_busy => icache_busy
);
SRDY_I_icache <= bout_rdy and icache_mem_gnt;
inst_dcache : dcache
GENERIC MAP
(
cache_size => 2048, -- words
cache_size => dcache_size, -- words
line_size => 8
)
PORT MAP
@@ -256,64 +262,126 @@ inst_dcache : dcache
SRDY_I => SRDY_I_dcache,
en => dcached,
cpu_en => dcache_en,
cpu_r_wn => cpu_dmem_re,
cpu_we => cpu_dmem_we,
cpu_be => cpu_dmem_be,
cpu_addr => cpu_dmem_addr,
cpu_din => cpu_dmem_dout,
cpu_dout => dcache_dout,
cpu_busy => dcache_busy2
cpu_busy => dcache_busy
);
SRDY_I_dcache <= bout_rdy and dcache_mem_gnt;
dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0';
cpu_dmem_din <= dcache_dout when uncached_access = '0' else DAT_I_dmem;
dcache_en <= cpu_dmem_en and not CYC_O_dmem;
cpu_dmem_din <= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd;
dcache_en <= cpu_dmem_en and not busy;
dcache_flags:
-- Instantiate synchronous FIFO
inst_bout_fifo: entity work.fifo_sync_dist
GENERIC MAP
(
addr_width => 4,
data_width => 69
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => bout_fifo_we,
re => bout_fifo_re,
fifo_full => bout_fifo_full,
fifo_empty => bout_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => bout_fifo_din,
data_r => bout_fifo_dout
);
bout_rdy <= not bout_fifo_full;
bout_fifo_re <= not bout_fifo_empty and SRDY_I;
bout_fifo_we <= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
bout_fifo_data_in <= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
bout_fifo_addr_in <= ADDR_O_dmem_wr when dmem_mem_wr_gnt = '1' else
ADDR_O_dmem_rd when dmem_mem_rd_gnt = '1' else
ADDR_O_dcache when dcache_mem_gnt = '1' else
ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '0');
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
-- Instantiate synchronous FIFO
inst_write_fifo: entity work.fifo_sync_dist
GENERIC MAP
(
addr_width => 4,
data_width => 68
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => write_fifo_we,
re => write_fifo_re,
fifo_full => write_busy,
fifo_empty => write_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => write_fifo_din,
data_r => write_fifo_dout
);
CYC_O_dmem_wr <= not write_fifo_empty;
DAT_O_dmem_wr <= write_fifo_data_out;
ADDR_O_dmem_wr <= write_fifo_addr_out;
SEL_O_dmem_wr <= write_fifo_sel_out;
write_fifo_data_in <= cpu_dmem_dout;
write_fifo_addr_in <= cpu_dmem_addr;
write_fifo_sel_in <= cpu_dmem_be;
write_fifo_re <= STB_O_dmem_wr;
write_fifo_we <= cpu_dmem_en and not busy and cpu_dmem_we;
dmem_rd_flags:
process(CLK_I)
begin
if rising_edge(CLK_I) then
uncached_access <= '0';
if RST_I = '1' then
CYC_O_dmem <= '0';
CYC_O_dmem_rd <= '0';
else
if ACK_I = '1' and dmem_mem_gnt = '1' then
uncached_access <= not WE_O_dmem;
CYC_O_dmem <= '0';
if ACK_I = '1' and dmem_mem_rd_gnt = '1' then
uncached_access <= '1';
CYC_O_dmem_rd <= '0';
end if;
if cpu_dmem_en = '1' and CYC_O_dmem = '0' and dcache_busy2 = '0' then
CYC_O_dmem <= '1';
if dcached = '1' and cpu_dmem_re = '1' then
CYC_O_dmem <= '0';
if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then
if dcached = '0' then
CYC_O_dmem_rd <= '1';
end if;
end if;
end if;
end if;
end process;
dcache_data:
dmem_rd_data:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
DAT_I_dmem <= (others => '0');
elsif ACK_I = '1' and CYC_O_dmem = '1' then
DAT_I_dmem <= DAT_I;
DAT_I_dmem_rd <= (others => '0');
elsif ACK_I = '1' and CYC_O_dmem_rd = '1' then
DAT_I_dmem_rd <= DAT_I;
end if;
end if;
end process;
dcache_regs:
dmem_rd_regs:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
WE_O_dmem <= '0';
SEL_O_dmem <= (others => '0');
elsif cpu_dmem_en = '1' and CYC_O_dmem = '0' and dcache_busy2 = '0' then
DAT_O_dmem <= cpu_dmem_dout;
ADDR_O_dmem <= cpu_dmem_addr;
WE_O_dmem <= not cpu_dmem_re;
SEL_O_dmem <= cpu_dmem_we;
if cpu_dmem_en = '1' and busy = '0' then
ADDR_O_dmem_rd <= cpu_dmem_addr;
end if;
end if;
end process;
@@ -331,48 +399,60 @@ bus_state_next:
end process;
bus_state:
process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem, SRDY_I, ACK_I)
process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK_I)
begin
icache_mem_gnt <= '0';
dcache_mem_gnt <= '0';
dmem_mem_gnt <= '0';
STB_O_dmem <= '0';
dmem_mem_rd_gnt <= '0';
dmem_mem_wr_gnt <= '0';
STB_O_dmem_rd <= '0';
STB_O_dmem_wr <= '0';
bus_idle <= '0';
sn <= s;
case s is
when init =>
sn <= ready;
when ready =>
if CYC_O_dmem = '1' then
dmem_mem_gnt <= '1';
if SRDY_I = '1' then
STB_O_dmem <= '1';
sn <= uncached_bus_access;
end if;
bus_idle <= '1';
if CYC_O_dmem_wr = '1' then
sn <= write_bus;
elsif CYC_O_dmem_rd = '1' then
sn <= read_bus;
elsif CYC_O_icache = '1' then
sn <= i_cache_bus_access;
-- icache_mem_gnt <= '1';
sn <= icache_bus_access;
elsif CYC_O_dcache = '1' then
sn <= d_cache_bus_access;
-- dcache_mem_gnt <= '1';
sn <= dcache_bus_access;
end if;
when i_cache_bus_access =>
when icache_bus_access =>
icache_mem_gnt <= '1';
if CYC_O_icache = '0' then
sn <= ready;
-- icache_mem_gnt <= '0';
sn <= ready;
end if;
when d_cache_bus_access =>
when dcache_bus_access =>
dcache_mem_gnt <= '1';
if CYC_O_dcache = '0' then
sn <= ready;
-- dcache_mem_gnt <= '0';
sn <= ready;
end if;
when uncached_bus_access =>
dmem_mem_gnt <= '1';
when write_bus =>
dmem_mem_wr_gnt <= '1';
if CYC_O_dmem_wr = '1' then
if bout_rdy = '1' then
STB_O_dmem_wr <= '1';
end if;
else
sn <= ready;
end if;
when read_bus =>
dmem_mem_rd_gnt <= '1';
if bout_rdy = '1' then
STB_O_dmem_rd <= '1';
sn <= read_finish;
end if;
when read_finish =>
dmem_mem_rd_gnt <= '1';
if ACK_I = '1' then
sn <= ready;
-- dmem_mem_gnt <= '0';
sn <= ready;
end if;
when others =>
sn <= ready;
@@ -384,7 +464,7 @@ bus_timeout_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if (icache_mem_gnt or dcache_mem_gnt or dmem_mem_gnt) = '1' then
if bus_idle = '0' then
if bus_timeout_cnt /= 0 then
bus_timeout_cnt <= bus_timeout_cnt - 1;
else
@@ -406,11 +486,11 @@ bus_err:
cpu_dmem_err <= '0';
elsif bus_timeout = '1' then
cpu_imem_err <= icache_mem_gnt;
cpu_dmem_err <= dcache_mem_gnt or dmem_mem_gnt;
cpu_dmem_err <= dcache_mem_gnt or dmem_mem_wr_gnt or dmem_mem_rd_gnt;
end if;
end if;
end process;
-------------------------------------------------------------------
end behavior;
lib/CPUs/MIPS/src/core/mips_cop.vhd
+2 -2
View File
@@ -338,10 +338,10 @@ cop_register_read:
reg := test_reg;
when others =>
reg := X"DEADBEEF";
reg := (others => '-');
end case;
dout <= reg;
dout <= reg after 1 ns;
end if;
end process;
lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+6 -35
View File
@@ -43,8 +43,8 @@ entity pipeline is
dmem_err : in STD_LOGIC;
dmem_rdy : in STD_LOGIC;
dmem_en : out STD_LOGIC;
dmem_re : out STD_LOGIC;
dmem_we : out unsigned(3 downto 0);
dmem_we : out STD_LOGIC;
dmem_be : out unsigned(3 downto 0);
dmem_addr : out word_t;
dmem_din : in word_t;
dmem_dout : out word_t
@@ -615,7 +615,7 @@ proc_stage_DMEM_ADDR:
process(clk_1)
begin
if rising_edge(clk_1) then
if sdu.EX_stall = '0' then --and ID_stage.ctrl.dmem_en = '1' then
if sdu.EX_stall = '0' then
EX_stage.va <= vaddr;
if cop_stat.RE = '1' then
EX_stage.pa_off <= not vaddr(1 downto 0);
@@ -625,8 +625,8 @@ proc_stage_DMEM_ADDR:
end if;
end if;
end process;
dmem_we <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
dmem_re <= not EX_stage.ctrl.dmem_we;
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
dmem_we <= EX_stage.ctrl.dmem_we;
dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
dmem_addr <= EX_stage.va;
cop_din <= EX_stage.reg_b;
@@ -677,28 +677,7 @@ proc_stage_bcu_op:
end if;
end process;
alu_op1_mux:
process(EX_stage)
variable data : word_t;
begin
data := EX_stage.reg_a;
-- case EX_stage.ctrl.alu.op1_src is
--
-- when alu_src_reg =>
-- data := EX_stage.reg_a;
--
-- when alu_src_muldiv =>
-- data := mul_result;
--
-- when others => null;
--
-- end case;
EX_stage.alu_op1 <= data;
end process;
EX_stage.alu_op1 <= EX_stage.reg_a;
alu_op2_mux:
process(clk_1)
@@ -810,11 +789,6 @@ proc_stage_MEM_n:
MEM_stage.ctrl <= ctrl_lines_default;
MEM_stage.pa_off <= (others => '0');
MEM_stage.events_in <= events_clr;
-- MEM_stage.epc <= (others => '0');
-- MEM_stage.pcn <= (others => '0');
-- MEM_stage.va <= (others => '0');
-- MEM_stage.reg_wptr <= (others => '0');
-- MEM_stage.ex_result <= (others => '0');
elsif sdu.MEM_stall = '0' then
MEM_stage.events_in <= EX_stage.events;
MEM_stage.op <= EX_stage.op;
@@ -894,9 +868,6 @@ proc_stage_WB_p:
if rst = '1' then
WB_stage.op <= NOP;
WB_stage.wreg_we <= '0';
-- WB_stage.epc <= (others => '0');
-- WB_stage.reg_wptr <= (others => '0');
-- WB_stage.data <= (others => '0');
elsif sdu.WB_stall = '0' then
WB_stage.op <= MEM_stage.op;
WB_stage.wreg_we <= MEM_stage.wreg_we;
lib/CPUs/MIPS/src/core/mips_top.vhd
+20 -10
View File
@@ -66,8 +66,8 @@ architecture rtl of mips_top is
dmem_err : in STD_LOGIC;
dmem_rdy : in STD_LOGIC;
dmem_en : out STD_LOGIC;
dmem_re : out STD_LOGIC;
dmem_we : out unsigned(3 downto 0);
dmem_we : out STD_LOGIC;
dmem_be : out unsigned(3 downto 0);
dmem_addr : out word_t;
dmem_din : in word_t;
dmem_dout : out word_t
@@ -81,14 +81,19 @@ architecture rtl of mips_top is
signal dmem_err : std_logic;
signal dmem_rdy : std_logic;
signal dmem_en : std_logic;
signal dmem_re : std_logic;
signal dmem_we : std_logic;
signal dmem_addr : word_t;
signal dmem_dout : word_t;
signal dmem_din : word_t;
signal dmem_we : unsigned(3 downto 0);
signal dmem_be : unsigned(3 downto 0);
COMPONENT bui
COMPONENT biu
GENERIC
(
icache_size : natural;
dcache_size : natural
);
PORT
(
RST_I : in STD_LOGIC;
@@ -111,8 +116,8 @@ architecture rtl of mips_top is
cpu_dmem_err : out STD_LOGIC;
cpu_dmem_rdy : out STD_LOGIC;
cpu_dmem_en : in STD_LOGIC;
cpu_dmem_re : in STD_LOGIC;
cpu_dmem_we : in unsigned(3 downto 0);
cpu_dmem_we : in STD_LOGIC;
cpu_dmem_be : in unsigned(3 downto 0);
cpu_dmem_dout : in word_t;
cpu_dmem_din : out word_t;
cpu_dmem_addr : in word_t
@@ -140,14 +145,19 @@ inst_pipeline: pipeline
dmem_err => dmem_err,
dmem_rdy => dmem_rdy,
dmem_en => dmem_en,
dmem_re => dmem_re,
dmem_we => dmem_we,
dmem_be => dmem_be,
dmem_addr => dmem_addr,
dmem_din => dmem_din,
dmem_dout => dmem_dout
);
inst_bui: bui
inst_biu: biu
GENERIC MAP
(
icache_size => 4096, -- words
dcache_size => 4096 -- words
)
PORT MAP
(
RST_I => RST_I,
@@ -170,8 +180,8 @@ inst_bui: bui
cpu_dmem_err => dmem_err,
cpu_dmem_rdy => dmem_rdy,
cpu_dmem_en => dmem_en,
cpu_dmem_re => dmem_re,
cpu_dmem_we => dmem_we,
cpu_dmem_be => dmem_be,
cpu_dmem_addr => dmem_addr,
cpu_dmem_din => dmem_din,
cpu_dmem_dout => dmem_dout
lib/CPUs/MIPS/src/core/mips_types.vhd
+1 -1
View File
@@ -30,7 +30,7 @@ use IEEE.numeric_std.ALL;
package mips_types is
-- Revision of the CPU
constant REVISION : integer := 1;
constant REVISION : integer := 9;
constant WORD_WIDTH : integer := 32;
--Types
lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd
-2174
View File
File diff suppressed because it is too large Load Diff
lib/CPUs/MIPS/src/irom_hello.vhd
-320
View File
@@ -1,320 +0,0 @@
-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
clk : in STD_LOGIC;
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"3C1D7FFF", -- 00000000
X"0C100014", -- 00000004
X"37BDEFFC", -- 00000008
X"24080002", -- 0000000C
X"0107102A", -- 00000010
X"ACC40000", -- 00000014
X"1040000B", -- 00000018
X"ACC50004", -- 0000001C
X"24C60008", -- 00000020
X"24E8FFFE", -- 00000024
X"8CC2FFF8", -- 00000028
X"8CC3FFFC", -- 0000002C
X"2508FFFF", -- 00000030
X"00431021", -- 00000034
X"ACC20000", -- 00000038
X"1500FFFA", -- 0000003C
X"24C60004", -- 00000040
X"00E04021", -- 00000044
X"03E00008", -- 00000048
X"01001021", -- 0000004C
X"27BDFF78", -- 00000050
X"3C021003", -- 00000054
X"3C030001", -- 00000058
X"AFB60078", -- 0000005C
X"3456FFFC", -- 00000060
X"3C02AAAA", -- 00000064
X"AFB7007C", -- 00000068
X"AFB50074", -- 0000006C
X"AFB40070", -- 00000070
X"AFB20068", -- 00000074
X"AFB00060", -- 00000078
X"AFBF0080", -- 0000007C
X"AFB3006C", -- 00000080
X"AFB10064", -- 00000084
X"AEC00000", -- 00000088
X"3450AAAA", -- 0000008C
X"347786A0", -- 00000090
X"27B20010", -- 00000094
X"24150014", -- 00000098
X"3474869F", -- 0000009C
X"00009821", -- 000000A0
X"00002021", -- 000000A4
X"02401021", -- 000000A8
X"24060013", -- 000000AC
X"24C6FFFF", -- 000000B0
X"AC500000", -- 000000B4
X"04C1FFFD", -- 000000B8
X"24420004", -- 000000BC
X"02041026", -- 000000C0
X"24910001", -- 000000C4
X"24420001", -- 000000C8
X"02202821", -- 000000CC
X"27A60010", -- 000000D0
X"24070014", -- 000000D4
X"0C100003", -- 000000D8
X"00028040", -- 000000DC
X"24070002", -- 000000E0
X"26450008", -- 000000E4
X"0810003E", -- 000000E8
X"24060011", -- 000000EC
X"04C0000A", -- 000000F0
X"00000000", -- 000000F4
X"8CA20000", -- 000000F8
X"8CA3FFFC", -- 000000FC
X"8CA4FFF8", -- 00000100
X"00431023", -- 00000104
X"24C6FFFF", -- 00000108
X"1482FFF8", -- 0000010C
X"24A50004", -- 00000110
X"04C1FFF8", -- 00000114
X"24E70001", -- 00000118
X"10F5000C", -- 0000011C
X"00000000", -- 00000120
X"0291102A", -- 00000124
X"1040FFDF", -- 00000128
X"02202021", -- 0000012C
X"1677FFDB", -- 00000130
X"00009821", -- 00000134
X"8EC20000", -- 00000138
X"00000000", -- 0000013C
X"24420001", -- 00000140
X"AEC20000", -- 00000144
X"0810002A", -- 00000148
X"00002021", -- 0000014C
X"08100049", -- 00000150
X"26730001", -- 00000154
X"00000000", -- 00000158
X"00000000", -- 0000015C
X"00000000", -- 00000160
X"00000000", -- 00000164
X"00000000", -- 00000168
X"00000000", -- 0000016C
X"00000000", -- 00000170
X"00000000", -- 00000174
X"00000000", -- 00000178
X"00000000", -- 0000017C
X"00000000", -- 00000180
X"00000000", -- 00000184
X"00000000", -- 00000188
X"00000000", -- 0000018C
X"00000000", -- 00000190
X"00000000", -- 00000194
X"00000000", -- 00000198
X"00000000", -- 0000019C
X"00000000", -- 000001A0
X"00000000", -- 000001A4
X"00000000", -- 000001A8
X"00000000", -- 000001AC
X"00000000", -- 000001B0
X"00000000", -- 000001B4
X"00000000", -- 000001B8
X"00000000", -- 000001BC
X"00000000", -- 000001C0
X"00000000", -- 000001C4
X"00000000", -- 000001C8
X"00000000", -- 000001CC
X"00000000", -- 000001D0
X"00000000", -- 000001D4
X"00000000", -- 000001D8
X"00000000", -- 000001DC
X"00000000", -- 000001E0
X"00000000", -- 000001E4
X"00000000", -- 000001E8
X"00000000", -- 000001EC
X"00000000", -- 000001F0
X"00000000", -- 000001F4
X"00000000", -- 000001F8
X"00000000", -- 000001FC
X"00000000", -- 00000200
X"00000000", -- 00000204
X"00000000", -- 00000208
X"00000000", -- 0000020C
X"00000000", -- 00000210
X"00000000", -- 00000214
X"00000000", -- 00000218
X"00000000", -- 0000021C
X"00000000", -- 00000220
X"00000000", -- 00000224
X"00000000", -- 00000228
X"00000000", -- 0000022C
X"00000000", -- 00000230
X"00000000", -- 00000234
X"00000000", -- 00000238
X"00000000", -- 0000023C
X"00000000", -- 00000240
X"00000000", -- 00000244
X"00000000", -- 00000248
X"00000000", -- 0000024C
X"00000000", -- 00000250
X"00000000", -- 00000254
X"00000000", -- 00000258
X"00000000", -- 0000025C
X"00000000", -- 00000260
X"00000000", -- 00000264
X"00000000", -- 00000268
X"00000000", -- 0000026C
X"00000000", -- 00000270
X"00000000", -- 00000274
X"00000000", -- 00000278
X"00000000", -- 0000027C
X"00000000", -- 00000280
X"00000000", -- 00000284
X"00000000", -- 00000288
X"00000000", -- 0000028C
X"00000000", -- 00000290
X"00000000", -- 00000294
X"00000000", -- 00000298
X"00000000", -- 0000029C
X"00000000", -- 000002A0
X"00000000", -- 000002A4
X"00000000", -- 000002A8
X"00000000", -- 000002AC
X"00000000", -- 000002B0
X"00000000", -- 000002B4
X"00000000", -- 000002B8
X"00000000", -- 000002BC
X"00000000", -- 000002C0
X"00000000", -- 000002C4
X"00000000", -- 000002C8
X"00000000", -- 000002CC
X"00000000", -- 000002D0
X"00000000", -- 000002D4
X"00000000", -- 000002D8
X"00000000", -- 000002DC
X"00000000", -- 000002E0
X"00000000", -- 000002E4
X"00000000", -- 000002E8
X"00000000", -- 000002EC
X"00000000", -- 000002F0
X"00000000", -- 000002F4
X"00000000", -- 000002F8
X"00000000", -- 000002FC
X"00000000", -- 00000300
X"00000000", -- 00000304
X"00000000", -- 00000308
X"00000000", -- 0000030C
X"00000000", -- 00000310
X"00000000", -- 00000314
X"00000000", -- 00000318
X"00000000", -- 0000031C
X"00000000", -- 00000320
X"00000000", -- 00000324
X"00000000", -- 00000328
X"00000000", -- 0000032C
X"00000000", -- 00000330
X"00000000", -- 00000334
X"00000000", -- 00000338
X"00000000", -- 0000033C
X"00000000", -- 00000340
X"00000000", -- 00000344
X"00000000", -- 00000348
X"00000000", -- 0000034C
X"00000000", -- 00000350
X"00000000", -- 00000354
X"00000000", -- 00000358
X"00000000", -- 0000035C
X"00000000", -- 00000360
X"00000000", -- 00000364
X"00000000", -- 00000368
X"00000000", -- 0000036C
X"00000000", -- 00000370
X"00000000", -- 00000374
X"00000000", -- 00000378
X"00000000", -- 0000037C
X"00000000", -- 00000380
X"00000000", -- 00000384
X"00000000", -- 00000388
X"00000000", -- 0000038C
X"00000000", -- 00000390
X"00000000", -- 00000394
X"00000000", -- 00000398
X"00000000", -- 0000039C
X"00000000", -- 000003A0
X"00000000", -- 000003A4
X"00000000", -- 000003A8
X"00000000", -- 000003AC
X"00000000", -- 000003B0
X"00000000", -- 000003B4
X"00000000", -- 000003B8
X"00000000", -- 000003BC
X"00000000", -- 000003C0
X"00000000", -- 000003C4
X"00000000", -- 000003C8
X"00000000", -- 000003CC
X"00000000", -- 000003D0
X"00000000", -- 000003D4
X"00000000", -- 000003D8
X"00000000", -- 000003DC
X"00000000", -- 000003E0
X"00000000", -- 000003E4
X"00000000", -- 000003E8
X"00000000", -- 000003EC
X"00000000", -- 000003F0
X"00000000", -- 000003F4
X"00000000", -- 000003F8
X"00000000" -- 000003FC
);
begin
PROM_READ:
process(clk)
begin
if rising_edge(clk) then
dout <= word_array(to_integer(addr));
end if;
end process;
end itest;
lib/CPUs/MIPS/src/irom_test1.vhd
-121
View File
@@ -1,121 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"08100001", -- [0x00400000] j 0x00400004 [main]
X"3c011234", -- [0x00400004] lui $1, 4660
X"34215678", -- [0x00400008] ori $1, $1, 22136
X"3021f00f", -- [0x0040000c] andi $1, $1, -4081
X"2021affc", -- [0x00400010] addi $1, $1, -20484
X"2021ffff", -- [0x00400014] addi $1, $1, -1
X"1c20fffe", -- [0x00400018] bgtz $1 -8 [loop-0x00400018]
X"3c020000", -- [0x0040001c] lui $2, 0
X"34420001", -- [0x00400020] ori $2, $2, 1
X"3c010000", -- [0x00400024] lui $1, 0
X"34210004", -- [0x00400028] ori $1, $1, 4
X"00220822", -- [0x0040002c] sub $1, $1, $2
X"1c20fffe", -- [0x00400030] bgtz $1 -8 [loop2-0x00400030]
X"3c1f0040", -- [0x00400034] lui $31, 64
X"03e00008", -- [0x00400038] jr $31
X"00000000", -- [0x0040003c] nop
X"00000000", -- [0x00400040] nop
X"00000000", -- [0x00400044] nop
X"00000000", -- [0x00400048] nop
X"00000000", -- [0x0040004c] nop
X"00000000", -- [0x00400050] nop
X"00000000", -- [0x00400054] nop
X"00000000", -- [0x00400058] nop
X"00000000", -- [0x0040005c] nop
X"00000000", -- [0x00400060] nop
X"00000000", -- [0x00400064] nop
X"00000000", -- [0x00400068] nop
X"00000000", -- [0x0040006c] nop
X"00000000", -- [0x00400070] nop
X"00000000", -- [0x00400074] nop
X"00000000", -- [0x00400078] nop
X"00000000", -- [0x0040007c] nop
X"00000000", -- [0x00400080] nop
X"00000000", -- [0x00400084] nop
X"00000000", -- [0x00400088] nop
X"00000000", -- [0x0040008c] nop
X"00000000", -- [0x00400090] nop
X"00000000", -- [0x00400094] nop
X"00000000", -- [0x00400098] nop
X"00000000", -- [0x0040009c] nop
X"00000000", -- [0x004000a0] nop
X"00000000", -- [0x004000a4] nop
X"00000000", -- [0x004000a8] nop
X"00000000", -- [0x004000ac] nop
X"00000000", -- [0x004000b0] nop
X"00000000", -- [0x004000b4] nop
X"00000000", -- [0x004000b8] nop
X"00000000", -- [0x004000bc] nop
X"00000000", -- [0x004000c0] nop
X"00000000", -- [0x004000c4] nop
X"00000000", -- [0x004000c8] nop
X"00000000", -- [0x004000cc] nop
X"00000000", -- [0x004000d0] nop
X"00000000", -- [0x004000d4] nop
X"00000000", -- [0x004000d8] nop
X"00000000", -- [0x004000dc] nop
X"00000000", -- [0x004000e0] nop
X"00000000", -- [0x004000e4] nop
X"00000000", -- [0x004000e8] nop
X"00000000", -- [0x004000ec] nop
X"00000000", -- [0x004000f0] nop
X"00000000", -- [0x004000f4] nop
X"00000000", -- [0x004000f8] nop
X"00000000" -- [0x004000fc] nop
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test2.vhd
-73
View File
@@ -1,73 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"08100001", -- j 0x00400004 [main] ; 5: j main
X"3c011234", -- lui $1, 4660 ; 7: lui $1, 0x1234
X"34215678", -- ori $1, $1, 22136 ; 8: ori $1, $1, 0x5678
X"3c035555", -- lui $3, 21845 ; 9: lui $3, 0x5555
X"3463aaaa", -- ori $3, $3, -21846 ; 10: ori $3, $3, 0xAAAA
X"3c021000", -- lui $2, 4096 ; 11: lui $2, 0x1000
X"ac410000", -- sw $1, 0($2) ; 12: sw $1, 0($2)
X"ac430004", -- sw $3, 4($2) ; 13: sw $3, 4($2)
X"00000000", -- nop ; 14: sll $0, $0, 0
X"ac400000", -- sw $0, 0($2) ; 15: sw $0, 0($2)
X"ac400004", -- sw $0, 4($2) ; 16: sw $0, 4($2)
X"8c410000", -- lw $1, 0($2) ; 17: lw $1, 0($2)
X"8c430004", -- lw $3, 4($2) ; 18: lw $3, 4($2)
X"00000000", -- nop ; 19: sll $0, $0, 0
X"00000000", -- nop ; 20: sll $0, $0, 0
X"08100001" -- j 0x00400004 [main] ; 21: j main
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test3.vhd
-122
View File
@@ -1,122 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"08100001", -- [0x00400000] j 0x00400004 [main]
X"3c011234", -- [0x00400004] lui $1, 4660
X"34215a5a", -- [0x00400008] ori $1, $1, 23130
X"00010840", -- [0x0040000c] sll $1, $1, 1
X"00010900", -- [0x00400010] sll $1, $1, 4
X"00010880", -- [0x00400014] sll $1, $1, 2
X"00010840", -- [0x00400018] sll $1, $1, 1
X"00010a00", -- [0x0040001c] sll $1, $1, 8
X"00010882", -- [0x00400020] srl $1, $1, 2
X"00010942", -- [0x00400024] srl $1, $1, 5
X"00010842", -- [0x00400028] srl $1, $1, 1
X"00010a02", -- [0x0040002c] srl $1, $1, 8
X"3821ffff", -- [0x00400030] xori $1, $1, -1
X"3c1f0040", -- [0x00400034] lui $31, 64
X"03e00008", -- [0x00400038] jr $31
X"003f0826", -- [0x0040003c] xor $1, $1, $31
X"00000000", -- [0x00400040] nop
X"00000000", -- [0x00400044] nop
X"00000000", -- [0x00400048] nop
X"00000000", -- [0x0040004c] nop
X"00000000", -- [0x00400050] nop
X"00000000", -- [0x00400054] nop
X"00000000", -- [0x00400058] nop
X"00000000", -- [0x0040005c] nop
X"00000000", -- [0x00400060] nop
X"00000000", -- [0x00400064] nop
X"00000000", -- [0x00400068] nop
X"00000000", -- [0x0040006c] nop
X"00000000", -- [0x00400070] nop
X"00000000", -- [0x00400074] nop
X"00000000", -- [0x00400078] nop
X"00000000", -- [0x0040007c] nop
X"00000000", -- [0x00400080] nop
X"00000000", -- [0x00400084] nop
X"00000000", -- [0x00400088] nop
X"00000000", -- [0x0040008c] nop
X"00000000", -- [0x00400090] nop
X"00000000", -- [0x00400094] nop
X"00000000", -- [0x00400098] nop
X"00000000", -- [0x0040009c] nop
X"00000000", -- [0x004000a0] nop
X"00000000", -- [0x004000a4] nop
X"00000000", -- [0x004000a8] nop
X"00000000", -- [0x004000ac] nop
X"00000000", -- [0x004000b0] nop
X"00000000", -- [0x004000b4] nop
X"00000000", -- [0x004000b8]
X"00000000", -- [0x004000bc]
X"00000000", -- [0x004000c0]
X"00000000", -- [0x004000c4]
X"00000000", -- [0x004000c8]
X"00000000", -- [0x004000cc]
X"00000000", -- [0x004000d0]
X"00000000", -- [0x004000d4]
X"00000000", -- [0x004000d8]
X"00000000", -- [0x004000dc]
X"00000000", -- [0x004000e0]
X"00000000", -- [0x004000e4]
X"00000000", -- [0x004000e8]
X"00000000", -- [0x004000ec]
X"00000000", -- [0x004000f0]
X"00000000", -- [0x004000f4]
X"00000000", -- [0x004000f8]
X"00000000" -- [0x004000fc]
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test4.vhd
-122
View File
@@ -1,122 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main
X"00000000", -- [0x00400004] nop ; 7: sll $0, $0, 0
X"3c011000", -- [0x00400008] lui $1, 4096 ; 8: lui $1, 0x1000
X"20220000", -- [0x0040000c] addi $2, $1, 0 ; 9: addi $2, $1, 0
X"3c071234", -- [0x00400010] lui $7, 4660 ; 10: lui $7, 0x1234
X"3c050001", -- [0x00400014] lui $5, 1 ; 11: lui $5, 0x0001
X"ac270000", -- [0x00400018] sw $7, 0($1) ; 12: sw $7, 0($1)
X"8c430000", -- [0x0040001c] lw $3, 0($2) ; 13: lw $3, 0($2)
X"00654020", -- [0x00400020] add $8, $3, $5 ; 14: add $8, $3, $5
X"00654820", -- [0x00400024] add $9, $3, $5 ; 15: add $9, $3, $5
X"00655020", -- [0x00400028] add $10, $3, $5 ; 16: add $10, $3, $5
X"00655820", -- [0x0040002c] add $11, $3, $5 ; 17: add $11, $3, $5
X"00000000", -- [0x00400030] nop ; 18: sll $0, $0, 0
X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0
X"08100001", -- [0x00400038] j 0x00400004 [main] ; 20: j main
X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0
X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test5.vhd
-122
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@@ -1,122 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"08100001", -- [0x00400000] j 0x00400004 [main]
X"3c018000", -- [0x00400004] lui $1, -32768
X"3c020000", -- [0x00400008] lui $2, 0
X"3c030000", -- [0x0040000c] lui $3, 0
X"34420001", -- [0x00400010] ori $2, $2, 1
X"34630003", -- [0x00400014] ori $3, $3, 3
X"00010842", -- [0x00400018] srl $1, $1, 1
X"00010840", -- [0x0040001c] sll $1, $1, 1
X"00010843", -- [0x00400020] sra $1, $1, 1
X"000108c3", -- [0x00400024] sra $1, $1, 3
X"00612004", -- [0x00400028] sllv $4, $1, $3
X"00412807", -- [0x0040002c] srav $5, $1, $2
X"00613007", -- [0x00400030] srav $6, $1, $3
X"3c1f0040", -- [0x00400034] lui $31, 64
X"03e00008", -- [0x00400038] jr $31
X"00000000", -- [0x0040003c] nop
X"00000000", -- [0x00400040] nop
X"00000000", -- [0x00400044] nop
X"00000000", -- [0x00400048] nop
X"00000000", -- [0x0040004c] nop
X"00000000", -- [0x00400050] nop
X"00000000", -- [0x00400054] nop
X"00000000", -- [0x00400058] nop
X"00000000", -- [0x0040005c] nop
X"00000000", -- [0x00400060] nop
X"00000000", -- [0x00400064] nop
X"00000000", -- [0x00400068] nop
X"00000000", -- [0x0040006c] nop
X"00000000", -- [0x00400070] nop
X"00000000", -- [0x00400074] nop
X"00000000", -- [0x00400078] nop
X"00000000", -- [0x0040007c] nop
X"00000000", -- [0x00400080] nop
X"00000000", -- [0x00400084] nop
X"00000000", -- [0x00400088] nop
X"00000000", -- [0x0040008c] nop
X"00000000", -- [0x00400090] nop
X"00000000", -- [0x00400094] nop
X"00000000", -- [0x00400098] nop
X"00000000", -- [0x0040009c] nop
X"00000000", -- [0x004000a0] nop
X"00000000", -- [0x004000a4] nop
X"00000000", -- [0x004000a8] nop
X"00000000", -- [0x004000ac] nop
X"00000000", -- [0x004000b0] nop
X"00000000", -- [0x004000b4] nop
X"00000000", -- [0x004000b8] nop
X"00000000", -- [0x004000bc] nop
X"00000000", -- [0x004000c0] nop
X"00000000", -- [0x004000c4] nop
X"00000000", -- [0x004000c8] nop
X"00000000", -- [0x004000cc] nop
X"00000000", -- [0x004000d0] nop
X"00000000", -- [0x004000d4] nop
X"00000000", -- [0x004000d8] nop
X"00000000", -- [0x004000dc] nop
X"00000000", -- [0x004000e0] nop
X"00000000", -- [0x004000e4] nop
X"00000000", -- [0x004000e8] nop
X"00000000", -- [0x004000ec] nop
X"00000000", -- [0x004000f0] nop
X"00000000", -- [0x004000f4] nop
X"00000000", -- [0x004000f8] nop
X"00000000" -- [0x004000fc] nop
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test6.vhd
-121
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@@ -1,121 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main
X"3c080000", -- [0x00400004] lui $8, 0 ; 7: lui $8, 0
X"00000000", -- [0x00400008] nop ; 8: sll $0, $0, 0
X"0c100009", -- [0x0040000c] jal 0x00400024 [subr1] ; 9: jal subr1
X"3c010040", -- [0x00400010] lui $1, 64 [subr2] ; 10: la $2, subr2
X"34220030", -- [0x00400014] ori $2, $1, 48 [subr2]
X"00407809", -- [0x00400018] jalr $15, $2 ; 11: jalr $15, $2
X"00000000", -- [0x0040001c] nop ; 12: sll $0, $0, 0
X"08100002", -- [0x00400020] j 0x00400008 [loop] ; 13: j loop
X"21080001", -- [0x00400024] addi $8, $8, 1 ; 15: addi $8, 1
X"00000000", -- [0x00400028] nop ; 16: sll $0, $0, 0
X"03e00008", -- [0x0040002c] jr $31 ; 17: jr $31
X"21080010", -- [0x00400030] addi $8, $8, 16 ; 18: addi $8, 16
X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0
X"01e00008", -- [0x00400038] jr $15 ; 20: jr $15
X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0
X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0
X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test_addsub.vhd
-121
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@@ -1,121 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"3c011234", -- [0x00400000] lui $1, 4660
X"34225678", -- [0x00400004] ori $2, $1, 22136
X"3c012345", -- [0x00400008] lui $1, 9029
X"34236789", -- [0x0040000c] ori $3, $1, 26505
X"3c018765", -- [0x00400010] lui $1, -30875
X"34244321", -- [0x00400014] ori $4, $1, 17185
X"3c019876", -- [0x00400018] lui $1, -26506
X"34255432", -- [0x0040001c] ori $5, $1, 21554
X"00000000", -- [0x00400020] nop
X"00427823", -- [0x00400024] subu $15, $2, $2
X"00437823", -- [0x00400028] subu $15, $2, $3
X"00447823", -- [0x0040002c] subu $15, $2, $4
X"00457823", -- [0x00400030] subu $15, $2, $5
X"00627823", -- [0x00400034] subu $15, $3, $2
X"00637823", -- [0x00400038] subu $15, $3, $3
X"00647823", -- [0x0040003c] subu $15, $3, $4
X"00657823", -- [0x00400040] subu $15, $3, $5
X"00827823", -- [0x00400044] subu $15, $4, $2
X"00837823", -- [0x00400048] subu $15, $4, $3
X"00847823", -- [0x0040004c] subu $15, $4, $4
X"00857823", -- [0x00400050] subu $15, $4, $5
X"00a27823", -- [0x00400054] subu $15, $5, $2
X"00a37823", -- [0x00400058] subu $15, $5, $3
X"00a47823", -- [0x0040005c] subu $15, $5, $4
X"00a57823", -- [0x00400060] subu $15, $5, $5
X"00000000", -- [0x00400064] nop
X"00427822", -- [0x00400068] sub $15, $2, $2
X"00437822", -- [0x0040006c] sub $15, $2, $3
X"00447822", -- [0x00400070] sub $15, $2, $4
X"00457822", -- [0x00400074] sub $15, $2, $5
X"00627822", -- [0x00400078] sub $15, $3, $2
X"00637822", -- [0x0040007c] sub $15, $3, $3
X"00647822", -- [0x00400080] sub $15, $3, $4
X"00657822", -- [0x00400084] sub $15, $3, $5
X"00827822", -- [0x00400088] sub $15, $4, $2
X"00837822", -- [0x0040008c] sub $15, $4, $3
X"00847822", -- [0x00400090] sub $15, $4, $4
X"00857822", -- [0x00400094] sub $15, $4, $5
X"00a27822", -- [0x00400098] sub $15, $5, $2
X"00a37822", -- [0x0040009c] sub $15, $5, $3
X"00a47822", -- [0x004000a0] sub $15, $5, $4
X"00a57822", -- [0x004000a4] sub $15, $5, $5
X"00000000", -- [0x004000a8] nop
X"08104000", -- [0x004000ac] j 0x00410000 [main]
X"00000000", -- [0x004000b0] nop
X"00000000", -- [0x004000b4]
X"00000000", -- [0x004000b8]
X"00000000", -- [0x004000bc]
X"00000000", -- [0x004000c0]
X"00000000", -- [0x004000c4]
X"00000000", -- [0x004000c8]
X"00000000", -- [0x004000cc]
X"00000000", -- [0x004000d0]
X"00000000", -- [0x004000d4]
X"00000000", -- [0x004000d8]
X"00000000", -- [0x004000dc]
X"00000000", -- [0x004000e0]
X"00000000", -- [0x004000e4]
X"00000000", -- [0x004000e8]
X"00000000", -- [0x004000ec]
X"00000000", -- [0x004000f0]
X"00000000", -- [0x004000f4]
X"00000000", -- [0x004000f8]
X"00000000" -- [0x004000fc]
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test_slt.vhd
-121
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@@ -1,121 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"3c011234", -- [0x00400000] lui $1, 4660
X"34225678", -- [0x00400004] ori $2, $1, 22136
X"3c012345", -- [0x00400008] lui $1, 9029
X"34236789", -- [0x0040000c] ori $3, $1, 26505
X"3c018765", -- [0x00400010] lui $1, -30875
X"34244321", -- [0x00400014] ori $4, $1, 17185
X"3c019876", -- [0x00400018] lui $1, -26506
X"34255432", -- [0x0040001c] ori $5, $1, 21554
X"3c081000", -- [0x00400020] lui $8, 4096
X"00000000", -- [0x00400024] nop
X"0042782b", -- [0x00400028] sltu $15, $2, $2
X"0043782b", -- [0x0040002c] sltu $15, $2, $3
X"0044782b", -- [0x00400030] sltu $15, $2, $4
X"0045782b", -- [0x00400034] sltu $15, $2, $5
X"0062782b", -- [0x00400038] sltu $15, $3, $2
X"0063782b", -- [0x0040003c] sltu $15, $3, $3
X"0064782b", -- [0x00400040] sltu $15, $3, $4
X"0065782b", -- [0x00400044] sltu $15, $3, $5
X"0082782b", -- [0x00400048] sltu $15, $4, $2
X"0083782b", -- [0x0040004c] sltu $15, $4, $3
X"0084782b", -- [0x00400050] sltu $15, $4, $4
X"0085782b", -- [0x00400054] sltu $15, $4, $5
X"00a2782b", -- [0x00400058] sltu $15, $5, $2
X"00a3782b", -- [0x0040005c] sltu $15, $5, $3
X"00a4782b", -- [0x00400060] sltu $15, $5, $4
X"00a5782b", -- [0x00400064] sltu $15, $5, $5
X"00000000", -- [0x00400068] nop
X"0042782a", -- [0x0040006c] slt $15, $2, $2
X"0043782a", -- [0x00400070] slt $15, $2, $3
X"0044782a", -- [0x00400074] slt $15, $2, $4
X"0045782a", -- [0x00400078] slt $15, $2, $5
X"0062782a", -- [0x0040007c] slt $15, $3, $2
X"0063782a", -- [0x00400080] slt $15, $3, $3
X"0064782a", -- [0x00400084] slt $15, $3, $4
X"0065782a", -- [0x00400088] slt $15, $3, $5
X"0082782a", -- [0x0040008c] slt $15, $4, $2
X"0083782a", -- [0x00400090] slt $15, $4, $3
X"0084782a", -- [0x00400094] slt $15, $4, $4
X"0085782a", -- [0x00400098] slt $15, $4, $5
X"00a2782a", -- [0x0040009c] slt $15, $5, $2
X"00a3782a", -- [0x004000a0] slt $15, $5, $3
X"00a4782a", -- [0x004000a4] slt $15, $5, $4
X"00a5782a", -- [0x004000a8] slt $15, $5, $5
X"00000000", -- [0x004000ac] nop
X"08104000", -- [0x004000b0] j 0x00410000 [main]
X"00000000", -- [0x004000b4] nop
X"00000000", -- [0x004000b8]
X"00000000", -- [0x004000bc]
X"00000000", -- [0x004000c0]
X"00000000", -- [0x004000c4]
X"00000000", -- [0x004000c8]
X"00000000", -- [0x004000cc]
X"00000000", -- [0x004000d0]
X"00000000", -- [0x004000d4]
X"00000000", -- [0x004000d8]
X"00000000", -- [0x004000dc]
X"00000000", -- [0x004000e0]
X"00000000", -- [0x004000e4]
X"00000000", -- [0x004000e8]
X"00000000", -- [0x004000ec]
X"00000000", -- [0x004000f0]
X"00000000", -- [0x004000f4]
X"00000000", -- [0x004000f8]
X"00000000" -- [0x004000fc]
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test_slti.vhd
-121
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@@ -1,121 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"3c011234", -- [0x00400000] lui $1, 4660
X"34225678", -- [0x00400004] ori $2, $1, 22136
X"3c012345", -- [0x00400008] lui $1, 9029
X"34236789", -- [0x0040000c] ori $3, $1, 26505
X"3c018765", -- [0x00400010] lui $1, -30875
X"34244321", -- [0x00400014] ori $4, $1, 17185
X"3c019876", -- [0x00400018] lui $1, -26506
X"34255432", -- [0x0040001c] ori $5, $1, 21554
X"3c081000", -- [0x00400020] lui $8, 4096
X"00000000", -- [0x00400024] nop
X"2c4f1234", -- [0x00400028] sltiu $15, $2, 4660
X"2c4f2345", -- [0x0040002c] sltiu $15, $2, 9029
X"2c4fedcc", -- [0x00400030] sltiu $15, $2, -4660
X"2c4fdcbb", -- [0x00400034] sltiu $15, $2, -9029
X"2c6f1234", -- [0x00400038] sltiu $15, $3, 4660
X"2c6f2345", -- [0x0040003c] sltiu $15, $3, 9029
X"2c6fedcc", -- [0x00400040] sltiu $15, $3, -4660
X"2c6fdcbb", -- [0x00400044] sltiu $15, $3, -9029
X"2c8f1234", -- [0x00400048] sltiu $15, $4, 4660
X"2c8f2345", -- [0x0040004c] sltiu $15, $4, 9029
X"2c8fedcc", -- [0x00400050] sltiu $15, $4, -4660
X"2c8fdcbb", -- [0x00400054] sltiu $15, $4, -9029
X"2caf1234", -- [0x00400058] sltiu $15, $5, 4660
X"2caf2345", -- [0x0040005c] sltiu $15, $5, 9029
X"2cafedcc", -- [0x00400060] sltiu $15, $5, -4660
X"2cafdcbb", -- [0x00400064] sltiu $15, $5, -9029
X"00000000", -- [0x00400068] nop
X"284f1234", -- [0x0040006c] slti $15, $2, 4660
X"284f2345", -- [0x00400070] slti $15, $2, 9029
X"284fedcc", -- [0x00400074] slti $15, $2, -4660
X"284fdcbb", -- [0x00400078] slti $15, $2, -9029
X"286f1234", -- [0x0040007c] slti $15, $3, 4660
X"286f2345", -- [0x00400080] slti $15, $3, 9029
X"286fedcc", -- [0x00400084] slti $15, $3, -4660
X"286fdcbb", -- [0x00400088] slti $15, $3, -9029
X"288f1234", -- [0x0040008c] slti $15, $4, 4660
X"288f2345", -- [0x00400090] slti $15, $4, 9029
X"288fedcc", -- [0x00400094] slti $15, $4, -4660
X"288fdcbb", -- [0x00400098] slti $15, $4, -9029
X"28af1234", -- [0x0040009c] slti $15, $5, 4660
X"28af2345", -- [0x004000a0] slti $15, $5, 9029
X"28afedcc", -- [0x004000a4] slti $15, $5, -4660
X"28afdcbb", -- [0x004000a8] slti $15, $5, -9029
X"00000000", -- [0x004000ac] nop
X"08104000", -- [0x004000b0] j 0x00410000 [main]
X"00000000", -- [0x004000b4] nop
X"00000000", -- [0x004000b8]
X"00000000", -- [0x004000bc]
X"00000000", -- [0x004000c0]
X"00000000", -- [0x004000c4]
X"00000000", -- [0x004000c8]
X"00000000", -- [0x004000cc]
X"00000000", -- [0x004000d0]
X"00000000", -- [0x004000d4]
X"00000000", -- [0x004000d8]
X"00000000", -- [0x004000dc]
X"00000000", -- [0x004000e0]
X"00000000", -- [0x004000e4]
X"00000000", -- [0x004000e8]
X"00000000", -- [0x004000ec]
X"00000000", -- [0x004000f0]
X"00000000", -- [0x004000f4]
X"00000000", -- [0x004000f8]
X"00000000" -- [0x004000fc]
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/irom_test_sub.vhd
-121
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@@ -1,121 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY rom IS
Generic
(
addr_width : integer := 2;
data_width : integer := 32
);
Port
(
addr : in unsigned(addr_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
END rom;
ARCHITECTURE itest OF rom IS
subtype word_t is unsigned(data_width-1 downto 0);
type word_array_t is array (0 to 2**addr_width-1) of word_t;
-- Assembled from itest.jsm
constant word_array : word_array_t :=
(
X"3c011234", -- [0x00400000] lui $1, 4660
X"34225678", -- [0x00400004] ori $2, $1, 22136
X"3c012345", -- [0x00400008] lui $1, 9029
X"34236789", -- [0x0040000c] ori $3, $1, 26505
X"3c018765", -- [0x00400010] lui $1, -30875
X"34244321", -- [0x00400014] ori $4, $1, 17185
X"3c019876", -- [0x00400018] lui $1, -26506
X"34255432", -- [0x0040001c] ori $5, $1, 21554
X"00000000", -- [0x00400020] nop
X"00427823", -- [0x00400024] subu $15, $2, $2
X"00437823", -- [0x00400028] subu $15, $2, $3
X"00447823", -- [0x0040002c] subu $15, $2, $4
X"00457823", -- [0x00400030] subu $15, $2, $5
X"00627823", -- [0x00400034] subu $15, $3, $2
X"00637823", -- [0x00400038] subu $15, $3, $3
X"00647823", -- [0x0040003c] subu $15, $3, $4
X"00657823", -- [0x00400040] subu $15, $3, $5
X"00827823", -- [0x00400044] subu $15, $4, $2
X"00837823", -- [0x00400048] subu $15, $4, $3
X"00847823", -- [0x0040004c] subu $15, $4, $4
X"00857823", -- [0x00400050] subu $15, $4, $5
X"00a27823", -- [0x00400054] subu $15, $5, $2
X"00a37823", -- [0x00400058] subu $15, $5, $3
X"00a47823", -- [0x0040005c] subu $15, $5, $4
X"00a57823", -- [0x00400060] subu $15, $5, $5
X"00000000", -- [0x00400064] nop
X"00427822", -- [0x00400068] sub $15, $2, $2
X"00437822", -- [0x0040006c] sub $15, $2, $3
X"00447822", -- [0x00400070] sub $15, $2, $4
X"00457822", -- [0x00400074] sub $15, $2, $5
X"00627822", -- [0x00400078] sub $15, $3, $2
X"00637822", -- [0x0040007c] sub $15, $3, $3
X"00647822", -- [0x00400080] sub $15, $3, $4
X"00657822", -- [0x00400084] sub $15, $3, $5
X"00827822", -- [0x00400088] sub $15, $4, $2
X"00837822", -- [0x0040008c] sub $15, $4, $3
X"00847822", -- [0x00400090] sub $15, $4, $4
X"00857822", -- [0x00400094] sub $15, $4, $5
X"00a27822", -- [0x00400098] sub $15, $5, $2
X"00a37822", -- [0x0040009c] sub $15, $5, $3
X"00a47822", -- [0x004000a0] sub $15, $5, $4
X"00a57822", -- [0x004000a4] sub $15, $5, $5
X"00000000", -- [0x004000a8] nop
X"08104000", -- [0x004000ac] j 0x00410000 [main]
X"00000000", -- [0x004000b0] nop
X"00000000", -- [0x004000b4]
X"00000000", -- [0x004000b8]
X"00000000", -- [0x004000bc]
X"00000000", -- [0x004000c0]
X"00000000", -- [0x004000c4]
X"00000000", -- [0x004000c8]
X"00000000", -- [0x004000cc]
X"00000000", -- [0x004000d0]
X"00000000", -- [0x004000d4]
X"00000000", -- [0x004000d8]
X"00000000", -- [0x004000dc]
X"00000000", -- [0x004000e0]
X"00000000", -- [0x004000e4]
X"00000000", -- [0x004000e8]
X"00000000", -- [0x004000ec]
X"00000000", -- [0x004000f0]
X"00000000", -- [0x004000f4]
X"00000000", -- [0x004000f8]
X"00000000" -- [0x004000fc]
);
begin
PROM_READ:
dout <= word_array(to_integer(addr));
end itest;
lib/CPUs/MIPS/src/mips_embedded.vhd
-332
View File
@@ -1,332 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
library work;
use work.mips_types.all;
entity mips_embedded is
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
halt : in STD_LOGIC;
int : in unsigned(5 downto 0);
rxd : in STD_LOGIC;
txd : out STD_LOGIC;
dout : out word_t
);
end mips_embedded;
architecture rtl of mips_embedded is
COMPONENT mips_top
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
int : in unsigned(5 downto 0);
mem_rdy : in STD_LOGIC;
mem_re : out STD_LOGIC;
mem_en : out STD_LOGIC;
mem_we : out unsigned(3 downto 0);
mem_din : in word_t;
mem_dout : out word_t;
mem_addr : out word_t
);
END COMPONENT;
signal mem_din : word_t;
signal mem_dout : word_t;
signal mem_addr : word_t;
signal mem_re : std_logic;
signal mem_en : std_logic;
signal mem_we : unsigned(3 downto 0);
signal mem_rdy : std_logic;
subtype tick_usec_t is natural range 0 to 99;
signal tick_usec : tick_usec_t;
signal cnt_usec : word_t;
signal cnt_sec : word_t;
signal cnt_usec_preset : word_t;
signal cnt_sec_preset : word_t;
signal cnt_usec_en : std_logic;
signal cnt_usec_we : std_logic;
signal cnt_sec_en : std_logic;
signal cnt_sec_we : std_logic;
COMPONENT uart_tx
Port
(
data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic
);
END COMPONENT;
COMPONENT uart_rx
Port
(
serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic
);
END COMPONENT;
signal baud_count : unsigned(7 downto 0);
signal en_16_x_baud : std_logic;
signal reg_we_uart_tx : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
signal reg_uart_tx : unsigned(7 downto 0);
signal reg_re_uart_rx : std_logic;
signal reg_uart_rx : std_logic_vector(7 downto 0);
signal rx_data_present : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
signal uart_status_port : unsigned(7 downto 0);
signal reg_uart_ctrl : unsigned(7 downto 0);
signal reg_uart_baud : unsigned(7 downto 0);
begin
registers_write:
process(clk)
begin
if rising_edge(clk) then
reg_we_uart_tx <= '0';
cnt_usec_we <= '0';
cnt_sec_we <= '0';
if rst = '1' then
dout <= (others => '0');
reg_uart_baud <= to_unsigned(53, 8);
reg_uart_ctrl <= to_unsigned(0, 8);
elsif mem_en = '1' then
case mem_addr(5 downto 2) is
when "0000" =>
if mem_we(0) = '1' then
dout(7 downto 0) <= mem_dout(7 downto 0);
end if;
if mem_we(1) = '1' then
dout(15 downto 8) <= mem_dout(15 downto 8);
end if;
if mem_we(2) = '1' then
dout(23 downto 16) <= mem_dout(23 downto 16);
end if;
if mem_we(3) = '1' then
dout(31 downto 24) <= mem_dout(31 downto 24);
end if;
when "0001" =>
if mem_we(0) = '1' then
reg_we_uart_tx <= '1';
reg_uart_tx <= mem_dout(7 downto 0);
end if;
when "0010" =>
if mem_we(0) = '1' then
reg_uart_ctrl <= mem_dout(7 downto 0);
end if;
if mem_we(1) = '1' then
reg_uart_baud <= mem_dout(15 downto 8);
end if;
when "0100" =>
if mem_we(3) = '1' then
cnt_usec_we <= '1';
cnt_usec_preset <= mem_dout;
end if;
when "0101" =>
if mem_we(3) = '1' then
cnt_sec_we <= '1';
cnt_sec_preset <= mem_dout;
end if;
when others => null;
end case;
end if;
end if;
end process;
registers_read:
process(clk)
begin
if rising_edge(clk) then
reg_re_uart_rx <= '0';
if mem_en = '1' then
mem_din <= (others => '0');
case mem_addr(5 downto 2) is
when "0000" => null;
when "0001" =>
reg_re_uart_rx <= '1';
mem_din(7 downto 0) <= unsigned(reg_uart_rx);
when "0010" =>
mem_din(7 downto 0) <= uart_status_port;
mem_din(15 downto 8) <= reg_uart_baud;
when "0100" =>
mem_din <= cnt_usec;
when "0101" =>
mem_din <= cnt_sec;
when others => null;
end case;
end if;
end if;
end process;
mem_rdy <= not halt;
inst_mips_top: mips_top
PORT MAP
(
rst => rst,
clk => clk,
int => int,
mem_rdy => mem_rdy,
mem_en => mem_en,
mem_we => mem_we,
mem_din => mem_din,
mem_dout => mem_dout,
mem_addr => mem_addr
);
inst_uart_tx: uart_tx
port map
(
data_in => std_logic_vector(reg_uart_tx),
write_buffer => reg_we_uart_tx,
reset_buffer => rst,
en_16_x_baud => en_16_x_baud,
serial_out => txd,
buffer_full => tx_full,
buffer_half_full => tx_half_full,
clk => clk
);
inst_uart_rx: uart_rx
port map
(
serial_in => rxd,
data_out => reg_uart_rx,
read_buffer => reg_re_uart_rx,
reset_buffer => rst,
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,
buffer_full => rx_full,
buffer_half_full => rx_half_full,
clk => clk
);
uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
tick_usec_timer:
process(clk)
begin
if clk'event and clk='1' then
cnt_usec_en <= '0';
if rst = '1' then
tick_usec <= 0;
cnt_usec_en <= '0';
elsif tick_usec = tick_usec_t'high then
tick_usec <= 0;
cnt_usec_en <= '1';
else
tick_usec <= tick_usec + 1;
end if;
end if;
end process;
cnt_usec_timer:
process(clk)
begin
if clk'event and clk='1' then
cnt_sec_en <= '0';
if rst = '1' then
cnt_usec <= (others => '0');
cnt_sec_en <= '0';
elsif cnt_usec_we = '1' then
cnt_usec <= cnt_usec_preset;
elsif cnt_usec_en = '1' then
if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then
cnt_usec <= (others => '0');
cnt_sec_en <= '1';
else
cnt_usec <= cnt_usec + 1;
end if;
end if;
end if;
end process;
cnt_sec_timer:
process(clk)
begin
if clk'event and clk='1' then
if rst = '1' then
cnt_sec <= (others => '0');
elsif cnt_sec_we = '1' then
cnt_sec <= cnt_sec_preset;
elsif cnt_sec_en = '1' then
cnt_sec <= cnt_sec + 1;
end if;
end if;
end process;
baud_timer:
process(clk)
begin
if clk'event and clk='1' then
if rst = '1' then
baud_count <= (others => '0');
elsif baud_count = reg_uart_baud then
baud_count <= (others => '0');
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process;
end rtl;
lib/CPUs/MIPS/src/mips_embedded_syn.vhd
-137
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@@ -1,137 +0,0 @@
--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: JIPS top file
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
library work;
use work.mips_types.all;
entity mips_embedded_syn is
Port
(
sys_rst_n_in : in STD_LOGIC;
sys_clk_in : in STD_LOGIC;
sys_dip : in STD_LOGIC_VECTOR (7 downto 0);
sys_btn : in STD_LOGIC_VECTOR (8 downto 0);
sys_led : out STD_LOGIC_VECTOR (7 downto 0);
sys_rx : in STD_LOGIC;
sys_tx : out STD_LOGIC;
sys_error : out STD_LOGIC_VECTOR (1 downto 0)
);
end mips_embedded_syn;
architecture struct of mips_embedded_syn is
COMPONENT mips_embedded
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
halt : in STD_LOGIC;
int : in unsigned(5 downto 0);
rxd : in STD_LOGIC;
txd : out STD_LOGIC;
dout : out word_t
);
END COMPONENT;
signal dout : word_t;
signal rst : STD_LOGIC;
signal clk : STD_LOGIC;
signal halt : STD_LOGIC;
signal int : unsigned(5 downto 0);
signal btn_r : unsigned (8 downto 0);
signal dip_r : unsigned (7 downto 0);
begin
-------------------------------------------------------------------
inst_mips_embedded: mips_embedded
PORT MAP
(
rst => rst,
clk => clk,
halt => halt,
int => int,
rxd => sys_rx,
txd => sys_tx,
dout => dout
);
clk <= sys_clk_in;
rst <= not sys_rst_n_in;
ERR_LED_reg:
process(rst, clk)
begin
if rst = '1' then
sys_error <= (others => '1');
elsif rising_edge(clk) then
sys_error <= STD_LOGIC_VECTOR(dout(31 downto 30));
end if;
end process;
LED_reg:
process(rst, clk)
begin
if rst = '1' then
sys_led <= (others => '0');
elsif rising_edge(clk) then
sys_led <= STD_LOGIC_VECTOR(dout(7 downto 0));
end if;
end process;
DIP_reg:
process(rst, clk)
begin
if rst = '1' then
dip_r <= (others => '0');
elsif rising_edge(clk) then
dip_r <= unsigned(sys_dip);
end if;
end process;
BTN_reg:
process(rst, clk)
begin
if rst = '1' then
btn_r <= (others => '0');
elsif rising_edge(clk) then
btn_r <= unsigned(sys_btn);
end if;
end process;
halt <= btn_r(4) after 6.5 ns;
int(0) <= dip_r(0) and btn_r(3) after 1 ns;
int(1) <= dip_r(1) and btn_r(3) after 1 ns;
int(2) <= dip_r(2) and btn_r(3) after 1 ns;
int(3) <= dip_r(3) and btn_r(3) after 1 ns;
int(4) <= dip_r(4) and btn_r(3) after 1 ns;
int(5) <= dip_r(5) and btn_r(3) after 1 ns;
-------------------------------------------------------------------
end struct;
lib/CPUs/MIPS/src/mips_muldiv.vhd
-83
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@@ -1,83 +0,0 @@
--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: The arithmetic logic unit
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.mips_types.all;
entity muldiv is
Port
(
rst : in std_logic;
clk : in std_logic;
din_vld_hi : in std_logic;
din_vld_lo : in std_logic;
din_hi : in word_t;
din_lo : in word_t;
hilo_sel : in std_logic;
dout : out word_t
);
end muldiv;
architecture Behavioral of muldiv is
signal reg_hi, reg_lo : word_t;
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
proc_reg_out:
process(hilo_sel, reg_hi, reg_lo)
begin
if hilo_sel = '1' then
dout <= reg_hi;
else
dout <= reg_lo;
end if;
end process;
proc_reg_in:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_hi <= (others => '0');
reg_lo <= (others => '0');
elsif din_vld_hi = '1' then
if hilo_sel = '1' then
reg_hi <= din_hi;
else
reg_lo <= din_hi;
end if;
end if;
if din_vld_lo = '1' then
reg_lo <= din_lo;
end if;
end if;
end process;
--------------------------------------------------------------------------
end Behavioral;
lib/CPUs/MIPS/src/ram.vhd
-115
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@@ -1,115 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram IS
Generic
(
word_addr_width : integer := 6
);
Port
(
clk : in STD_LOGIC;
we : in unsigned(3 downto 0);
ce : in STD_LOGIC;
addr : in unsigned(31 downto 0);
din : in unsigned(31 downto 0);
dout : out unsigned(31 downto 0)
);
END ram;
ARCHITECTURE behavior OF ram IS
constant depth : natural := 2**word_addr_width;
type sram_t is array (0 to depth-1) of unsigned(7 downto 0);
function sram_clear return sram_t is
variable result : sram_t;
begin
for i in 0 to sram_t'length-1 loop
result(i) := (others => '0');
end loop;
return result;
end sram_clear;
signal sram0, sram1, sram2, sram3 : sram_t := sram_clear;
BEGIN
SRAM_RW:
process(clk)
variable index : natural range 0 to depth-1;
begin
if rising_edge(clk) and ce = '1' then
index := to_integer(addr(word_addr_width+1 downto 2));
if we(0) = '1' then
sram0(index)<= din(7 downto 0);
end if;
dout(7 downto 0) <= sram0(index);
end if;
end process;
process(clk)
variable index : natural range 0 to depth-1;
begin
if rising_edge(clk) and ce = '1' then
index := to_integer(addr(word_addr_width+1 downto 2));
if we(1) = '1' then
sram1(index)<= din(15 downto 8);
end if;
dout(15 downto 8) <= sram1(index);
end if;
end process;
process(clk)
variable index : natural range 0 to depth-1;
begin
if rising_edge(clk) and ce = '1' then
index := to_integer(addr(word_addr_width+1 downto 2));
if we(2) = '1' then
sram2(index)<= din(23 downto 16);
end if;
dout(23 downto 16) <= sram2(index);
end if;
end process;
process(clk)
variable index : natural range 0 to depth-1;
begin
if rising_edge(clk) and ce = '1' then
index := to_integer(addr(word_addr_width+1 downto 2));
if we(3) = '1' then
sram3(index)<= din(31 downto 24);
end if;
dout(31 downto 24) <= sram3(index);
end if;
end process;
end behavior;
lib/CPUs/MIPS/src/ram_ld.vhd
-177
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@@ -1,177 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
ENTITY ram IS
Generic
(
word_addr_width : integer := 6
);
Port
(
clk : in STD_LOGIC;
ce : in STD_LOGIC;
we : in unsigned(3 downto 0);
addr : in unsigned(31 downto 0);
din : in unsigned(31 downto 0);
dout : out unsigned(31 downto 0)
);
END ram;
ARCHITECTURE behavior OF ram IS
COMPONENT dpram_2w2r
Generic
(
addr_width : integer;
data_width : integer
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
END COMPONENT;
signal jtag_clk : STD_LOGIC;
signal jtag_we : unsigned(3 downto 0);
signal jtag_addr : unsigned (15 downto 0);
signal jtag_dout : unsigned (31 downto 0);
signal jtag_din : unsigned (31 downto 0);
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
signal user_regi, user_rego : unsigned (47 downto 0);
BEGIN
gen_sram:
for i in 0 to 3 generate
begin
inst_dpram_2w2r : dpram_2w2r
GENERIC MAP
(
addr_width => word_addr_width,
data_width => 8
)
PORT MAP
(
clk_a => clk,
en_a => ce,
we_a => we(i),
addr_a => addr(word_addr_width+1 downto 2),
din_a => din((i+1)*8-1 downto i*8),
dout_a => dout((i+1)*8-1 downto i*8),
clk_b => jtag_clk,
en_b => jtag_we(i),
we_b => jtag_we(i),
addr_b => jtag_addr(word_addr_width-1 downto 0),
din_b => jtag_din((i+1)*8-1 downto i*8),
dout_b => jtag_dout((i+1)*8-1 downto i*8)
);
end generate;
--------------------------------------------------------------------------
-- Virtex-4: JTAG Loader
--------------------------------------------------------------------------
i00_BUFG : BUFG
port map
(
O => bs_clk1,
I => bs_clk0
);
i01_BUFG : BUFG
port map
(
O => bs_update1,
I => bs_update0
);
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
generic map
(
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
)
port map
(
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
DRCK => bs_clk0, -- Data register output for USER functions
RESET => bs_rst, -- Reset output from TAP controller
SEL => bs_sel, -- USER active output
SHIFT => bs_shift, -- SHIFT output from TAP controller
TDI => bs_tdi, -- TDI output from TAP controller
UPDATE => bs_update0, -- UPDATE output from TAP controller
TDO => bs_tdo -- Data input for USER function
);
jtag_addr <= user_regi(user_regi'left downto jtag_dout'length);
jtag_din <= user_regi(jtag_dout'length-1 downto 0);
jtag_clk <= bs_update1;
jtag_we <= (3 downto 0 => bs_sel);
sipo:
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
begin
if bs_rst = '1' then
user_regi <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
end if;
end if;
end process;
piso:
process (bs_rst, bs_clk1, bs_shift, user_rego)
begin
bs_tdo <= user_rego(0);
if bs_rst = '1' then
user_rego <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
else
user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;
end if;
end if;
end process;
--------------------------------------------------------------------------
end behavior;
lib/CPUs/MIPS/src/ram_sim.vhd
-88
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@@ -1,88 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The ROM file for use in your VHDL design
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram IS
Generic
(
word_addr_width : integer := 6
);
Port
(
clk : in STD_LOGIC;
ce : in STD_LOGIC;
we : in unsigned(3 downto 0);
addr : in unsigned(31 downto 0);
din : in unsigned(31 downto 0);
dout : out unsigned(31 downto 0)
);
END ram;
ARCHITECTURE behavior OF ram IS
constant depth : natural := 2**word_addr_width;
type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
function sram_clear return sram_t is
variable result : sram_t;
begin
for i in 0 to sram_t'length-1 loop
result(i) := (others => '0');
end loop;
return result;
end sram_clear;
signal sram : sram_t := sram_clear;
BEGIN
SRAM_RW:
process(clk)
variable index : natural range 0 to depth-1;
begin
if rising_edge(clk) and ce = '1' then
index := to_integer(addr(word_addr_width+1 downto 2));
if we(0) = '1' then
sram(index)(7 downto 0) <= din(7 downto 0);
end if;
if we(1) = '1' then
sram(index)(15 downto 8) <= din(15 downto 8);
end if;
if we(2) = '1' then
sram(index)(23 downto 16) <= din(23 downto 16);
end if;
if we(3) = '1' then
sram(index)(31 downto 24) <= din(31 downto 24);
end if;
dout <= sram(index);
end if;
end process;
end behavior;
lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd
-4222
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lib/CPUs/MIPS/src/tb_eval_muldiv.vhd
-156
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@@ -1,156 +0,0 @@
-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: Testbench for JCPU
-- also writes 'opc.lst' for JASM-assembler
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.mips_types.all;
use work.mips_instr.all;
ENTITY tb_eval_muldiv IS
END tb_eval_muldiv;
ARCHITECTURE behavior OF tb_eval_muldiv IS
constant CLK_PERIOD : time := 10 ns;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal ce : std_logic := '0';
signal mul_divn : std_logic := '1';
signal op_valid : std_logic := '0';
signal op1_in : word_t := (others => '-');
signal op2_in : word_t := (others => '-');
signal result : unsigned (2*word_t'length-1 downto 0);
signal res_valid : std_logic;
signal busy : std_logic;
signal result_reg : unsigned (2*word_t'length-1 downto 0);
subtype pp_t is unsigned (39 downto 0);
signal pp0, pp1, pp2, pp3 : pp_t;
signal signed_mul : std_logic := '1';
signal sign1 : std_logic;
signal sign2 : std_logic;
signal cy : std_logic;
BEGIN
sign1 <= signed_mul and op1_in(op1_in'left);
sign2 <= signed_mul and op2_in(op1_in'left);
cy <= sign1;
pp0 <= op1_in * op2_in(7 downto 0);
pp1 <= op1_in * op2_in(15 downto 8);
pp2 <= op1_in * op2_in(23 downto 16);
pp3 <= op1_in * op2_in(31 downto 24);
result <= ((63 downto 40 => '0') & pp0)
+ ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0'))
+ ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0'))
+ (pp3 & (23 downto 0 => '0'));
result_reg <= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000"));
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
rst <= '0';
wait for 10*CLK_PERIOD;
wait until rising_edge(clk);
ce <= '1';
wait for 10*CLK_PERIOD;
op1_in <= X"FFFF_FFFA"; -- (-6)
op2_in <= X"0000_0005"; -- (+5)
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"0000_0006"; -- (+6)
op2_in <= X"FFFF_FFFB"; -- (-5)
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"1234_5678";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"1234_5678";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"1234_5678";
op2_in <= X"1234_5678";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"789A_BCDE";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"789A_BCDE";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait;
end process;
END;
lib/CPUs/MIPS/src/tb_mips_embedded.vhd
-82
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@@ -1,82 +0,0 @@
-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: Testbench for JCPU
-- also writes 'opc.lst' for JASM-assembler
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.mips_types.all;
ENTITY tb_mips_embedded IS
END tb_mips_embedded;
ARCHITECTURE behavior OF tb_mips_embedded IS
COMPONENT mips_embedded
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
halt : in STD_LOGIC;
dout : out word_t
);
END COMPONENT;
constant CLK_PERIOD : time := 10 ns;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal halt : std_logic := '0';
signal dout : word_t;
BEGIN
uut: mips_embedded
PORT MAP(
rst => rst,
clk => clk,
halt => halt,
dout => dout
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
END;
lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd
-123
View File
@@ -1,123 +0,0 @@
-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: Testbench for JCPU
-- also writes 'opc.lst' for JASM-assembler
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
ENTITY tb_mips_embedded_syn IS
END tb_mips_embedded_syn;
ARCHITECTURE behavior OF tb_mips_embedded_syn IS
COMPONENT mips_embedded_syn
Port
(
sys_rst_n_in : in STD_LOGIC;
sys_clk_in : in STD_LOGIC;
sys_dip : in STD_LOGIC_VECTOR (7 downto 0);
sys_btn : in STD_LOGIC_VECTOR (8 downto 0);
sys_led : out STD_LOGIC_VECTOR (7 downto 0);
sys_rx : in STD_LOGIC;
sys_tx : out STD_LOGIC;
sys_error : out STD_LOGIC_VECTOR (1 downto 0)
);
END COMPONENT;
constant CLK_PERIOD : time := 10.0 ns;
signal sys_rst_n_in : std_logic := '0';
signal sys_clk_in : std_logic := '1';
signal sys_led : STD_LOGIC_VECTOR (7 downto 0);
signal sys_btn : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
signal sys_dip : STD_LOGIC_VECTOR (7 downto 0) := "10001001";
signal sys_error : STD_LOGIC_VECTOR (1 downto 0);
signal sys_rx : std_logic := '1';
signal sys_tx : std_logic;
BEGIN
uut: mips_embedded_syn
PORT MAP
(
sys_rst_n_in => sys_rst_n_in,
sys_clk_in => sys_clk_in,
sys_btn => sys_btn,
sys_dip => sys_dip,
sys_led => sys_led,
sys_rx => sys_rx,
sys_tx => sys_tx,
sys_error => sys_error
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
sys_clk_in <= not sys_clk_in;
end process;
STIMULUS1: process
begin
wait for 3*CLK_PERIOD;
wait until rising_edge(sys_clk_in);
sys_rst_n_in <= '1';
-- wait for 9994999*CLK_PERIOD;
-- for i in 1 to 10000 loop
-- wait for 100*CLK_PERIOD;
-- sys_btn(3) <= '1';
-- wait for 10*CLK_PERIOD;
-- sys_btn(3) <= '0';
-- end loop;
wait until rising_edge(sys_clk_in) and now = 38980 ns;
sys_btn <= "000001000";
wait until rising_edge(sys_clk_in);
sys_btn <= "000000000";
wait;
end process;
STIMULUS2: process
begin
wait for 9999999*CLK_PERIOD;
for i in 1 to 10000 loop
wait for 137*CLK_PERIOD;
sys_btn(4) <= '1';
wait for 21*CLK_PERIOD;
sys_btn(4) <= '0';
end loop;
wait;
end process;
END;
lib/CPUs/MIPS/src/tb_mips_muldiv.vhd
+56 -32
View File
@@ -63,12 +63,14 @@ ARCHITECTURE behavior OF tb_mips_muldiv IS
signal start : std_logic := '0';
signal din_hi : word_t := (others => '-');
signal din_lo : word_t := (others => '-');
signal ref_hi : word_t := (others => '-');
signal ref_lo : word_t := (others => '-');
signal dout : word_t;
signal hilo_sel : std_logic := '0';
signal result : unsigned (2*word_t'length-1 downto 0);
signal md_result : unsigned (2*word_t'length-1 downto 0) := (others => '0');
signal ref_result : unsigned (2*word_t'length-1 downto 0);
signal ref_hi : unsigned (word_t'length-1 downto 0);
signal rtmp : unsigned (2*word_t'length-1 downto 0);
signal tmp2 : unsigned (word_t'length-1 downto 0);
signal check : std_logic;
type word_array_t is array (natural range <>) of word_t;
@@ -164,35 +166,31 @@ CLK_GEN: process
end process;
REF_GEN: process
variable tmp : unsigned (2*word_t'length-1 downto 0);
variable tmp2 : unsigned (word_t'length-1 downto 0);
begin
if mul_divn = '0' then
wait until rising_edge(clk) and start = '1';
ref_lo <= din_lo;
ref_hi <= din_hi;
wait until rising_edge(clk) and busy = '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk) and check = '1';
if s_un = '1' then
tmp := unsigned(signed(result(31 downto 0)) * signed(ref_lo));
tmp2 := unsigned(signed(tmp(31 downto 0)) + signed(result(63 downto 32)));
ref_result <= X"00000000" & tmp2(31 downto 0);
rtmp <= unsigned(signed(md_result(31 downto 0)) * signed(din_lo));
wait until rising_edge(clk);
tmp2 <= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32)));
wait until rising_edge(clk);
ref_hi <= tmp2(31 downto 0);
else
tmp := result(31 downto 0) * ref_lo;
tmp2 := tmp(31 downto 0) + result(63 downto 32);
ref_result <= X"00000000" & tmp2(31 downto 0);
rtmp <= md_result(31 downto 0) * din_lo;
wait until rising_edge(clk);
tmp2 <= rtmp(31 downto 0) + md_result(63 downto 32);
wait until rising_edge(clk);
ref_hi <= tmp2(31 downto 0);
end if;
wait until rising_edge(clk);
if ref_lo /= X"00000000" then
if din_lo /= X"00000000" then
if ENABLE_FAIL_REPORT then
assert ref_hi = ref_result(31 downto 0) report "Error on divison" severity failure;
assert din_hi = ref_hi report "Error on divison" severity failure;
end if;
end if;
else
wait until rising_edge(clk) and start = '1';
wait until rising_edge(clk) and busy = '0';
wait until rising_edge(clk) and check = '1';
if s_un = '1' then
ref_result <= unsigned(signed(din_hi) * signed(din_lo));
else
@@ -202,7 +200,7 @@ REF_GEN: process
wait until rising_edge(clk);
wait until rising_edge(clk);
if ENABLE_FAIL_REPORT then
assert ref_result = result report "Error on multiplication" severity failure;
assert ref_result = md_result report "Error on multiplication" severity failure;
end if;
end if;
@@ -221,6 +219,7 @@ STIMULUS: process
s_un <= '0';
for i in 0 to operands'length-1 loop
for j in 0 to operands'length-1 loop
check <= '0';
wait until rising_edge(clk) and busy = '0';
din_hi <= operands(i);
din_lo <= operands(j);
@@ -231,17 +230,23 @@ STIMULUS: process
-- Read result
wait until rising_edge(clk) and busy = '0';
result(31 downto 0) <= dout;
wait until rising_edge(clk);
md_result(31 downto 0) <= dout;
wait until rising_edge(clk);
hilo_sel <= '1';
wait until rising_edge(clk);
result(63 downto 32) <= dout;
wait for 2*CLK_PERIOD;
md_result(63 downto 32) <= dout;
check <= '1';
wait until rising_edge(clk);
check <= '0';
wait for 8*CLK_PERIOD;
end loop;
end loop;
s_un <= '1';
for i in 0 to operands'length-1 loop
for j in 0 to operands'length-1 loop
check <= '0';
wait until rising_edge(clk) and busy = '0';
din_hi <= operands(i);
din_lo <= operands(j);
@@ -252,11 +257,16 @@ STIMULUS: process
-- Read result
wait until rising_edge(clk) and busy = '0';
result(31 downto 0) <= dout;
wait until rising_edge(clk);
md_result(31 downto 0) <= dout;
wait until rising_edge(clk);
hilo_sel <= '1';
wait until rising_edge(clk);
result(63 downto 32) <= dout;
wait for 2*CLK_PERIOD;
md_result(63 downto 32) <= dout;
check <= '1';
wait until rising_edge(clk);
check <= '0';
wait for 8*CLK_PERIOD;
end loop;
end loop;
@@ -264,6 +274,7 @@ STIMULUS: process
s_un <= '0';
for i in 0 to operands'length-1 loop
for j in 0 to operands'length-1 loop
check <= '0';
wait until rising_edge(clk) and busy = '0';
din_hi <= operands(i);
din_lo <= operands(j);
@@ -274,16 +285,23 @@ STIMULUS: process
-- Read result
wait until rising_edge(clk) and busy = '0';
result(31 downto 0) <= dout;
wait until rising_edge(clk);
md_result(31 downto 0) <= dout;
wait until rising_edge(clk);
hilo_sel <= '1';
wait until rising_edge(clk);
result(63 downto 32) <= dout;
md_result(63 downto 32) <= dout;
check <= '1';
wait until rising_edge(clk);
check <= '0';
wait for 8*CLK_PERIOD;
end loop;
end loop;
s_un <= '1';
for i in 0 to operands'length-1 loop
for j in 0 to operands'length-1 loop
check <= '0';
wait until rising_edge(clk) and busy = '0';
din_hi <= operands(i);
din_lo <= operands(j);
@@ -294,10 +312,16 @@ STIMULUS: process
-- Read result
wait until rising_edge(clk) and busy = '0';
result(31 downto 0) <= dout;
wait until rising_edge(clk);
md_result(31 downto 0) <= dout;
wait until rising_edge(clk);
hilo_sel <= '1';
wait until rising_edge(clk);
result(63 downto 32) <= dout;
md_result(63 downto 32) <= dout;
check <= '1';
wait until rising_edge(clk);
check <= '0';
wait for 8*CLK_PERIOD;
end loop;
end loop;
lib/CPUs/MIPS/src/tb_mips_top.vhd
+337 -106
View File
@@ -25,148 +25,379 @@
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.mips_types.all;
use work.mips_instr.all;
use work.async_types.all;
use work.async_defs.all;
ENTITY tb_mips_top IS
END tb_mips_top;
ARCHITECTURE behavior OF tb_mips_top IS
COMPONENT mips_top
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
halt : in STD_LOGIC;
imem_din : in unsigned (WORD_WIDTH-1 downto 0);
imem_addr : out unsigned (WORD_WIDTH-1 downto 0);
dmem_we : out STD_LOGIC;
dmem_re : out STD_LOGIC;
dmem_din : in unsigned (WORD_WIDTH-1 downto 0);
dmem_dout : out unsigned (WORD_WIDTH-1 downto 0);
dmem_addr : out unsigned (WORD_WIDTH-1 downto 0)
);
END COMPONENT;
constant CLK_PERIOD : time := 10 ns;
constant SRAM_ADDR_WIDTH : integer := 14; -- bits
constant FLASH_ADDR_WIDTH : integer := 14; -- bits
signal debug : unsigned(1 downto 0);
COMPONENT rom
Port
(
clk : in STD_LOGIC;
addr : in word_t;
dout : out word_t
);
END COMPONENT;
-- Master
signal rst : STD_LOGIC := '1';
signal clk : STD_LOGIC := '0';
signal ACK_I : STD_LOGIC := '0';
signal SRDY_I : STD_LOGIC := '0';
signal ADDR_O : word_t;
signal DAT_I : word_t := (others => '0');
signal DAT_O : word_t;
signal WE_O : STD_LOGIC;
signal SEL_O : unsigned(3 downto 0);
signal CYC_O : STD_LOGIC;
signal STB_O : STD_LOGIC;
signal MRDY_O : STD_LOGIC;
signal INT : unsigned (5 downto 0) := (others => '0');
-- Slaves
signal CYC_I_rom : std_logic;
signal ACK_O_rom : std_logic;
signal SRDY_O_rom : std_logic;
signal DAT_O_rom : unsigned(31 downto 0);
COMPONENT ram
Generic
(
word_addr_width : integer
);
Port
(
clk : in STD_LOGIC;
we : in STD_LOGIC;
addr : in word_t;
din : in word_t;
dout : out word_t
);
END COMPONENT;
signal CYC_I_flash : std_logic;
signal ACK_O_flash : std_logic;
signal SRDY_O_flash : std_logic;
signal DAT_O_flash : unsigned(31 downto 0);
constant CLK_PERIOD : time := 10 ns;
signal CYC_I_sram : std_logic;
signal ACK_O_sram : std_logic;
signal SRDY_O_sram : std_logic;
signal DAT_O_sram : unsigned(31 downto 0);
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal cpu_halt : std_logic;
signal irom_data : word_t := (others => '-');
signal irom_addr : word_t;
signal dmem_din : word_t := (others => '-');
signal dmem_dout : word_t;
signal dmem_addr : word_t;
signal dmem_we : std_logic;
signal dmem_re : std_logic;
signal CYC_I_gpio : std_logic;
signal ACK_O_gpio : std_logic;
signal SRDY_O_gpio : std_logic;
signal DAT_O_gpio : unsigned(31 downto 0);
signal CYC_I_uart : std_logic;
signal ACK_O_uart : std_logic;
signal SRDY_O_uart : std_logic;
signal DAT_O_uart : unsigned(31 downto 0);
signal flash_cs_n : std_logic;
signal flash_oe_n : std_logic;
signal sram_cs_n : std_logic;
signal sram_wr_n : unsigned(3 downto 0);
signal sram_oe_n : std_logic;
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
signal sram_d : unsigned(31 downto 0);
signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
signal flash_d : unsigned(31 downto 0);
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0) := (others => '0');
signal gpi1 : unsigned(31 downto 0) := (others => '0');
signal int_uart_rx : std_logic;
signal rx : std_logic := '1';
signal tx : std_logic;
type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
signal mem_area : mem_area_t;
type word_array_t is array (natural range <>) of word_t;
signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
BEGIN
uut: mips_top
PORT MAP(
rst => rst,
clk => clk,
halt => cpu_halt,
imem_din => irom_data,
imem_addr => irom_addr,
dmem_we => dmem_we,
dmem_re => dmem_re,
dmem_din => dmem_din,
dmem_dout => dmem_dout,
dmem_addr => dmem_addr
);
inst_rom: rom
PORT MAP
(
clk => clk,
addr => irom_addr,
dout => irom_data
);
inst_ram: ram
GENERIC MAP
(
word_addr_width => 6
)
PORT MAP
(
clk => clk,
we => dmem_we,
addr => dmem_addr,
din => dmem_dout,
dout => dmem_din
);
------------------------------------------------------------------
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
HLT_GEN:
process(rst, clk)
subtype cnt_t is natural range 0 to 2;
variable cnt : cnt_t;
------------------------------------------------------------------
-- Memory mux
------------------------------------------------------------------
mem_mux:
process(ADDR_O)
begin
if rst = '1' then
cnt := cnt_t'high;
cpu_halt <= '0';
elsif rising_edge(clk) then
cpu_halt <= '0';
if cnt /= 0 then
cnt := cnt - 1;
else
cnt := cnt_t'high;
cpu_halt <= '1';
mem_area <= mem_dead;
if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash;
elsif ADDR_O(31 downto 28) = X"A" then
if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then
mem_area <= mem_gpio;
elsif ADDR_O(18 downto 16) = "001" then
mem_area <= mem_uart;
end if;
elsif ADDR_O(27 downto 26) = "01" then
mem_area <= mem_flash;
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sram;
end if;
end process;
signal_mux:
process(mem_area, CYC_O)
begin
CYC_I_uart <= '0';
CYC_I_gpio <= '0';
CYC_I_flash <= '0';
CYC_I_rom <= '0';
CYC_I_sram <= '0';
case mem_area is
when mem_gpio =>
CYC_I_gpio <= CYC_O;
when mem_uart =>
CYC_I_uart <= CYC_O;
when mem_flash =>
CYC_I_flash <= CYC_O;
when mem_rom =>
CYC_I_rom <= CYC_O;
when mem_sram =>
CYC_I_sram <= CYC_O;
when others => null;
end case;
end process;
SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio;
ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio;
DAT_I <= DAT_O_sram when CYC_I_sram = '1' else
DAT_O_rom when CYC_I_rom = '1' else
DAT_O_flash when CYC_I_flash = '1' else
DAT_O_uart when CYC_I_uart = '1' else
DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
------------------------------------------------------------------
uut: entity work.mips_top
PORT MAP
(
debug => debug,
RST_I => rst,
CLK_I => clk,
ACK_I => ACK_I,
SRDY_I => SRDY_I,
ADDR_O => ADDR_O,
DAT_I => DAT_I,
DAT_O => DAT_O,
WE_O => WE_O,
SEL_O => SEL_O,
CYC_O => CYC_O,
STB_O => STB_O,
MRDY_O => MRDY_O,
INT => INT
);
INT(1) <= int_uart_rx;
inst_rom : entity work.rom_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_rom,
STB_I => STB_O,
ACK_O => ACK_O_rom,
MRDY_I => MRDY_O,
SRDY_O => SRDY_O_rom,
ADDR_I => ADDR_O,
DAT_O => DAT_O_rom
);
inst_gpio : entity work.gpio_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_gpio,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_gpio,
SRDY_O => SRDY_O_gpio,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_O_gpio,
sys_gpo0 => gpo0,
sys_gpo1 => gpo1,
sys_gpi0 => gpi0,
sys_gpi1 => gpi1
);
inst_flash_port : entity work.async_port_wb
GENERIC MAP
(
addr_width => FLASH_ADDR_WIDTH,
data_width => 32,
byte_sel_width => 1,
async_timespec => ts_flash
)
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_flash,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_flash,
SRDY_O => SRDY_O_flash,
MRDY_I => MRDY_O,
SEL_I => SEL_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_O_flash,
async_a => flash_a,
async_d => flash_d,
async_cs => flash_cs_n,
async_wr => open,
async_rd => flash_oe_n,
async_rst => open
);
inst_sram_port : entity work.async_port_wb
GENERIC MAP
(
addr_width => SRAM_ADDR_WIDTH,
data_width => 32,
byte_sel_width => 4,
async_timespec => ts_sram
)
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_sram,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_sram,
SRDY_O => SRDY_O_sram,
MRDY_I => MRDY_O,
SEL_I => SEL_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_O_sram,
async_a => sram_a,
async_d => sram_d,
async_cs => sram_cs_n,
async_wr => sram_wr_n,
async_rd => sram_oe_n,
async_rst => open
);
inst_uart : entity work.uart_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_uart,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_uart,
SRDY_O => SRDY_O_uart,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_O_uart,
INT_RX_O => int_uart_rx,
INT_TX_O => open,
ser_rx => rx,
ser_tx => tx
);
------------------------------------------------------------------
SRAM_READ:
process(sram_a, sram_cs_n, sram_oe_n)
begin
sram_d <= (others => 'Z');
if sram_oe_n = '0' then
if sram_cs_n = '0' then
sram_d <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)));
end if;
end if;
end process;
SRAM_WRITE:
process(sram_a, sram_cs_n, sram_wr_n)
begin
if rising_edge(sram_wr_n(0)) then
if sram_cs_n = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
end if;
end if;
if rising_edge(sram_wr_n(1)) then
if sram_cs_n = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
end if;
end if;
if rising_edge(sram_wr_n(2)) then
if sram_cs_n = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
end if;
end if;
if rising_edge(sram_wr_n(3)) then
if sram_cs_n = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
end if;
end if;
end process;
------------------------------------------------------------------
FLASH_READ:
process(rst, flash_cs_n, flash_oe_n, flash_a)
type file_t is file of integer;
file load_flash : file_t open read_mode is "hello.flash.bin";
variable instr : integer;
variable index : natural;
variable temp : signed(31 downto 0);
begin
if rst = '1' then
index := 0;
while not endfile(load_flash) loop
read(load_flash, instr);
temp := to_signed(instr, word_t'length);
flash_data(index) <= unsigned(temp);
index := index + 1;
end loop;
else
flash_d <= (others => 'Z') after 10 ns;
if flash_oe_n = '0' and flash_cs_n = '0' then
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
flash_d <= flash_data(index) after 10 ns;
end if;
end if;
end process;
------------------------------------------------------------------
STIMULUS: process
begin
-- for i in 0 to instr_name_array'length-1 loop
-- fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
-- end loop;
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
rst <= '0';
wait for 2*CLK_PERIOD;
-- assert false report "Test finished" severity error;
wait;
end process;
lib/CPUs/MIPS/src/testbench.ROM_ld.vhd
-4222
View File
File diff suppressed because it is too large Load Diff
lib/CPUs/MIPS/syn/ise101/mips_top.prj
+20
View File
@@ -0,0 +1,20 @@
vhdl work "../../src/core/mips_types.vhd"
vhdl work "../../../../misc/dpram_2w2r.vhd"
vhdl work "../../../../misc/dpram_1w1r_dist.vhd"
vhdl work "../../../../misc/dpram_1w1r.vhd"
vhdl work "../../../../FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../src/core/mips_instr.vhd"
vhdl work "../../../../FIFO/src/fifo_sync_dist.vhd"
vhdl work "../../src/core/mips_shifter.vhd"
vhdl work "../../src/core/mips_reg.vhd"
vhdl work "../../src/core/mips_muldiv.vhd"
vhdl work "../../src/core/mips_idecode_rom.vhd"
vhdl work "../../src/core/mips_icache.vhd"
vhdl work "../../src/core/mips_dcache.vhd"
vhdl work "../../src/core/mips_cop.vhd"
vhdl work "../../src/core/mips_bcu.vhd"
vhdl work "../../src/core/mips_alu.vhd"
vhdl work "../../src/core/mips_pipeline.vhd"
vhdl work "../../src/core/mips_biu.vhd"
vhdl work "../../src/core/mips_top.vhd"
lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
+20
View File
@@ -0,0 +1,20 @@
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
lib/CPUs/MIPS/todo.txt
+5
View File
@@ -0,0 +1,5 @@
2008-10-26
- Optimierung: MUL32x32 primitive für Virtex-4
- External COP 1..3 interface
- FPU (COP1)
- MMU
lib/CPUs/MIPS/tools/Makefile
+16 -7
View File
@@ -1,8 +1,17 @@
all: ramgen romgen
CFLAGS=-O2
ramgen: src/ramgen.c
gcc -o ./ramgen.exe src/ramgen.c
romgen: src/romgen.c
gcc -o ./romgen.exe src/romgen.c
CC=gcc
all: romgen ramgen flashgen
romgen: ./src/romgen.c
$(CC) $(CFLAGS) ./src/romgen.c -o ./romgen
ramgen: ./src/ramgen.c
$(CC) $(CFLAGS) ./src/ramgen.c -o ./ramgen
flashgen: ./src/flashgen.c
$(CC) $(CFLAGS) ./src/flashgen.c -o ./flashgen
clean:
rm -rf romgen* ramgen* flashgen*
lib/CPUs/MIPS/tools/insrom.rb
-46
View File
@@ -1,46 +0,0 @@
#!/usr/bin/env ruby
# ----------------------------------------------------------------------
# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
# This file: Insertion of code fragments into templates
#
# Copyright (C) 2008 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
arg = $*
rom_filename = arg[0].to_s
tpl_filename = arg[1].to_s
subst_pattern = "ROM_INSERT_HERE"
# --------------------------------------------------------
# Open file
# --------------------------------------------------------
romfile = File.open(rom_filename, "r")
tplfile = File.open(tpl_filename, "r")
re = Regexp.new(subst_pattern)
while (line = tplfile.gets)
puts line
line.scan(re).each do |word|
romfile.each do |raw_line|
puts raw_line
end
end
end
lib/CPUs/MIPS/tools/irom_ld.vhd.tpl
-147
View File
@@ -1,147 +0,0 @@
-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: loadable ROM
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
ENTITY irom IS
Port (
clk : in STD_LOGIC;
addr : in inst_addr_t;
dout : out inst_t
);
END irom;
ARCHITECTURE loadable OF irom IS
-- JASM_ROM_INSERT_HERE
signal jtag_ld_clk : STD_LOGIC;
signal jtag_ld_we : STD_LOGIC;
signal jtag_ld_addr : unsigned (15 downto 0);
signal jtag_ld_dout : unsigned (31 downto 0);
signal jtag_ld_din : unsigned (31 downto 0);
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
signal user_regi, user_rego : unsigned (47 downto 0);
constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
begin
--------------------------------------------------------------------------
-- Virtex-4: JTAG Loader
--------------------------------------------------------------------------
i00_BUFG : BUFG
port map
(
O => bs_clk1,
I => bs_clk0
);
i01_BUFG : BUFG
port map
(
O => bs_update1,
I => bs_update0
);
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
generic map
(
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
)
port map
(
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
DRCK => bs_clk0, -- Data register output for USER functions
RESET => bs_rst, -- Reset output from TAP controller
SEL => bs_sel, -- USER active output
SHIFT => bs_shift, -- SHIFT output from TAP controller
TDI => bs_tdi, -- TDI output from TAP controller
UPDATE => bs_update0, -- UPDATE output from TAP controller
TDO => bs_tdo -- Data input for USER function
);
jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
jtag_ld_clk <= bs_update1;
jtag_ld_we <= bs_sel;
sipo:
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
begin
if bs_rst = '1' then
user_regi <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
end if;
end if;
end process;
piso:
process (bs_rst, bs_clk1, bs_shift, user_rego)
begin
bs_tdo <= user_rego(0);
if bs_rst = '1' then
user_rego <= (others => '0');
elsif rising_edge(bs_clk1) then
if bs_shift = '1' then
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
else
user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;
-- user_rego <= id;
end if;
end if;
end process;
PROM_WRITE:
process(jtag_ld_clk, jtag_ld_we)
begin
if rising_edge(jtag_ld_clk) then
if jtag_ld_we = '1' then
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
else
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
end if;
end if;
end process;
--------------------------------------------------------------------------
-- ROM Read/Write
--------------------------------------------------------------------------
PROM_READ:
process(clk)
begin
if rising_edge(clk) then
dout <= imem_rom(to_integer(addr));
end if;
end process;
--------------------------------------------------------------------------
end loadable;
lib/CPUs/MIPS/tools/make.sh
-51
View File
@@ -1,51 +0,0 @@
#!/bin/sh
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: rom-file generation for cpu_core
#
# Copyright (C) 2007 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
# $Header: /tmp/cvsroot/VHDL/lib/CPUs/MIPS/tools/make.sh,v 1.1 2008-08-25 08:29:55 Jens Exp $
# ----------------------------------------------------------------------
TARGET=$2
DSTDIR=$1
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
$JASM_HOME/jasm.rb $TARGET.jsm
irom_tcl_snippet="$TARGET.irom.tcl.snip"
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
rm -f *.snip
lib/CPUs/MIPS/tools/rom.tcl.tpl
-61
View File
@@ -1,61 +0,0 @@
# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: The ROM file for upload to target over JTAG
#
# Copyright (C) 2007 J. Ahrensfeld
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# For questions and ideas, please contact the author at jens@jayfield.org
#
# ---------------------------------------------------------------------
# ---------------------------------------------------------------------
# For Chipscope 9.1
# ---------------------------------------------------------------------
# Source JTAG/TCL frame work
cd $env(CHIPSCOPE)\\bin\\nt
source csejtag.tcl
namespace import ::chipscope::*
# Platform USB Cable
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
# Create session
set handle [::chipscope::csejtag_session create 0]
# Open JTAG and lock
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
set lock_result [::chipscope::csejtag_target lock $handle 1000]
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
# Get Device ID
set devtype "Virtex-4SX"
set devid 2
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
set CSE_OP $CSEJTAG_SHIFT_READWRITE
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
# Write Program
# JASM_ROM_INSERT_HERE
::chipscope::csejtag_target unlock $handle
::chipscope::csejtag_target close $handle
::chipscope::csejtag_session destroy $handle
exit
lib/CPUs/MIPS/tools/src/flashgen.c
+117
View File
@@ -0,0 +1,117 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#define INT8 char
#define INT16 short
#define INT32 long
#define UINT8 unsigned char
#define UINT16 unsigned short
#define UINT32 unsigned long
#define INT int
#define UINT unsigned int
#define FLOAT32 float
#define FLOAT64 double
#define SDRAM_BASE 0x40000000
#define FLASH_OFFSET 0x00000000
// --------------------------------------------------------------
typedef struct _sflash_img_hdr_t
{
UINT8 magic[4];
UINT32 target_addr;
UINT32 img_offset;
UINT32 img_size;
UINT32 hdr_next;
UINT8 img_name[128];
UINT8 res[108];
} flash_img_hdr_t;
// --------------------------------------------------------------
void basename(char *pSrc, char *pDst)
{
int i, size;
size = strlen(pSrc);
while(pSrc[size] != '.')
size--;
for (i=0; i < size; i++)
pDst[i] = pSrc[i];
pDst[i] = 0;
}
// --------------------------------------------------------------
int main(int argc, char *argv[])
{
char *pFilenameIn;
char name_flash[1024];
char name_prj[1024];
char *pBuf;
flash_img_hdr_t img_hdr = {0};
FILE *pFile;
int filesize;
long start, end;
int i;
if (argc < 2)
{
fprintf(stderr, "Usage: flashgen <input file>\n");
return 1;
}
pFilenameIn = argv[1];
pFile = fopen(pFilenameIn, "rb");
if (!pFile)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
basename(pFilenameIn, name_prj);
sprintf(name_flash, "%s.flash.bin", name_prj);
// determine filesize
fseek(pFile, 0, SEEK_SET);
start = ftell(pFile);
fseek(pFile, 0, SEEK_END);
end = ftell(pFile);
fseek(pFile, 0, SEEK_SET);
filesize = (end-start);
pBuf = (char*)malloc(filesize);
fread(pBuf, 1, filesize, pFile);
fclose(pFile);
pFile = fopen(name_flash, "wb");
if (!pFile)
{
fprintf(stderr, "Error opening file %s\n", name_flash);
return 1;
}
img_hdr.magic[0] = 'J';
img_hdr.magic[1] = 'F';
img_hdr.magic[2] = 'I';
img_hdr.magic[3] = '1';
img_hdr.target_addr = SDRAM_BASE;
img_hdr.img_size = filesize;
img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
img_hdr.hdr_next = FLASH_OFFSET;
fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
fwrite(pBuf, 1, filesize, pFile);
fclose(pFile);
return 0;
}
lib/CPUs/MIPS/tools/src/ramgen.c
+261 -1
View File
@@ -24,6 +24,260 @@ void basename(char *pSrc, char *pDst)
}
int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
long start, end;
int i, word, filesize, romsize;
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
pFileIn = fopen(pFilenameIn, "rb");
if (!pFileIn)
{
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
return 1;
}
pFileOut = fopen(pFilenameOut, "wb");
if (!pFileOut)
{
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
return 1;
}
fseek(pFileIn, 0, SEEK_SET);
start = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_END);
end = ftell(pFileIn);
fseek(pFileIn, 0, SEEK_SET);
filesize = (end-start);
romsize = (int)pow(2, nbits_addr+2);
// -------------------------------------------------------------------------
// Header
// -------------------------------------------------------------------------
fprintf(pFileOut, "LIBRARY IEEE;\n");
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "library UNISIM;\n");
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
fprintf(pFileOut, "\tPort\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "END %s;\n", ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
fprintf(pFileOut, "\t(\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// ROM part
// -------------------------------------------------------------------------
for (i=0; i < filesize; i += sizeof(int))
{
fread(&word, 1, sizeof(int), pFileIn);
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
word = 0;
for (; i < romsize; i += sizeof(int))
{
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
if (i < (romsize-sizeof(int)))
fprintf(pFileOut, ", -- %8.8X\n", i);
else
fprintf(pFileOut, " -- %8.8X\n", i);
}
fprintf(pFileOut, "\t);\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "begin\n", ARCH_NAME);
fprintf(pFileOut, "\n");
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(clk)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
// -------------------------------------------------------------------------
// Trailer
// -------------------------------------------------------------------------
fprintf(pFileOut, "\n");
fputs(tpl, pFileOut);
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
fprintf(pFileOut, "\tbegin\n");
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\telse\n");
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
fprintf(pFileOut, "\t\t\tend if;\n");
fprintf(pFileOut, "\t\tend if;\n");
fprintf(pFileOut, "\tend process;\n");
fprintf(pFileOut, "\n");
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
return 0;
}
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
{
FILE *pFileIn, *pFileOut;
@@ -97,6 +351,8 @@ int main(int argc, char *argv[])
char *pFilenameIn;
char name_prj[1024];
char name_rom_tcl[1024];
char name_rom[1024];
char name_rom_v4ld[1024];
FILE *pFileIn;
int filesize, romsize, nbits_addr, nbits_data;
@@ -105,7 +361,7 @@ int main(int argc, char *argv[])
if (argc < 2)
{
fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
return 1;
}
@@ -115,8 +371,12 @@ int main(int argc, char *argv[])
basename(pFilenameIn, name_prj);
sprintf(name_rom, "%s.vhd", name_prj);
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
sprintf(name_rom_tcl, "%s.tcl", name_prj);
SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
lib/CPUs/MIPS/tools/src/romgen.c
+1 -1
View File
@@ -4,7 +4,7 @@
#include <math.h>
#define ARCH_NAME "data"
#define ENT_NAME "icache"
#define ENT_NAME "rom"
#define JTAG_ADDR_WIDTH 16
// --------------------------------------------------------------
lib/SDRAM/ddr_sdr_v1_5/ise9/sdram_ctrl_top.prj
-13
View File
@@ -1,13 +0,0 @@
vhdl work "../../../misc/utils_pkg.vhd"
vhdl work "../src/sdram_config.vhd"
vhdl work "../../../FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../src/sdram_types.vhd"
vhdl work "../../../FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../FIFO/src/dpram.vhd"
vhdl work "../src/sdram_ctrl.vhd"
vhdl work "../src/sdram_cmd.vhd"
vhdl work "../src/reset_virtex4.vhd"
vhdl work "../src/fifo_sync.vhd"
vhdl work "../src/ddr_phy_virtex4.vhd"
vhdl work "../src/clockgen_virtex4.vhd"
vhdl work "../src/sdram_ctrl_top.vhd"
lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk
BIN
View File
Binary file not shown.
lib/SDRAM/ddr_sdr_v1_5/sim/compile_simprim.do
-6
View File
@@ -1,6 +0,0 @@
vlib simprim
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
lib/SDRAM/ddr_sdr_v1_5/sim/compile_unisim.do
-6
View File
@@ -1,6 +0,0 @@
vlib unisim
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo
-28
View File
@@ -1,28 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../src/fifo_sync.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
vcom -explicit -93 "../src/reset_virtex4.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
vcom -explicit -93 "../src/sdram_ctrl.vhd"
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../src/sdram_ctrl_frontend_wb.vhd"
vcom -explicit -93 "../src/mt46v16m16.vhd"
vcom -explicit -93 "../src/tb_sdram_ctrl_frontend_wb.vhd"
#restart -force
vsim -t 1ps -lib work tb_sdram_ctrl_frontend_wb
do {tb_sdram_ctrl_frontend_wb.wdo}
view wave
view structure
view signals
run 10us
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo
-42
View File
@@ -1,42 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt
add wave -noupdate -divider Part
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8165533 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {7279048 ps} {8233593 ps}
lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
-389
View File
@@ -1,389 +0,0 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: DDR physical layer (Virtex-4 specific)
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.sdram_config.all;
use work.sdram_types.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ddr_phy is
Port (
sys_rst : in STD_LOGIC;
sys_clk0 : in STD_LOGIC;
sys_clk270 : in STD_LOGIC;
u_tag_in : in user_tag_t;
u_tag_rd : out user_tag_t;
u_tag_wr : out user_tag_t;
read_clk : in STD_LOGIC;
phy_ctrl : in phy_ctrl_t;
part_ctrl : in part_ctrl_t;
sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0);
sdr_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0);
sdr_data_vld : out STD_LOGIC;
sdr_data_req_w : out STD_LOGIC;
sdr_data_req_r : out STD_LOGIC;
part_clk_p : out STD_LOGIC;
part_clk_n : out STD_LOGIC;
part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0);
part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0);
part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0);
part_cs_n : out STD_LOGIC;
part_we_n : out STD_LOGIC;
part_cas_n : out STD_LOGIC;
part_ras_n : out STD_LOGIC;
part_cke : out STD_LOGIC
);
end ddr_phy;
architecture tech of ddr_phy is
signal dqs_drive : std_logic;
signal drive : std_logic;
signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0);
signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0);
signal dqs_rst : std_logic;
signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0);
signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0);
signal part_ctrl_reg : part_ctrl_t;
signal we_reg : std_logic;
signal read_en : std_logic;
type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
signal u_tag_pipe : u_tag_array_t;
type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0);
signal dm_out_pipe : dm_out_array_t;
begin
------------------------------------------------------------------------------------------------------------------------------------------------
utag_pipe:
process(sys_rst, sys_clk0)
begin
if rising_edge(sys_clk0) then
for i in u_tag_pipe'length-1 downto 1 loop
u_tag_pipe(i) <= u_tag_pipe(i-1);
end loop;
if phy_ctrl.utag_we = '1' then
u_tag_pipe(0) <= u_tag_in;
end if;
end if;
end process;
dmout_pipe:
process(sys_rst, sys_clk0)
begin
if rising_edge(sys_clk0) then
for i in dm_out_pipe'length-1 downto 1 loop
dm_out_pipe(i) <= dm_out_pipe(i-1);
end loop;
if phy_ctrl.utag_we = '1' then
dm_out_pipe(0) <= sdr_dm_rd_in;
end if;
end if;
end process;
WE_REGISTER:
process(sys_rst, sys_clk0)
begin
if sys_rst = '1' then
we_reg <= '0';
elsif rising_edge(sys_clk0) then
we_reg <= phy_ctrl.we;
end if;
end process;
DATA_DRIVE_GEN:
process(sys_clk0)
begin
if falling_edge(sys_clk0) then
dqs_rst <= not we_reg;
drive <= we_reg;
end if;
end process;
DQS_DRIVE_GEN:
process(sys_clk0)
variable p : unsigned(1 downto 0);
begin
if rising_edge(sys_clk0) then
if phy_ctrl.drive_en = '1' then
p := (others => '1');
else
p := p(p'left-1 downto 0) & '0';
end if;
end if;
dqs_drive <= p(p'left);
end process;
------------------------------------------------------------------------------------------------------------------------------------------------
-- SDRAM Clock
ODDR_clk_p : ODDR
generic map
(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => part_clk_p, -- 1-bit DDR output
C => sys_clk0, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR_clk_n : ODDR
generic map
(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => part_clk_n, -- 1-bit DDR output
C => sys_clk0, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '0', -- 1-bit data input (positive edge)
D2 => '1', -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
------------------------------------------------------------------------------------------------------------------------------------------------
-- Data OUT DDR-FFs
gen_ddr_data_out:
for n in 0 to DDR_DATA_WIDTH-1 generate
begin
ODDR_data : ODDR
generic map
(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => ddr_data_w(n), -- 1-bit DDR output
C => sys_clk270, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge)
D2 => sdr_data_w(n), -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate gen_ddr_data_out;
-- Sample tristate on clock90
process (sys_clk270)
begin
if rising_edge(sys_clk270) then
for n in 0 to DDR_DATA_WIDTH-1 loop
drive270(n) <= drive;
end loop;
end if;
end process;
-- Output mux
out_mux_data:
for n in 0 to DDR_DATA_WIDTH-1 generate
part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
end generate;
------------------------------------------------------------------------------------------------------------------------------------------------
-- Data-mask OUT DDR-FFs
gen_ddr_dm_out:
for n in 0 to DDR_DM_WIDTH-1 generate
begin
ODDR_dm : ODDR
generic map
(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => part_dm(n), -- 1-bit DDR output
C => sys_clk270, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => sdr_dm_wr_in(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge)
D2 => sdr_dm_wr_in(n), -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate gen_ddr_dm_out;
------------------------------------------------------------------------------------------------------------------------------------------------
-- DQS OUT DDR-FFs
gen_dqs_out:
for n in 0 to DDR_DQS_WIDTH-1 generate
begin
ODDR_dqs : ODDR
generic map
(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => dqs(n), -- 1-bit DDR output
C => sys_clk0, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D2 => '0', -- 1-bit data input (positive edge)
D1 => '1', -- 1-bit data input (negative edge)
R => dqs_rst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate gen_dqs_out;
-- Tristate-Control fuer dqs
process (sys_clk0) is
variable zctrl : boolean;
begin
if rising_edge(sys_clk0) then
if dqs_drive = '1' then
zctrl := false;
else
zctrl := true;
end if;
if zctrl then
dqs_zen <= (others => '1');
else
dqs_zen <= (others => '0');
end if;
end if;
end process;
-- Tristate-Buffer fuer dqs
gen_out_mux_dqs:
for n in 0 to DDR_DQS_WIDTH-1 generate
part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
end generate gen_out_mux_dqs;
------------------------------------------------------------------------------------------------------------------------------------------------
process (sys_rst, sys_clk0) is
begin
if sys_rst = '1' then
part_ctrl_reg.cmd <= COMMAND(SD_DESELECT);
part_ctrl_reg.ba <= (others=>'0');
part_ctrl_reg.addr <= (others=>'0');
part_ctrl_reg.cke <= '0';
elsif rising_edge(sys_clk0) then
part_ctrl_reg <= part_ctrl;
end if;
end process;
process (sys_clk0) is
begin
if falling_edge(sys_clk0) then
part_ras_n <= part_ctrl_reg.cmd.ras_n;
part_cas_n <= part_ctrl_reg.cmd.cas_n;
part_we_n <= part_ctrl_reg.cmd.we_n;
part_cs_n <= part_ctrl_reg.cmd.cs_n;
part_ba <= part_ctrl_reg.ba;
part_addr <= part_ctrl_reg.addr;
part_cke <= part_ctrl_reg.cke;
end if;
end process;
-----------------------------------------------------------------
-- READ DATA Processing
-----------------------------------------------------------------
gen_ddr_data_in:
for n in 0 to DDR_DATA_WIDTH-1 generate
begin
IDDR_data : IDDR
generic map
(
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC"
)
port map
(
Q1 => data_r(n), -- 1-bit output for positive edge of clock
Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock
C => read_clk, -- 1-bit clock input
CE => read_en, -- 1-bit clock enable input
D => part_data(n), -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
end generate;
data_sample_stage:
process (sys_clk0)
begin
if falling_edge(sys_clk0) then
data_reg_r <= data_r;
end if;
end process;
misc_flags_and_data_out:
process (sys_rst, sys_clk0)
variable p : unsigned(3 downto 0);
begin
if sys_rst = '1' then
p := (others => '0');
read_en <= '0';
sdr_data_vld <= '0';
sdr_data_req_w <= '0';
sdr_data_req_r <= '0';
elsif rising_edge(sys_clk0) then
sdr_data_r <= data_reg_r;
if p(3) = '1' then
u_tag_rd <= u_tag_pipe(4);
sdr_dm_rd_out <= dm_out_pipe(4);
end if;
if phy_ctrl.we = '1' then
u_tag_wr <= u_tag_pipe(0);
end if;
sdr_data_req_w <= phy_ctrl.we;
sdr_data_req_r <= phy_ctrl.re;
sdr_data_vld <= p(3);
read_en <= p(1);
if phy_ctrl.re = '1' then
p := p(p'left-1 downto 0) & '1';
else
p := p(p'left-1 downto 0) & '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
end tech;
lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd
-117
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@@ -1,117 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use work.fifo_ctrl_pkg.all;
entity fifo_sync is
Generic (
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC;
data_w : in unsigned (data_width-1 downto 0);
data_r : out unsigned (data_width-1 downto 0)
);
end fifo_sync;
architecture Behavioral of fifo_sync is
signal mem_wr_en : STD_LOGIC;
signal mem_rd_en : STD_LOGIC;
signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
begin
mem_wr_en <= not full;
mem_rd_en <= not pre_empty;
fifo_full <= full;
fifo_empty <= empty;
fifo_afull <= almost_full;
fifo_aempty <= almost_empty;
inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
GENERIC MAP
(
addr_width => addr_width,
almost_full_thresh => almost_full_thresh,
almost_empty_thresh => almost_empty_thresh
)
PORT MAP
(
rst => rst,
clk => clk,
we => we,
re => re,
ptr_w => ptr_w,
ptr_r => ptr_r,
fifo_full => full,
fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_empty => pre_empty,
fifo_afull => almost_full,
fifo_aempty => almost_empty
);
inst_dpram_1w1r: entity work.dpram_1w1r_dist
GENERIC MAP (
addr_width => addr_width,
data_width => data_width
)
PORT MAP(
clka => clk,
clkb => clk,
en_a => mem_wr_en,
en_b => mem_rd_en,
we_a => we,
addr_a => ptr_w,
addr_b => ptr_r,
din_a => data_w,
dout_b => data_r
);
end Behavioral;
lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd
-1320
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lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd
-111
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@@ -1,111 +0,0 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Reset generator (Virtex-4 specific)
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity reset is
port
(
clk : in std_logic;
rst_in : in std_logic;
rst_out : out std_logic
);
end;
architecture tech of reset is
signal rst : std_logic;
signal shift_pipe : std_logic_vector(3 downto 0);
attribute KEEP : string;
attribute KEEP of shift_pipe : signal is "TRUE";
begin
rst <= shift_pipe(0);
bufg_reset: bufg
port map
(
o => rst_out,
i => rst
);
fdp0: fdp
generic map
(
init => '1'
)
port map
(
d => rst_in,
c => clk,
pre => '0',
q => shift_pipe(3)
);
fdp1: fdp
generic map
(
init => '1'
)
port map
(
d => shift_pipe(3),
c => clk,
pre => '0',
q => shift_pipe(2)
);
fdp2: fdp
generic map
(
init => '1'
)
port map
(
d => shift_pipe(2),
c => clk,
pre => '0',
q => shift_pipe(1)
);
fdp3: fdp
generic map
(
init => '1'
)
port map
(
d => shift_pipe(1),
c => clk,
pre => '0',
q => shift_pipe(0)
);
end tech;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
-269
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@@ -1,269 +0,0 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: SDRAM command controller
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.sdram_config.all;
use work.sdram_types.all;
entity sdram_cmd is
Generic (BL : natural := 2);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
u_tag_in : in user_tag_t;
u_tag_out : out user_tag_t;
phy_ctrl : out phy_ctrl_t;
cmd : in sdr_cmd_t;
cmd_we : in STD_LOGIC;
cmd_ack : out STD_LOGIC;
col_addr : in col_addr_t;
mode_word : in mode_word_t;
sdr_cmd_ctrl : out sdr_cmd_lines_t;
sdr_addr : out sdr_addr_t;
sdr_ba : out sdr_ba_t
);
end sdram_cmd;
architecture behaviour of sdram_cmd is
signal st_sdr, st_sdr_next : sdr_state_t;
signal cc_preset : natural range 0 to 10;
signal cc_load_en : std_logic;
signal cycle_finished : std_logic;
signal burst_preset : natural range 0 to 3;
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
begin
u_tag_out <= u_tag_in;
------------------------------------------------------------------------------------------
fsm_sdr_state:
process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
begin
st_sdr_next <= st_sdr;
sdr_cmd_ctrl <= COMMAND(SD_NOP);
cc_load_en <= '0';
cc_preset <= TIMING(cmd);
burst_load_en <= '0';
cmd_ack <= '0';
burst_preset <= BL/2-1;
phy_ctrl.re <= '0';
phy_ctrl.drive_en <= '0';
phy_ctrl.we <= '0';
phy_ctrl.utag_we <= '0';
sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1);
case st_sdr is
when PWR_DOWN =>
sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
if enable = '1' then
st_sdr_next <= IDLE;
end if;
when PRECHARGE =>
if cycle_finished = '1' then
st_sdr_next <= IDLE;
end if;
when MODE =>
if cycle_finished = '1' then
st_sdr_next <= IDLE;
end if;
when IDLE =>
if cmd_we = '1' then
cmd_ack <= '1';
cc_load_en <= '1';
cc_preset <= TIMING(cmd);
sdr_cmd_ctrl <= COMMAND(cmd);
case cmd is
when SD_PRE =>
st_sdr_next <= PRECHARGE;
sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL);
when SD_LMR =>
st_sdr_next <= MODE;
when SD_ACT =>
st_sdr_next <= ROW_ACT;
when SD_AR =>
st_sdr_next <= AUTO_REF;
when others => null;
end case;
end if;
when ROW_ACT =>
if cycle_finished = '1' then
if cmd_we = '1' then
cmd_ack <= '1';
burst_load_en <= '1';
cc_load_en <= '1';
cc_preset <= TIMING(cmd);
sdr_cmd_ctrl <= COMMAND(cmd);
case cmd is
when SD_PRE =>
st_sdr_next <= PRECHARGE;
when SD_READ =>
phy_ctrl.utag_we <= '1';
st_sdr_next <= READ;
sdr_addr(col_addr_t'range) <= col_addr;
when SD_WRITE =>
phy_ctrl.utag_we <= '1';
phy_ctrl.drive_en <= '1';
st_sdr_next <= WRITE;
sdr_addr(col_addr_t'range) <= col_addr;
when others => null;
end case;
end if;
end if;
when WRITE =>
phy_ctrl.drive_en <= '1';
phy_ctrl.we <= '1';
if burst_finished = '1' then
if cmd_we = '1' and cmd = SD_WRITE then
sdr_addr(col_addr_t'range) <= col_addr;
cmd_ack <= '1';
burst_load_en <= '1';
sdr_cmd_ctrl <= COMMAND(cmd);
phy_ctrl.utag_we <= '1';
else
phy_ctrl.drive_en <= '0';
cc_load_en <= '1';
cc_preset <= TIMING(SD_WRITE)+1;
st_sdr_next <= ROW_ACT;
end if;
end if;
when READ =>
phy_ctrl.re <= '1';
if burst_finished = '1' then
if cmd_we = '1' and cmd = SD_READ then
sdr_addr(col_addr_t'range) <= col_addr;
cmd_ack <= '1';
burst_load_en <= '1';
sdr_cmd_ctrl <= COMMAND(cmd);
phy_ctrl.utag_we <= '1';
else
cc_load_en <= '1';
cc_preset <= TIMING(SD_READ);
st_sdr_next <= ROW_ACT;
end if;
end if;
when WRITE_A => -- not implemented yet
cmd_ack <= '1';
st_sdr_next <= IDLE;
when READ_A => -- not implemented yet
cmd_ack <= '1';
st_sdr_next <= IDLE;
when BURST_STOP => -- not implemented yet
cmd_ack <= '1';
st_sdr_next <= IDLE;
when SELF_REF => -- not implemented yet
cmd_ack <= '1';
st_sdr_next <= IDLE;
when PRE_PWR_DOWN => -- not implemented yet
cmd_ack <= '1';
st_sdr_next <= IDLE;
when ACT_PWR_DOWN => -- not implemented yet
cmd_ack <= '1';
st_sdr_next <= IDLE;
when AUTO_REF =>
if cycle_finished = '1' then
st_sdr_next <= IDLE;
end if;
when others =>
st_sdr_next <= IDLE;
end case;
end process;
fsm_sdr_state_next:
process (rst, clk)
begin
if rst = '1' then
st_sdr <= PWR_DOWN;
elsif rising_edge(clk) then
st_sdr <= st_sdr_next;
end if;
end process;
------------------------------------------------------------------------------------------
cycle_counter:
process (rst, clk)
variable cycle_cnt : natural range 0 to 10;
begin
if rst = '1' then
cycle_cnt := 0;
cycle_finished <= '0';
elsif rising_edge(clk) then
cycle_finished <= '0';
if cc_load_en = '1' then
cycle_cnt := cc_preset;
elsif cycle_cnt /= 0 then
cycle_cnt := cycle_cnt - 1;
else
cycle_finished <= '1';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
burst_counter:
process (rst, clk)
variable burst_cnt : natural range 0 to 3;
begin
if rst = '1' then
burst_cnt := 0;
elsif rising_edge(clk) then
burst_finished <= '0';
if burst_load_en = '1' then
burst_cnt := burst_preset;
elsif burst_cnt /= 0 then
burst_cnt := burst_cnt - 1;
end if;
if burst_cnt = 0 then
burst_finished <= '1';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
end behaviour;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
-74
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@@ -1,74 +0,0 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: User SDRAM component adjustments
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
package sdram_config is
constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
constant DDR_COL_ADDR_WIDTH : positive := 9; --
constant LMR_REG_BASE : natural := 0;
constant LMR_REG_EXTENDED : natural := 1;
constant LMR_OP_NORMAL : natural := 0;
constant LMR_OP_RES_DLL : natural := 2;
constant LMR_BT_SEQ : natural := 0;
constant LMR_BT_ILVD : natural := 1;
constant LMR_BL2 : natural := 1;
constant LMR_BL4 : natural := 2;
constant LMR_BL8 : natural := 3;
constant LMR_CL2 : natural := 2;
constant LMR_CL3 : natural := 3;
constant LMR_CL2_5 : natural := 6;
-- DDR SDRAM Hardware defined constants
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
constant ENABLE_PRE_ALL : std_logic := '1';
constant ENABLE_AUTO_PRE : std_logic := '0';
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125; -- us
-- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : positive := 2; -- precharge command period
constant TRAS : positive := 4; -- active to precharge delay
constant TRFC : positive := 8; -- auto refresh command period
constant TMRD : positive := 2; -- load mode register command cylce time
constant TRCD : positive := 2; -- active to read or write delay !
constant TWR : positive := 2; -- write recovery time
constant PWR_UP_WAIT : natural := 1; -- µs
subtype user_tag_t is unsigned(3 downto 0);
----------------------------------------------------------------------------------------------
end sdram_config;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
-487
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@@ -1,487 +0,0 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: SDRAM main controller and user I/F
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.sdram_config.all;
use work.sdram_types.all;
use work.utils_pkg.all;
entity sdram_ctrl is
Generic
(
f_sysclk : natural := 100E6;
BL : natural := 2
);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
u_busy : out STD_LOGIC;
u_tag_in : in user_tag_t;
u_tag_out : out user_tag_t;
u_addr : in user_addr_t;
u_cmd : in user_cmd_t;
u_cmd_we : in STD_LOGIC;
col_addr : out col_addr_t;
sdr_cmd_busy : in STD_LOGIC;
sdr_cmd : out sdr_cmd_t;
sdr_cmd_we : out STD_LOGIC;
sdr_mode : out mode_word_t;
sdr_cke : out STD_LOGIC
);
end sdram_ctrl;
architecture behaviour of sdram_ctrl is
constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL);
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic;
signal cycle_cnt : natural range 0 to 255;
signal cc_preset : natural range 0 to 255;
signal cc_load_en : std_logic;
signal cycle_finished : std_logic;
signal seq_cnt : natural range 0 to 31;
signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic;
constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic;
signal addr_reg_load_en : std_logic;
signal u_tag_reg : user_tag_t;
signal bank_addr_reg : bank_addr_t;
signal row_addr_reg : row_addr_t;
signal col_addr_reg : col_addr_t;
signal u_bank_addr : bank_addr_t;
signal u_row_addr : row_addr_t;
signal u_col_addr : col_addr_t;
signal act_request : std_logic;
signal act_request_set : std_logic;
signal act_request_clr : std_logic;
type init_seq_rom_t is array (0 to 14) of init_seq_t;
constant init_seq_rom : init_seq_rom_t :=
(
(
cmd => SD_NOP,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_PRE,
mode_word => "000010000000000",
wait_cycle => 0
),
(
cmd => SD_NOP,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_LMR,
mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
wait_cycle => 0
),
(
cmd => SD_NOP,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_LMR,
mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
wait_cycle => 200
),
(
cmd => SD_NOP,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_PRE,
mode_word => "000010000000000",
wait_cycle => 0
),
(
cmd => SD_NOP,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_AR,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_NOP,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_AR,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_NOP,
mode_word => (others => '0'),
wait_cycle => 0
),
(
cmd => SD_LMR,
mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
wait_cycle => 200
),
(
cmd => SD_NOP,
mode_word => (others => '0'),
wait_cycle => 0
)
);
begin
u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
------------------------------------------------------------------------------------------
fsm_ctrl_state:
process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request)
begin
u_busy <= '1';
pwr_up_cnt_rst <= '0';
cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
cc_load_en <= '0';
sdr_cmd <= init_seq_rom(seq_cnt).cmd;
sdr_cmd_we <= '0';
sdr_mode <= bank_addr_reg & row_addr_reg;
col_addr <= col_addr_reg;
sdr_cke <= '1';
seq_cnt_en <= '0';
seq_rst_en <= '0';
addr_reg_load_en <= '0';
refresh_cnt_rst <= '0';
act_request_set <= '0';
act_request_clr <= '0';
u_tag_out <= u_tag_reg;
st_ctrl_next <= st_ctrl;
case st_ctrl is
when RESET =>
sdr_cke <= '0';
pwr_up_cnt_rst <= '1';
st_ctrl_next <= POWER_WAIT;
when POWER_WAIT =>
sdr_cke <= '0';
if pwr_up_finished = '1' then
seq_rst_en <= '1';
st_ctrl_next <= INIT;
end if;
when INIT =>
sdr_mode <= init_seq_rom(seq_cnt).mode_word;
sdr_cmd <= init_seq_rom(seq_cnt).cmd;
cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
if seq_cnt = init_seq_rom_t'high then
act_request_set <= '1';
refresh_cnt_rst <= '1';
st_ctrl_next <= USER_READY;
elsif sdr_cmd_busy = '0' then
cc_load_en <= '1';
sdr_cmd_we <= '1';
st_ctrl_next <= INIT_WAIT;
end if;
when INIT_WAIT =>
if sdr_cmd_busy = '0' and cycle_finished = '1' then
seq_cnt_en <= '1';
st_ctrl_next <= INIT;
end if;
when USER_READY =>
if sdr_cmd_busy = '0' then
if refresh_request = '1' then
sdr_mode(BIT_PRE_ALL) <= '1';
sdr_cmd_we <= '1';
sdr_cmd <= SD_PRE;
st_ctrl_next <= REFRESH;
else
u_busy <= '0';
if u_cmd_we = '1' then
case u_cmd is
when UCMD_NOP =>
sdr_cmd <= SD_NOP;
when UCMD_LMR =>
sdr_cmd <= SD_NOP;
when UCMD_WRITE =>
col_addr <= u_col_addr;
u_tag_out <= u_tag_in;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
addr_reg_load_en <= '1';
act_request_clr <= '1';
sdr_cmd <= SD_WRITE;
if (u_row_addr /= row_addr_reg) or act_request = '1' then
st_ctrl_next <= USER_WRITE_PRE;
elsif (u_bank_addr /= bank_addr_reg) then
if ENABLE_PRE_ALL = '1' then
st_ctrl_next <= USER_WRITE_ACT;
else
st_ctrl_next <= USER_WRITE_PRE;
end if;
elsif sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
else
st_ctrl_next <= USER_WRITE;
end if;
when UCMD_READ =>
col_addr <= u_col_addr;
u_tag_out <= u_tag_in;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
addr_reg_load_en <= '1';
act_request_clr <= '1';
sdr_cmd <= SD_READ;
if (u_row_addr /= row_addr_reg) or act_request = '1' then
st_ctrl_next <= USER_READ_PRE;
elsif (u_bank_addr /= bank_addr_reg) then
if ENABLE_PRE_ALL = '1' then
st_ctrl_next <= USER_READ_ACT;
else
st_ctrl_next <= USER_READ_PRE;
end if;
elsif sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
else
st_ctrl_next <= USER_READ;
end if;
when others => null;
end case;
end if;
end if;
end if;
when USER_WRITE_PRE =>
sdr_cmd <= SD_PRE;
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_WRITE_ACT;
end if;
when USER_WRITE_ACT =>
sdr_cmd <= SD_ACT;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_WRITE;
end if;
when USER_WRITE =>
sdr_cmd <= SD_WRITE;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READY;
end if;
when USER_READ_PRE =>
sdr_cmd <= SD_PRE;
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READ_ACT;
end if;
when USER_READ_ACT =>
sdr_cmd <= SD_ACT;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READ;
end if;
when USER_READ =>
sdr_cmd <= SD_READ;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READY;
end if;
when REFRESH =>
sdr_cmd <= SD_AR;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READY;
refresh_cnt_rst <= '1';
act_request_set <= '1';
end if;
when others =>
st_ctrl_next <= RESET;
end case;
end process;
fsm_ctrl_state_next:
process (rst, clk)
begin
if rst = '1' then
st_ctrl <= RESET;
elsif rising_edge(clk) then
st_ctrl <= st_ctrl_next;
end if;
end process;
------------------------------------------------------------------------------------------
act_request_register:
process (rst, clk)
begin
if rst = '1' then
act_request <= '1';
elsif rising_edge(clk) then
if act_request_set = '1' then
act_request <= '1';
elsif act_request_clr = '1' then
act_request <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
user_addr_register:
process (rst, clk)
begin
if rst = '1' then
bank_addr_reg <= (others => '0');
row_addr_reg <= (others => '0');
col_addr_reg <= (others => '0');
u_tag_reg <= (others => '0');
elsif rising_edge(clk) then
if addr_reg_load_en = '1' then
bank_addr_reg <= u_bank_addr;
row_addr_reg <= u_row_addr;
col_addr_reg <= u_col_addr;
u_tag_reg <= u_tag_in;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
power_up_counter:
process (rst, clk)
begin
if rst = '1' then
pwr_up_cnt <= 0;
pwr_up_finished <= '0';
elsif rising_edge(clk) then
pwr_up_finished <= '0';
if pwr_up_cnt_rst = '1' then
pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1;
else
if pwr_up_cnt /= 0 then
pwr_up_cnt <= pwr_up_cnt - 1;
else
pwr_up_finished <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
refresh_counter:
process (rst, clk)
begin
if rst = '1' then
refresh_cnt <= 0;
refresh_request <= '0';
elsif rising_edge(clk) then
refresh_request <= '0';
if refresh_cnt_rst = '1' then
refresh_cnt <= REFRESH_CLOCK_INTERVAL-1;
else
if refresh_cnt /= 0 then
refresh_cnt <= refresh_cnt - 1;
else
refresh_request <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
cycle_counter:
process (rst, clk)
begin
if rst = '1' then
cycle_cnt <= 0;
cycle_finished <= '0';
elsif rising_edge(clk) then
cycle_finished <= '0';
if cc_load_en = '1' then
cycle_cnt <= cc_preset;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
else
cycle_finished <= '1';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
seq_counter:
process (rst, clk)
begin
if rst = '1' then
seq_cnt <= 0;
elsif rising_edge(clk) then
if seq_rst_en = '1' then
seq_cnt <= 0;
elsif seq_cnt_en = '1' then
if seq_cnt /= init_seq_rom_t'high then
seq_cnt <= seq_cnt + 1;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
end behaviour;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
-283
View File
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
entity sdram_ctrl_frontend_wb is
Generic
(
BL : natural := 2;
f_sysclk : natural := 100E6;
fifo_depth : integer := 4
);
Port
(
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
CLK270_I : in STD_LOGIC;
CLK270VAR_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
-- SDRAM signals
sd_clk_p : out STD_LOGIC;
sd_clk_n : out STD_LOGIC;
sd_cke : out STD_LOGIC;
sd_cs_n : out STD_LOGIC;
sd_cas_n : out STD_LOGIC;
sd_ras_n : out STD_LOGIC;
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
);
end sdram_ctrl_frontend_wb;
architecture struct of sdram_ctrl_frontend_wb is
-- Number of user data words for simulation
signal u_addr : user_addr_t;
signal u_tag_in : user_tag_t;
signal u_tag_rd : user_tag_t;
signal u_tag_wr : user_tag_t;
signal u_cmd : user_cmd_t;
signal u_cmd_we : std_logic;
signal u_busy : std_logic;
signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0);
signal u_dm_rd_in : unsigned(SDR_DM_WIDTH-1 downto 0);
signal u_dm_rd_out : unsigned(SDR_DM_WIDTH-1 downto 0);
signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal u_data_vld : std_logic;
signal u_req_wr : std_logic;
signal rdy : std_logic;
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + 4;
signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_re : std_logic;
signal cat_fifo_we : std_logic;
signal cat_fifo_full : std_logic;
signal cat_fifo_empty : std_logic;
-- signal cat_fifo_almost_full : std_logic;
-- signal cat_fifo_almost_empty : std_logic;
signal write_fifo_din : unsigned(35 downto 0);
signal write_fifo_dout : unsigned(35 downto 0);
signal write_fifo_re : std_logic;
signal write_fifo_we : std_logic;
signal write_fifo_full : std_logic;
signal write_fifo_empty : std_logic;
-- signal write_fifo_almost_full : std_logic;
-- signal write_fifo_almost_empty : std_logic;
signal read_fifo_din : unsigned(35 downto 0);
signal read_fifo_dout : unsigned(35 downto 0);
signal read_fifo_re : std_logic;
signal read_fifo_we : std_logic;
signal read_fifo_full : std_logic;
signal read_fifo_empty : std_logic;
-- signal read_fifo_almost_full : std_logic;
-- signal read_fifo_almost_empty : std_logic;
alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 4);
alias dm_rd_fifo_in is cat_fifo_din(4-1 downto 0);
alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 4);
alias dm_rd_fifo_out is cat_fifo_dout(4-1 downto 0);
alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-4);
alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-4-1 downto 0);
alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-4);
alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-4-1 downto 0);
alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-4);
alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-4-1 downto 0);
alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-4);
alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-4-1 downto 0);
begin
-- Instantiate synchronous FIFO
inst_cat_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => fifo_depth,
data_width => CAT_FIFO_WIDTH
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => cat_fifo_we,
re => cat_fifo_re,
fifo_full => cat_fifo_full,
fifo_empty => cat_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => cat_fifo_din,
data_r => cat_fifo_dout
);
-- Instantiate synchronous FIFO
inst_write_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => fifo_depth,
data_width => 36
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => write_fifo_we,
re => write_fifo_re,
fifo_full => write_fifo_full,
fifo_empty => write_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => write_fifo_din,
data_r => write_fifo_dout
);
-- Instantiate synchronous FIFO
inst_read_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => fifo_depth,
data_width => 36
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => read_fifo_we,
re => read_fifo_re,
fifo_full => read_fifo_full,
fifo_empty => read_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => read_fifo_din,
data_r => read_fifo_dout
);
-- DDR SDRAM Controller Core
inst_sdram_ctrl : entity work.sdram_ctrl_top
Generic map
(
BL => BL,
f_sysclk => f_sysclk
)
Port map
(
sys_rst_in => RST_I,
sys_clk0_in => CLK_I,
sys_clk270_in => CLK270_I,
capture_clk270_in => CLK270VAR_I,
-- User interface
u_data_vld => u_data_vld,
u_data_req_w => u_req_wr,
u_data_req_r => open,
u_tag_in => u_tag_in,
u_tag_rd => u_tag_rd,
u_tag_wr => u_tag_wr,
u_busy => u_busy,
u_addr => u_addr,
u_cmd => u_cmd,
u_cmd_we => u_cmd_we,
u_data_wr => u_data_w,
u_data_rd => u_data_r,
u_dm_wr_in => u_dm_wr_in,
u_dm_rd_in => u_dm_rd_in,
u_dm_rd_out => u_dm_rd_out,
-- SDRAM signals
sd_clk_p => sd_clk_p,
sd_clk_n => sd_clk_n,
sd_cke => sd_cke,
sd_cs_n => sd_cs_n,
sd_cas_n => sd_cas_n,
sd_ras_n => sd_ras_n,
sd_we_n => sd_we_n,
sd_addr => sd_addr,
sd_ba => sd_ba,
sd_dm => sd_dm,
sd_dqs => sd_dqs,
sd_data => sd_data
);
------------------------------------------------------------------------------------------
SRDY_O <= rdy;
ACK_O <= not (read_fifo_empty);
DAT_O <= read_fifo_data_out;
rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
write_fifo_we <= STB_I and WE_I and rdy;
write_fifo_data_in <= DAT_I;
write_fifo_dm_in <= not SEL_I;
cat_fifo_we <= STB_I and rdy;
cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ;
addr_fifo_in <= ADDR_I(24 downto 2) & "0";
dm_rd_fifo_in <= not SEL_I;
tag_fifo_in <= (others=>'0');
u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
u_cmd <= cmd_fifo_out;
u_addr <= addr_fifo_out;
u_dm_rd_in <= dm_rd_fifo_out & dm_rd_fifo_out;
u_dm_wr_in <= write_fifo_dm_out & write_fifo_dm_out;
u_tag_in <= tag_fifo_out;
write_fifo_re <= u_req_wr and (not write_fifo_empty);
cat_fifo_re <= u_cmd_we;
u_data_w <= write_fifo_data_out & write_fifo_data_out;
read_fifo_re <= (not read_fifo_empty) and MRDY_I;
read_fifo_we <= u_data_vld;
read_fifo_data_in <= u_data_r(31 downto 0);
read_fifo_dm_in <= u_dm_rd_out(3 downto 0);
end architecture struct;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
-248
View File
@@ -1,248 +0,0 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Top-level put all together
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.sdram_config.all;
use work.sdram_types.all;
entity sdram_ctrl_top is
Generic
(
BL : natural := 2;
f_sysclk : natural := 100E6
);
Port
(
sys_rst_in : in STD_LOGIC;
sys_clk0_in : in STD_LOGIC;
sys_clk270_in : in STD_LOGIC;
capture_clk270_in : in STD_LOGIC;
-- User interface
u_data_vld : out STD_LOGIC;
u_data_req_w : out STD_LOGIC;
u_data_req_r : out STD_LOGIC;
u_busy : out STD_LOGIC;
u_tag_in : in user_tag_t;
u_tag_rd : out user_tag_t;
u_tag_wr : out user_tag_t;
u_addr : in user_addr_t;
u_cmd : in user_cmd_t;
u_cmd_we : in STD_LOGIC;
u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0);
u_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
u_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
u_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0);
u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0);
-- SDRAM signals
sd_clk_p : out STD_LOGIC;
sd_clk_n : out STD_LOGIC;
sd_cke : out STD_LOGIC;
sd_cs_n : out STD_LOGIC;
sd_cas_n : out STD_LOGIC;
sd_ras_n : out STD_LOGIC;
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
);
end sdram_ctrl_top;
architecture rtl of sdram_ctrl_top is
signal phy_ctrl : phy_ctrl_t;
signal u_tag : user_tag_t;
signal sd_cmd_in : sdr_cmd_t;
signal sd_cmd : sdr_cmd_t;
signal sd_cmd_we : std_logic;
signal cmd_ctrl : sdr_cmd_lines_t;
signal cke : std_logic;
signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
-- Clock generator
signal ctrl_rst : std_logic;
signal part_ctrl : part_ctrl_t;
-- SD command FIFO
constant CMD_FIFO_ADDR_WIDTH : positive := 2;
constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
signal cmd_fifo_re : std_logic;
signal cmd_fifo_we : std_logic;
signal cmd_fifo_full : std_logic;
signal cmd_fifo_empty : std_logic;
alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
begin
---------------------------------
part_ctrl.cmd <= cmd_ctrl;
part_ctrl.ba <= ba;
part_ctrl.addr <= addr;
part_ctrl.cke <= cke;
---------------------------------
sd_cmd_we <= not cmd_fifo_empty;
cmd_fifo_in <= to_unsigned(sd_cmd_in, 4);
sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out));
---------------------------------
inst_reset: entity work.reset
port map
(
clk => sys_clk0_in,
rst_in => sys_rst_in,
rst_out => ctrl_rst
);
-- Main controller
inst_sdram_ctrl : entity work.sdram_ctrl
Generic map
(
f_sysclk => 100E6,
BL => BL
)
Port map
(
rst => ctrl_rst,
clk => sys_clk0_in,
u_busy => u_busy,
u_tag_in => u_tag_in,
u_tag_out => tag_fifo_in,
u_cmd => u_cmd,
u_cmd_we => u_cmd_we,
u_addr => u_addr,
sdr_cmd_busy => cmd_fifo_full,
sdr_cmd => sd_cmd_in,
sdr_cmd_we => cmd_fifo_we,
col_addr => col_fifo_in,
sdr_mode => mode_fifo_in,
sdr_cke => cke
);
-- Instantiate synchronous FIFO
inst_sd_cmd_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => CMD_FIFO_ADDR_WIDTH,
data_width => CMD_FIFO_DATA_WIDTH,
almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1),
almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1)
)
PORT MAP
(
rst => ctrl_rst,
clk => sys_clk0_in,
we => cmd_fifo_we,
re => cmd_fifo_re,
fifo_full => cmd_fifo_full,
fifo_empty => cmd_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => cmd_fifo_din,
data_r => cmd_fifo_dout
);
-- DDR SDRAM command fsm
inst_sdram_cmd : entity work.sdram_cmd
Generic map
(
BL => BL
)
Port map
(
rst => ctrl_rst,
clk => sys_clk0_in,
u_tag_in => tag_fifo_out,
u_tag_out => u_tag,
phy_ctrl => phy_ctrl,
enable => cke,
cmd => sd_cmd,
cmd_we => sd_cmd_we,
cmd_ack => cmd_fifo_re,
sdr_cmd_ctrl => cmd_ctrl,
col_addr => col_fifo_out,
mode_word => mode_fifo_out,
sdr_ba => ba,
sdr_addr => addr
);
-- DDR phy
inst_ddr_phy : entity work.ddr_phy
Port map
(
sys_rst => ctrl_rst,
sys_clk0 => sys_clk0_in,
sys_clk270 => sys_clk270_in,
u_tag_in => u_tag,
u_tag_rd => u_tag_rd,
u_tag_wr => u_tag_wr,
read_clk => capture_clk270_in,
phy_ctrl => phy_ctrl,
part_ctrl => part_ctrl,
sdr_data_req_w => u_data_req_w,
sdr_data_req_r => u_data_req_r,
sdr_data_w => u_data_wr,
sdr_dm_wr_in => u_dm_wr_in,
sdr_dm_rd_in => u_dm_rd_in,
sdr_dm_rd_out => u_dm_rd_out,
sdr_data_r => u_data_rd,
sdr_data_vld => u_data_vld,
part_clk_p => sd_clk_p,
part_clk_n => sd_clk_n,
part_addr => sd_addr,
part_ba => sd_ba,
part_dm => sd_dm,
part_dqs => sd_dqs,
part_data => sd_data,
part_cs_n => sd_cs_n,
part_we_n => sd_we_n,
part_cas_n => sd_cas_n,
part_ras_n => sd_ras_n,
part_cke => sd_cke
);
end architecture rtl;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
-133
View File
@@ -1,133 +0,0 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Type definitions
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use work.sdram_config.all;
package sdram_types is
-----------------------------------------------------------------------------------------
-- Table of Timing Parameters as a function of operation
-- Derived constants from sdram_config
constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; --
constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; --
subtype user_cmd_t is unsigned(1 downto 0);
constant UCMD_NOP : user_cmd_t := "00";
constant UCMD_READ : user_cmd_t := "01";
constant UCMD_WRITE : user_cmd_t := "10";
constant UCMD_LMR : user_cmd_t := "11";
subtype sdr_cmd_t is natural range 0 to 9;
constant SD_DESELECT : sdr_cmd_t := 0;
constant SD_NOP : sdr_cmd_t := 1;
constant SD_LMR : sdr_cmd_t := 2;
constant SD_ACT : sdr_cmd_t := 3;
constant SD_READ : sdr_cmd_t := 4;
constant SD_WRITE : sdr_cmd_t := 5;
constant SD_PRE : sdr_cmd_t := 6;
constant SD_BST : sdr_cmd_t := 7;
constant SD_AR : sdr_cmd_t := 8;
constant SD_SR : sdr_cmd_t := 9;
type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
subtype col_addr_t is unsigned(8 downto 0);
subtype cycle_cnt_t is natural range 0 to 10;
type phy_ctrl_t is
record
drive_en : std_logic;
re : std_logic;
we : std_logic;
utag_we : std_logic;
end record phy_ctrl_t;
type sdr_cmd_lines_t is
record
cs_n : std_logic;
ras_n : std_logic;
cas_n : std_logic;
we_n : std_logic;
end record sdr_cmd_lines_t;
type part_ctrl_t is
record
cmd : sdr_cmd_lines_t;
ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
cke : std_logic;
end record part_ctrl_t;
type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
constant COMMAND : part_cmd_array_t :=
-- command cs_n ras_qn cas_qn we_qn
( SD_DESELECT => ( '1', '1', '1', '1'),
SD_NOP => ( '0', '1', '1', '1'),
SD_LMR => ( '0', '0', '0', '0'),
SD_ACT => ( '0', '0', '1', '1'),
SD_READ => ( '0', '1', '0', '1'),
SD_WRITE => ( '0', '1', '0', '0'),
SD_PRE => ( '0', '0', '1', '0'),
SD_BST => ( '0', '1', '1', '0'),
SD_AR => ( '0', '0', '0', '1'),
SD_SR => ( '0', '0', '0', '1')
);
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t :=
-- command cycle_cnt
( SD_DESELECT => ( 0 ),
SD_NOP => ( 0 ),
SD_LMR => ( TMRD-1 ),
SD_ACT => ( TRCD-1 ),
SD_READ => ( TCAS-1 ),
SD_WRITE => ( TWR-1 ),
SD_PRE => ( TRP-1 ),
SD_BST => ( 0 ),
SD_AR => ( TRFC-1 ),
SD_SR => ( TRFC-1 )
);
type init_seq_t is
record
cmd : sdr_cmd_t;
mode_word : mode_word_t;
wait_cycle : natural;
end record init_seq_t;
end sdram_types;
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
-505
View File
@@ -1,505 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
entity tb_sdram_ctrl_frontend_wb is
end;
architecture struct of tb_sdram_ctrl_frontend_wb is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
constant BURST_LEN : natural := 2;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal locked : std_logic;
signal error : std_logic;
signal clk_out : std_logic;
signal clk_fb : std_logic;
signal part_clk_p : std_logic;
signal part_clk_n : std_logic;
signal part_cke : std_logic;
signal part_cs_n : std_logic;
signal part_we_n : std_logic;
signal part_ras_n : std_logic;
signal part_cas_n : std_logic;
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal CLK_O : std_logic;
signal CLK270_O : std_logic;
signal CLK270VAR_O : std_logic;
signal RST_O : std_logic;
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal WE_O : std_logic := '0';
signal SEL_O : unsigned(3 downto 0) := (others => '1');
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0);
signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
sys1_phaseshift => 0,
frequency_hz => 100E6
)
PORT MAP
(
-- Clocks and Reset
rst => rst, -- external async reset, low active
clk_in => clk, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_fb, -- feedback clock
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sys1_clk270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys0_clk0_out => CLK_O, -- System clock #0, dcm#0 output 0°
sys0_clk270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
locked_out => locked, -- DCM locked status
error_out => error
);
clk_fb <= part_clk_p after 1 ns;
RST_O <= not locked;
-- DDR SDRAM Controller Core
sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => 100E6,
fifo_depth => 3
)
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
CLK270_I => CLK270_O,
CLK270VAR_I => CLK270VAR_O,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I,
-- SDRAM signals
sd_clk_p => part_clk_p,
sd_clk_n => part_clk_n,
sd_cke => part_cke,
sd_cs_n => part_cs_n,
sd_cas_n => part_cas_n,
sd_ras_n => part_ras_n,
sd_we_n => part_we_n,
sd_addr => part_addr,
sd_ba => part_ba,
sd_dm => part_dm,
sd_dqs => part_dqs,
sd_data => part_data
);
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_0 : entity work.mt46v16m16
port map
(
dq => std_logic_vector(part_data),
dqs => std_logic_vector(part_dqs),
addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba),
clk => part_clk_p,
clk_n => part_clk_n,
cke => part_cke,
cs_n => part_cs_n,
ras_n => part_ras_n,
cas_n => part_cas_n,
we_n => part_we_n,
dm => std_logic_vector(part_dm)
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
read_register:
process(CLK_O)
begin
if rising_edge(CLK_O) then
if dout_rst = '1' then
dout_cnt <= 0;
elsif ACK_I = '1' and WE_O = '0' then
dout_reg <= DAT_I;
dout_cnt <= dout_cnt + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
rst <= '0';
wait until RST_O = '0';
-- 8 single cycles
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"1234_0000";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
-- 8-word burst cycle
wait for 3*CLK_PERIOD;
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "0011";
ADDR_O <= X"0000_0080";
DAT_O <= X"DEADBEEF";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0080";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
-- 8-word burst cycle
wait for 3*CLK_PERIOD;
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
MRDY_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
MRDY_O <= '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 54;
CYC_O <= '0';
wait;
end process;
end architecture struct;