Compare commits
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
|
a67fbb643b |
Vendored
-100
@@ -1,100 +0,0 @@
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-----------------------------------------------------------------
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Changes in release 13
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-----------------------------------------------------------------
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- mips_biu.vhd: added asynchronous BUS-FIFOs to support different clocks for CPU and BUS
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- mips_dcache.vhd: improved instant-RAW stall behavior (faster execution)
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- uart_WB.vhd: added simulate_TX generic for plain TX output in simulation log
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-----------------------------------------------------------------
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Changes in release 12
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-----------------------------------------------------------------
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- reworked GCC-toolchain: Valid mips*-elf-binaries are now compiled and linked
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using a single mips*-elf-gcc command.
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To use: Copy $THIS_RELEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/,
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and see bsp/examples/Makefile gcc usage
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GCC-provided crt*-functions are now called without problems.
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In summary: The toolchain is now more compliant to the intentional use of GCC.
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- mips_biu.vhd: Addresses 0xA0000000..0xBFFFFFFF are now un-dcached for memory-mapped I/O,
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which is now compliant to literature.
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- gpio_wb.vhd: Timer hard-reset is now removed. This helps to keep current time in case of CPU hard-reset.
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- new bsp-example source: gunzip
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- updated drawing 'mips_jbus_timing.pdf'
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- added drawing 'memory_map.pdf'
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- moved COP0 from mips_pipeline.vhd to mips_top.vhd. Created new cop-interface for later COPz connection.
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- added I/D-cache info (size and linesize) to upper 16 bits of PrID-Register.
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Example of reading cache info is done in bsp/examples/testbench::PrintCPUinfo()
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- simplified instruction decoder in mips_instr.vhd. Now there are less warnings during synthesis.
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Removed idecode_rom.vhd from project as consequence.
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- added cop0 instructions to invalidate I-cache and D-Cache
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- added copz instructions lwcz and swcz
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- gpio_wb.vhd: added 32 bit timer with interrupt and auto reload
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- added debugger in libsys. New files are mipsdis.c/h and dbg.c/h
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- exception handlers can now be registered to any exception type
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- bugfix mips_pipeline/mips_cop: cop0 registers were not written during exception commit. Cop registers now behave like general registers.
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- added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian)
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- Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode
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- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of an MMU.
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- uart_wb.vhd: added interrupt enable
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- Interrupt pending flags (IP) are not anymore masked by Interrupt mask flags (IM) in H/W.
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Masking has to be done in S/W. H/W masking was removed because it isn't MIPS-compliant.
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- added NMI/RST pin (more MIPS compliant). Transition Asserting/Deasserting causes exception.
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Exception vector is reset (0xBFC00000). It's a soft-reset, which can help debugging. NMI/RST is not maskable.
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Using NMI/RST as reset is dangerous because periphery may not be reseted. Has to be done in S/W.
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Drawback of using NMI/RST: Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts), but I think you know that already.
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- Bootloader: Startup.S now invalidates I/D-Caches at boot.
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- uart_wb.vhd: fixed crappy tx-empty interrupt, Added Tx-IRQ acknowledge.
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- Bugfix in mips_pipeline: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.
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Newlib's MIPS-optimized version of memcpy() uses this for unaligned copy which revealed the bug.
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Symptom: Consecutive load instructions without nops using same target register (which is legal) like
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lw $1, 0(mem)
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lwl $1, 1(mem)
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or
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lwl $1, 0(mem)
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lwr $1, 1(mem)
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or similar, lead to incorrect result. Now it's fixed.
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- Bugfix mips_biu: instructions uncached LW => cached LW (with cache-miss) was buggy.
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Symptom:
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...
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1.: lw $a0, 32($s0) # Uncached load from memory mapped I/O
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2.: lw $a2, 4($v0) # Cached load and cache-miss.
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# $a0 receives same value as $a2.
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# CPU skips writing $a0 due to busy flag of D-Cache,
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# which is already active in the previous cycle
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...
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-----------------------------------------------------------------
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Changes in release 11
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-----------------------------------------------------------------
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- bugfix in mips_pipeline: pc_is_branch is now initialized at reset
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(fixes CPU unrecoverable state after reset)
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- reverted "optimization" in mips_dcache, which behaved buggy during exceptions
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- new example source: test_exception
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- minor changes in libsys
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- added async_port_timing in doc
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- examples/testbench: date set now really works
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-----------------------------------------------------------------
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Changes in release 10b
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-----------------------------------------------------------------
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- bugfix: fixed compiler bug (missing nop after lw) in bootloader,
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which caused exception during boot
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-----------------------------------------------------------------
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Changes in release 10a
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-----------------------------------------------------------------
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async_port_wb:
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- added byte enable for async_port
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bootloader.c
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- bugfix: fixed compiler bug (missing nop after lw)
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mips-core
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- bugfix: SEL_O lines are also asserted correctly during reads
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tools/romgen
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- TCL-Jtag now compatible with Chipscope 10.1
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mips_sys.c
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- use byte enable for sram and flash
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@@ -1,109 +0,0 @@
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-----------------------------------------------------------------
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J-MIPS Features
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-----------------------------------------------------------------
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- Synchrones Design
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- Portable Beschreibung in VHDL
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- Kompatible zur GNU Toolchain (Binutils, GCC, Newlib)
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- Befehle kompatibel mit MIPS-1 ISA (z.B. MIPS R3000)
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- 5-Stufige Pipeline und Hazardvermeidung durch Forwarding
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- 64Bit Multiplier (32Bit Operanden), 12 Cycles Latenz
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- 64Bit Divider (32Bit Operanden), 36 Cycles Latenz
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- Coprocessor 0 (COP0) für Exceptionhandling
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- Direct-mapped Instruction Cache mit variabler Größe, 8-words per Line
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- Direct-mapped Data Cache mit variabler Größe, 8-words per Line
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- J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen)
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- 1,2 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3)
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- Endianness umschaltbar zur Hard-reset Zeit
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- Unterschiedliche Frequenzen für CPU und BUS möglich
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-----------------------------------------------------------------
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Known Limitations
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-----------------------------------------------------------------
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- keine MMU
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- keine Unterstützung für Bus exceptions IBE und DBE
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- kein externes Coprocessor interface (COP1..3) für z.B. FPU
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- Befehle für Cop1..3 nicht implementiert:
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CFCz, CTCz, COPz, MFCz, MTCz, LWCz, SWCz
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Benutzung dieser Befehle führt zur Exception 'RI' (Reserved Instruction)
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- nicht alle COP0 Register/Bits vorhanden.
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-----------------------------------------------------------------
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Known Bugs
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-----------------------------------------------------------------
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- es gibt bestimmt noch nicht entdeckte Bugs
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-----------------------------------------------------------------
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Known Optimizations
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-----------------------------------------------------------------
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- Area: Multiplier als technologieabhängiges Primitive instanzieren
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- Area: Auf Divider verzichten
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- Area: Auf Multiplier verzichten
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- Area vs. Speed: Bei Hazards Pipeline-stall statt Forwarding.
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Durch Stalling geringerer Befehlsdurchsatz dafür weniger Logik.
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Weniger Logik bedeutet vielleicht wieder auch größere Taktfrequenz.
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-----------------------------------------------------------------
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Known ToDos
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-----------------------------------------------------------------
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- Unterstützung für Bus exceptions IBE und DBE
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- Externes COP1..3 interface, fehlende COP-Befehle implementieren
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- Optimierungen evaluieren und ggf. durchführen
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-----------------------------------------------------------------
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Synthesis results
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-----------------------------------------------------------------
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Virtex-4 XC4VSX35-10
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Config: 16Kbyte I/D-Cache
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Number of Slices 2387 15360 15%
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Number of Slice Flip Flops 1784 30720 5%
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Number of 4 input LUTs 3962 30720 12%
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Number of FIFO16/RAMB16s 18 192 9%
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Speed: 110MHz nach Synthesis
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-----------------------------------------------------------------
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Virtex-1 XCV1000-4
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Config: 4Kbyte I/D-Cache
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Number of Slices 2045 13824 16%
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Number of Slice Flip Flops 1783 27648 7%
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Number of 4 input LUTs 3923 27648 15%
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Number of FIFO16/RAMB16s 20 32 62%
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Speed: 30MHz nach Synthesis
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-----------------------------------------------------------------
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Performance bei 100MHz
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- GCC ohne Small-data section
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- MIPS Rev. 9
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-----------------------------------------------------------------
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I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12)
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1k 32 DMIPS 5 Mbit/s 345 kwhets/s 47/767 2,135s
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2k 51 DMIPS 5 Mbit/s 534 kwhets/s 38/561 2,134s
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4k 72 DMIPS 5 Mbit/s 623 kwhets/s 36/259 2,121s
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8k 98 DMIPS 10 Mbit/s 1149 kwhets/s 31/228 1,938s
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16k 115 DMIPS 17 Mbit/s 1234 kwhets/s 23/225 1,938s
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32k 115 DMIPS 17 Mbit/s 1285 kwhets/s 24/218 1,938s
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64k 115 DMIPS 17 Mbit/s 1285 kwhets/s 20/221 1,938s
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-----------------------------------------------------------------
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Performance bei 100MHz
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- GCC mit Small-data section
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- MIPS Rev. 9
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-----------------------------------------------------------------
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I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12)
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16k 117 DMIPS 17 Mbit/s 1236 kwhets/s 24/230 1,811s
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-----------------------------------------------------------------
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Performance bei 100MHz
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- GCC mit Small-data section
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- MIPS Rev. 10
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-----------------------------------------------------------------
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I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12)
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16k 120 DMIPS 17 Mbit/s 1242 kwhets/s 25/219 1,803s
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@@ -1,46 +0,0 @@
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# ---------------------------------------------------------------
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||||
# 1. Binutils bauen und installieren
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||||
# ---------------------------------------------------------------
|
||||
> tar -xzf binutils-2.19.tar.gz
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||||
> mkdir binutils-2.19_build
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||||
> cd binutils-2.19_build
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||||
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||||
> ../binutils-2.19/configure --target=mipsel-elf --prefix=/usr/local
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||||
> make
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||||
> make install
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||||
|
||||
# ---------------------------------------------------------------
|
||||
# 2. GCC bootstrapping
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||||
# ---------------------------------------------------------------
|
||||
> tar -xzf gcc-4.3.2.tar.gz
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||||
> mkdir gcc-4.3.2_build
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||||
> cd gcc-4.3.2_build
|
||||
> ../gcc-4.3.2/configure --target=mipsel-elf --prefix=/usr/local --enable-languages="c,c++" --without-headers --with-newlib --with-float=soft --disable-multilib
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||||
> CFLAGS_FOR_TARGET="-mno-gpopt" make all-gcc
|
||||
> make info-gcc
|
||||
> make install-gcc
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
# 3. Newlib bauen und installieren
|
||||
# ---------------------------------------------------------------
|
||||
> tar -xzf newlib-1.16.0.tar.gz
|
||||
! Bug in newlib-1.16.0/newlib/libc/machine/mips/strlen.c.
|
||||
Newlib von Hand patchen (32-bit MIPS targets):
|
||||
"lbu $3,0($4)\n"
|
||||
"nop\n" <= nop einfügen
|
||||
"bnez $3,1b\n"
|
||||
|
||||
> mkdir newlib-1.16.0_build
|
||||
> cd newlib-1.16.0_build
|
||||
> ../newlib-1.16.0/configure --target=mipsel-elf --prefix=/usr/local --with-float=soft --disable-multilib
|
||||
> TARGET_CFLAGS="-mno-gpopt" make all
|
||||
> make install
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
# 4. GCC bauen und installieren
|
||||
# ---------------------------------------------------------------
|
||||
> cd gcc-4.3.2_build
|
||||
> ../gcc-4.3.2/configure --target=mipsel-elf --prefix=/usr/local --enable-languages="c,c++" --disable-shared --with-newlib --with-float=soft --disable-multilib
|
||||
> CFLAGS_FOR_TARGET="-mno-gpopt" make all
|
||||
> make info
|
||||
> make install
|
||||
@@ -1,151 +0,0 @@
|
||||
#!/bin/sh
|
||||
TARGET=mipsel-elf
|
||||
PREFIX=/usr/local
|
||||
|
||||
SRC_BINUTILS=binutils-2.19
|
||||
SRC_GCC=gcc-4.3.3
|
||||
SRC_NEWLIB=newlib-1.16.0
|
||||
SRC_GMP=gmp-4.2.4
|
||||
SRC_MPFR=mpfr-2.4.0
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
# 1. Binutils bauen und installieren
|
||||
# ---------------------------------------------------------------
|
||||
if [ ! -e $SRC_BINUTILS.tar.bz2 ]; then
|
||||
echo Downloading $SRC_BINUTILS
|
||||
wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/binutils/$SRC_BINUTILS.tar.bz2 || exit 1
|
||||
else
|
||||
echo Skipped downloading $SRC_BINUTILS
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_BINUTILS ]; then
|
||||
echo Unpacking $SRC_BINUTILS
|
||||
tar -xjf $SRC_BINUTILS.tar.bz2 || exit 1
|
||||
else
|
||||
echo Skipped unpacking $SRC_BINUTILS
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_BINUTILS-build ]; then
|
||||
echo Building $SRC_BINUTILS
|
||||
mkdir -p $SRC_BINUTILS-build
|
||||
cd $SRC_BINUTILS-build
|
||||
../$SRC_BINUTILS/configure --target=$TARGET --prefix=$PREFIX || exit 1
|
||||
make || exit 1
|
||||
make install || exit 1
|
||||
cd ..
|
||||
else
|
||||
echo $SRC_BINUTILS is already built.
|
||||
fi
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
# 2. GMP bauen und installieren
|
||||
# ---------------------------------------------------------------
|
||||
if [ ! -e $SRC_GMP.tar.bz2 ]; then
|
||||
echo Downloading $SRC_GMP
|
||||
wget http://ftp.sunet.se/pub/gnu/gmp/$SRC_GMP.tar.bz2 || exit 1
|
||||
else
|
||||
echo Skipped downloading $SRC_GMP
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_GMP ]; then
|
||||
echo Unpacking $SRC_GMP
|
||||
tar -xjf $SRC_GMP.tar.bz2 || exit 1
|
||||
else
|
||||
echo Skipped unpacking $SRC_GMP
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_GMP-build ]; then
|
||||
echo Building $SRC_GMP
|
||||
mkdir -p $SRC_GMP-build
|
||||
cd $SRC_GMP-build
|
||||
../$SRC_GMP/configure --prefix=$PREFIX || exit 1
|
||||
make || exit 1
|
||||
make check || exit 1
|
||||
make install || exit 1
|
||||
cd ..
|
||||
else
|
||||
echo $SRC_GMP is already built.
|
||||
fi
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
# 3. MPFR bauen und installieren
|
||||
# ---------------------------------------------------------------
|
||||
if [ ! -e $SRC_MPFR.tar.bz2 ]; then
|
||||
echo Downloading $SRC_MPFR
|
||||
wget http://www.mpfr.org/mpfr-current/$SRC_MPFR.tar.bz2 || exit 1
|
||||
else
|
||||
echo Skipped downloading $SRC_MPFR
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_MPFR ]; then
|
||||
echo Unpacking $SRC_MPFR
|
||||
tar -xjf $SRC_MPFR.tar.bz2 || exit 1
|
||||
else
|
||||
echo Skipped unpacking $SRC_MPFR
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_MPFR-build ]; then
|
||||
echo Building $SRC_MPFR
|
||||
mkdir -p $SRC_MPFR-build
|
||||
cd $SRC_MPFR-build
|
||||
../$SRC_MPFR/configure --prefix=$PREFIX || exit 1
|
||||
make || exit 1
|
||||
make check || exit 1
|
||||
make install || exit 1
|
||||
cd ..
|
||||
else
|
||||
echo $SRC_MPFR is already built.
|
||||
fi
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
# 4. GCC & newlib bauen und installieren
|
||||
# ---------------------------------------------------------------
|
||||
if [ ! -e $SRC_NEWLIB.tar.gz ]; then
|
||||
echo Downloading $SRC_NEWLIB
|
||||
wget ftp://sources.redhat.com/pub/newlib/$SRC_NEWLIB.tar.gz || exit 1
|
||||
else
|
||||
echo Skipped downloading $SRC_NEWLIB
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_NEWLIB ]; then
|
||||
echo Unpacking $SRC_NEWLIB
|
||||
tar -xzf $SRC_NEWLIB.tar.gz || exit 1
|
||||
if [ -e $SRC_NEWLIB-jens.patch ]; then
|
||||
echo Patching $SRC_NEWLIB
|
||||
patch -p0 < $SRC_NEWLIB-jens.patch || exit 1
|
||||
fi
|
||||
else
|
||||
echo Skipped unpacking $SRC_NEWLIB
|
||||
fi
|
||||
|
||||
if [ ! -e $SRC_GCC.tar.bz2 ]; then
|
||||
echo Downloading $SRC_GCC
|
||||
wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/gcc/$SRC_GCC/$SRC_GCC.tar.bz2 || exit 1
|
||||
else
|
||||
echo Skipped downloading $SRC_GCC
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_GCC ]; then
|
||||
echo Unpacking $SRC_GCC
|
||||
tar -xjf $SRC_GCC.tar.bz2 || exit 1
|
||||
cd ./$SRC_GCC
|
||||
ln -sf ../$SRC_NEWLIB/newlib/ .
|
||||
cd ..
|
||||
else
|
||||
echo Skipped unpacking $SRC_GCC
|
||||
fi
|
||||
|
||||
if [ ! -e ./$SRC_GCC-build ]; then
|
||||
echo Building $SRC_GCC
|
||||
mkdir -p $SRC_GCC-build
|
||||
cd $SRC_GCC-build
|
||||
../$SRC_GCC/configure --target=$TARGET --prefix=$PREFIX --with-float=soft --with-newlib --verbose --enable-languages="c,c++" || exit 1
|
||||
LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$PREFIX/lib make all || exit 1
|
||||
make info || exit 1
|
||||
make install || exit 1
|
||||
cd ..
|
||||
echo $PREFIX/lib >/etc/ld.so.conf.d/local.conf
|
||||
ldconfig
|
||||
else
|
||||
echo $SRC_GCC is already built.
|
||||
fi
|
||||
@@ -1,11 +0,0 @@
|
||||
diff -Naur newlib-1.16.0/newlib/libc/machine/mips/strlen.c newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c
|
||||
--- newlib-1.16.0/newlib/libc/machine/mips/strlen.c 2002-03-14 03:41:43.000000000 +0100
|
||||
+++ newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c 2009-02-14 15:52:58.000000000 +0100
|
||||
@@ -60,6 +60,7 @@
|
||||
" addiu $2,$4,1\n"
|
||||
"\n"
|
||||
"1: lbu $3,0($4)\n"
|
||||
+ " nop\n"
|
||||
" bnez $3,1b\n"
|
||||
" addiu $4,$4,1\n"
|
||||
"\n"
|
||||
@@ -1,11 +0,0 @@
|
||||
diff -Naur newlib-1.17.0/newlib/libc/machine/mips/strlen.c newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c
|
||||
--- newlib-1.17.0/newlib/libc/machine/mips/strlen.c 2002-03-14 03:41:43.000000000 +0100
|
||||
+++ newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c 2009-02-14 15:45:19.000000000 +0100
|
||||
@@ -60,6 +60,7 @@
|
||||
" addiu $2,$4,1\n"
|
||||
"\n"
|
||||
"1: lbu $3,0($4)\n"
|
||||
+ " nop\n"
|
||||
" bnez $3,1b\n"
|
||||
" addiu $4,$4,1\n"
|
||||
"\n"
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_muldiv.vhd"
|
||||
vcom -explicit -93 "../src/tb_mips_muldiv.vhd"
|
||||
vsim -t 1ps -lib work tb_mips_muldiv
|
||||
do {tb_mips_muldiv.wdo}
|
||||
view wave
|
||||
|
||||
view structure
|
||||
view signals
|
||||
run 8ms
|
||||
@@ -0,0 +1,78 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/rst
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/clk
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/start
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/busy
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/s_un
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/md_result
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/check
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
|
||||
add wave -noupdate -divider FSM
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
|
||||
add wave -noupdate -divider {Multiplier internals}
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_muldiv/uut/pprod
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyi
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_res
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_res
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_reg
|
||||
add wave -noupdate -divider {Divider internals}
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/busy
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/s_un
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_start
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_add_cyi
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op2
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_res
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_q
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_qbit
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_en
|
||||
add wave -noupdate -divider FSM
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt
|
||||
add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
|
||||
add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {7735999838 ps} 0} {{Cursor 2} {512321 ps} 0}
|
||||
configure wave -namecolwidth 149
|
||||
configure wave -valuecolwidth 171
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {8400 us}
|
||||
@@ -1,42 +0,0 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../src/dpram_2w2r.vhd"
|
||||
vcom -explicit -93 "../src/dpram_1w1r.vhd"
|
||||
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/fifo_async_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/fifo_async.vhd"
|
||||
vcom -explicit -93 "../src/bbfifo_16x8.vhd"
|
||||
vcom -explicit -93 "../src/kcuart_rx.vhd"
|
||||
vcom -explicit -93 "../src/kcuart_tx.vhd"
|
||||
vcom -explicit -93 "../src/uart_rx.vhd"
|
||||
vcom -explicit -93 "../src/uart_tx.vhd"
|
||||
vcom -explicit -93 "../src/uart_wb.vhd"
|
||||
vcom -explicit -93 "../src/gpio_wb.vhd"
|
||||
vcom -explicit -93 "../src/async_types.vhd"
|
||||
vcom -explicit -93 "../src/async_port_wb.vhd"
|
||||
vcom -explicit -93 "../src/async_defs.vhd"
|
||||
vcom -explicit -93 "../src/bootloader.ROM.vhd"
|
||||
vcom -explicit -93 "../src/rom_wb.vhd"
|
||||
vcom -explicit -93 "../src/mips_types.vhd"
|
||||
vcom -explicit -93 "../src/mips_instr.vhd"
|
||||
vcom -explicit -93 "../src/mips_reg.vhd"
|
||||
vcom -explicit -93 "../src/mips_shifter.vhd"
|
||||
vcom -explicit -93 "../src/mips_alu.vhd"
|
||||
vcom -explicit -93 "../src/mips_muldiv.vhd"
|
||||
vcom -explicit -93 "../src/mips_cop.vhd"
|
||||
vcom -explicit -93 "../src/mips_icache.vhd"
|
||||
vcom -explicit -93 "../src/mips_dcache.vhd"
|
||||
vcom -explicit -93 "../src/mips_biu.vhd"
|
||||
vcom -explicit -93 "../src/mips_bcu.vhd"
|
||||
vcom -explicit -93 "../src/mips_pipeline.vhd"
|
||||
vcom -explicit -93 "../src/mips_top.vhd"
|
||||
vcom -explicit -93 "../src/mips_sys.vhd"
|
||||
vcom -explicit -93 "../src/tb_mips_sys.vhd"
|
||||
vsim -t 1ps -lib work tb_mips_sys
|
||||
do {tb_mips_sys.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 3000us
|
||||
@@ -1,45 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {MIPS top}
|
||||
add wave -noupdate -format Literal /tb_mips_sys/debug
|
||||
add wave -noupdate -format Logic /tb_mips_sys/rst
|
||||
add wave -noupdate -format Logic /tb_mips_sys/clk
|
||||
add wave -noupdate -divider Flash
|
||||
add wave -noupdate -format Logic /tb_mips_sys/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/flash_cs_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/flash_oe_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/flash_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/flash_d
|
||||
add wave -noupdate -divider SRAM
|
||||
add wave -noupdate -format Logic /tb_mips_sys/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sram_cs_n
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sram_wr_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sram_oe_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sram_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sram_d
|
||||
add wave -noupdate -divider GPIO
|
||||
add wave -noupdate -format Logic /tb_mips_sys/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpo0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpo1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpi0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpi1
|
||||
add wave -noupdate -divider UART
|
||||
add wave -noupdate -format Logic /tb_mips_sys/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/tx
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1165707237 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {3150 us}
|
||||
@@ -0,0 +1,57 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
|
||||
# RAMS
|
||||
vcom -explicit -93 "../../../misc/dpram_2w2r.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
|
||||
|
||||
# FIFOS
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd"
|
||||
|
||||
# UART
|
||||
vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
|
||||
vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
|
||||
vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
|
||||
vcom -explicit -93 "../../../uart/uart_rx.vhd"
|
||||
vcom -explicit -93 "../../../uart/uart_tx.vhd"
|
||||
vcom -explicit -93 "../../../uart/uart_wb.vhd"
|
||||
|
||||
# GPIO
|
||||
vcom -explicit -93 "../../../misc/gpio_wb.vhd"
|
||||
|
||||
# Async port
|
||||
vcom -explicit -93 "../../../misc/async_types.vhd"
|
||||
vcom -explicit -93 "../../../misc/async_port_wb.vhd"
|
||||
vcom -explicit -93 "../src/async_defs.vhd"
|
||||
|
||||
# ROM
|
||||
vcom -explicit -93 "../src/bootloader.ROM.vhd"
|
||||
vcom -explicit -93 "../../../misc/rom_wb.vhd"
|
||||
|
||||
# MIPS
|
||||
vcom -explicit -93 "../src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_instr.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_reg.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_shifter.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_alu.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_muldiv.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_cop.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_icache.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_dcache.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_biu.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_bcu.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
|
||||
vcom -explicit -93 "../src/core/mips_top.vhd"
|
||||
|
||||
vcom -explicit -93 "../src/tb_mips_top.vhd"
|
||||
vsim -t 1ps -lib work tb_mips_top
|
||||
do {tb_mips_top.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1600us
|
||||
@@ -0,0 +1,67 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {TOP interface}
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal /tb_mips_top/debug
|
||||
add wave -noupdate -format Logic /tb_mips_top/stb_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/ack_i
|
||||
add wave -noupdate -format Logic /tb_mips_top/srdy_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/we_o
|
||||
add wave -noupdate -format Literal /tb_mips_top/sel_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/cyc_o
|
||||
add wave -noupdate -format Logic /tb_mips_top/mrdy_o
|
||||
add wave -noupdate -format Literal /tb_mips_top/int
|
||||
add wave -noupdate -divider {External components}
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Logic /tb_mips_top/rx
|
||||
add wave -noupdate -format Logic /tb_mips_top/tx
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal /tb_mips_top/mem_area
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
|
||||
add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
|
||||
add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
|
||||
add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
|
||||
add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
|
||||
add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
|
||||
add wave -noupdate -divider ALU
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
|
||||
add wave -noupdate -divider PC
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
|
||||
add wave -noupdate -divider PC
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
|
||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1199854590 ps} 0}
|
||||
configure wave -namecolwidth 188
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {1260 us}
|
||||
@@ -31,38 +31,30 @@ package async_defs is
|
||||
|
||||
constant ts_flash : async_timespec_t :=
|
||||
(
|
||||
T_leadin => 00.0,
|
||||
T_pulse_rd => 120.0,
|
||||
T_pulse_wr => 70.0,
|
||||
T_leadout => 00.0,
|
||||
T_release => 40.0,
|
||||
T_pulse_rst => 80.0,
|
||||
T_pulse_page_rd => 30.0,
|
||||
can_page_rd => true,
|
||||
nbits_page_rd => 4,
|
||||
pol_cs => '0',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_be => '0',
|
||||
pol_rst => '0'
|
||||
ncyc_access => 1,
|
||||
ncyc_pulse_rd => 12,
|
||||
ncyc_pulse_wr => 7,
|
||||
ncyc_cs_hold => 1,
|
||||
ncyc_release => 1,
|
||||
ncyc_pulse_rst => 8,
|
||||
pol_cs => '0',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
constant ts_sram : async_timespec_t :=
|
||||
(
|
||||
T_leadin => 00.0,
|
||||
T_pulse_rd => 10.0,
|
||||
T_pulse_wr => 10.0,
|
||||
T_leadout => 00.0,
|
||||
T_release => 00.0,
|
||||
T_pulse_rst => 80.0,
|
||||
T_pulse_page_rd => 20.0,
|
||||
can_page_rd => false,
|
||||
nbits_page_rd => 5,
|
||||
pol_cs => '0',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_be => '0',
|
||||
pol_rst => '0'
|
||||
ncyc_access => 1,
|
||||
ncyc_pulse_rd => 12,
|
||||
ncyc_pulse_wr => 7,
|
||||
ncyc_cs_hold => 1,
|
||||
ncyc_release => 1,
|
||||
ncyc_pulse_rst => 8,
|
||||
pol_cs => '0',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
end async_defs;
|
||||
|
||||
+1444
-1444
File diff suppressed because it is too large
Load Diff
@@ -1,12 +0,0 @@
|
||||
VHDL/lib/CPUs/MIPS/src/core/dcache.vhd
|
||||
VHDL/lib/CPUs/MIPS/src/core/mips_dcache.vhd
|
||||
VHDL/lib/CPUs/MIPS/src/core/icache.vhd
|
||||
VHDL/lib/CPUs/MIPS/src/core/mips_icache.vhd
|
||||
VHDL/lib/CPUs/MIPS/src/core/mips_biu.vhd
|
||||
|
||||
VHDL/lib/CPUs/MIPS/src/core/mips_bui.vhd
|
||||
VHDL/lib/CPUs/MIPS/src/core/mips_biu.vhd
|
||||
VHDL/lib/CPUs/MIPS/src/core/mips_dcache.vhd
|
||||
|
||||
VHDL/lib/CPUs/MIPS/src/core/mips_icache.vhd
|
||||
|
||||
+190
-290
@@ -1,29 +1,7 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
@@ -40,12 +18,11 @@ ENTITY dcache IS
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
STB_O : out STD_LOGIC;
|
||||
CYC_O : out STD_LOGIC;
|
||||
ctrl : in cache_ctrl_t;
|
||||
en : in STD_LOGIC;
|
||||
cpu_en : in STD_LOGIC;
|
||||
cpu_we : in STD_LOGIC;
|
||||
cpu_be : in unsigned(3 downto 0);
|
||||
@@ -100,15 +77,25 @@ COMPONENT dpram_2w2r is
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant addr_width : natural := 32;
|
||||
function lg2(x : natural) return natural is
|
||||
begin
|
||||
return natural(ceil(log2(real(x))));
|
||||
end lg2;
|
||||
|
||||
function po2(x : natural) return natural is
|
||||
begin
|
||||
|
||||
return 2**lg2(x);
|
||||
end po2;
|
||||
|
||||
constant word_index_width : natural := lg2(line_size);
|
||||
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
|
||||
constant tag_width : natural := addr_width - word_index_width - cache_index_width - 2;
|
||||
constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
|
||||
constant tag_parity_width : natural := 3;
|
||||
constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width;
|
||||
constant tag_ram_addr_width : natural := cache_index_width;
|
||||
constant tram_data_width : natural := 1 + tag_parity_width + tag_width;
|
||||
constant tram_addr_width : natural := cache_index_width;
|
||||
|
||||
subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0);
|
||||
subtype tram_data_t is unsigned (tram_data_width-1 downto 0);
|
||||
|
||||
type dcache_entry_t is record
|
||||
valid : std_logic;
|
||||
@@ -116,7 +103,11 @@ END COMPONENT;
|
||||
tag : unsigned(tag_width-1 downto 0);
|
||||
end record;
|
||||
|
||||
function to_dcache_entry(x : tag_ram_data_t) return dcache_entry_t is
|
||||
alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
|
||||
alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
function to_dcache_entry(x : tram_data_t) return dcache_entry_t is
|
||||
variable result : dcache_entry_t;
|
||||
begin
|
||||
result.valid := x(0);
|
||||
@@ -126,141 +117,106 @@ END COMPONENT;
|
||||
return result;
|
||||
end to_dcache_entry;
|
||||
|
||||
function to_tag_ram_data(x : dcache_entry_t) return tag_ram_data_t is
|
||||
variable result : tag_ram_data_t;
|
||||
function to_tram_data(x : dcache_entry_t) return tram_data_t is
|
||||
variable result : tram_data_t;
|
||||
begin
|
||||
result(0) := x.valid;
|
||||
result(3 downto 1) := x.tv_p;
|
||||
result(tag_width+3 downto 4) := x.tag;
|
||||
|
||||
return result;
|
||||
end to_tag_ram_data;
|
||||
end to_tram_data;
|
||||
|
||||
type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache);
|
||||
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
|
||||
signal s, sn : cache_state_t;
|
||||
|
||||
signal cache_req : std_logic;
|
||||
signal cache_ack : std_logic;
|
||||
signal cache_busy : std_logic;
|
||||
signal cache_hit : std_logic;
|
||||
signal tag_match : std_logic;
|
||||
signal cache_hit_inv : std_logic;
|
||||
signal tag_match_inv : std_logic;
|
||||
|
||||
signal request_addr : unsigned(addr_width-1 downto 0);
|
||||
signal fill_addr : unsigned(addr_width-1 downto 0);
|
||||
|
||||
signal cache_index_inv : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_inv : unsigned(tag_width-1 downto 0);
|
||||
signal tag_reg_inv : unsigned(tag_width-1 downto 0);
|
||||
signal word_index_reg : unsigned(word_index_width-1 downto 0);
|
||||
signal cache_index_reg : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_index_reg : unsigned(tag_width-1 downto 0);
|
||||
|
||||
signal cache_entry_in : dcache_entry_t;
|
||||
signal cache_entry_out : dcache_entry_t;
|
||||
signal cache_entry_out_inv : dcache_entry_t;
|
||||
signal cpu_data_ram_addr : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal cpu_data_ram_dout : word_t;
|
||||
signal cpu_dram_addr : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal cpu_dram_dout : word_t;
|
||||
signal cpu_dram_din : word_t;
|
||||
signal cpu_data_reg : word_t;
|
||||
signal cpu_be_reg : unsigned(3 downto 0);
|
||||
signal cpu_we_reg : std_logic;
|
||||
signal ctrl_data_ram_addr : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal ctrl_data_ram_we : unsigned(3 downto 0);
|
||||
signal cpu_data_ram_we : unsigned(3 downto 0);
|
||||
signal ctrl_dram_en : std_logic;
|
||||
signal ctrl_dram_addr : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal ctrl_dram_din : word_t;
|
||||
signal ctrl_dram_we : unsigned(3 downto 0);
|
||||
signal cpu_dram_we : unsigned(3 downto 0);
|
||||
signal cpu_dram_en : std_logic;
|
||||
signal cpu_en2 : std_logic;
|
||||
signal cpu_we2 : std_logic;
|
||||
|
||||
signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_dout : tag_ram_data_t;
|
||||
signal tag_ram_dout_inv : tag_ram_data_t;
|
||||
signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_din : tag_ram_data_t;
|
||||
signal tag_ram_we : std_logic;
|
||||
signal tram_addr_rd : unsigned(cache_index_width-1 downto 0);
|
||||
signal tram_dout : tram_data_t;
|
||||
signal tram_addr_wr : unsigned(cache_index_width-1 downto 0);
|
||||
signal tram_din : tram_data_t;
|
||||
signal tram_re : std_logic;
|
||||
signal tram_we : std_logic;
|
||||
|
||||
signal fill_count : natural range 0 to 2**word_index_width-1;
|
||||
signal fill_count_en : std_logic;
|
||||
signal fill_count_rdy : std_logic;
|
||||
signal flush_count : natural range 0 to 2**cache_index_width-1;
|
||||
signal flush_count_rst : std_logic;
|
||||
signal flush_count_en : std_logic;
|
||||
signal flush_count_rdy : std_logic;
|
||||
signal request_count : natural range 0 to 2**word_index_width-1;
|
||||
signal request_count_en : std_logic;
|
||||
signal request_count_rdy : std_logic;
|
||||
signal was_miss : std_logic;
|
||||
signal invalidate_all : std_logic;
|
||||
signal invalidate_ack : std_logic;
|
||||
signal invalidate_en : std_logic;
|
||||
signal invalidate_req : std_logic;
|
||||
signal cpu_hit_we : std_logic;
|
||||
signal instant_raw : std_logic;
|
||||
signal hit_cache_index : unsigned(cache_index_width-1 downto 0);
|
||||
|
||||
alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
|
||||
alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias fill_word_index is fill_addr(word_index_width+1 downto 2);
|
||||
alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias req_word_index is request_addr(word_index_width+1 downto 2);
|
||||
alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
signal ram_index_count : natural range 0 to 2**word_index_width-1;
|
||||
signal ram_index_count_rst : std_logic;
|
||||
signal cache_index_count : natural range 0 to 2**cache_index_width-1;
|
||||
signal cache_index_count_en : std_logic;
|
||||
signal mem_index_count : natural range 0 to 2**word_index_width-1;
|
||||
signal mem_index_count_en : std_logic;
|
||||
signal mem_index_count_rst : std_logic;
|
||||
signal cpu_reg_en : std_logic;
|
||||
signal was_miss : std_logic;
|
||||
signal data_write : std_logic;
|
||||
signal cpu_hit_we : std_logic;
|
||||
signal instant_raw : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
cpu_hit_we <= cpu_we2 and cache_hit;
|
||||
|
||||
fill_address_register:
|
||||
cpu_index_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if fill_count_en = '1' then
|
||||
if ACK_I = '1' then
|
||||
fill_word_index <= fill_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
fill_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
if RST_I = '1' then
|
||||
cache_index_reg <= (others => '0');
|
||||
tag_index_reg <= (others => '0');
|
||||
elsif cpu_reg_en = '1' and en = '1' and instant_raw = '0' then
|
||||
word_index_reg <= cpu_word_index;
|
||||
cache_index_reg <= cpu_cache_index;
|
||||
tag_index_reg <= cpu_tag;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '1'then
|
||||
if SRDY_I = '1' then
|
||||
req_word_index <= req_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
request_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_request_register:
|
||||
cpu_data_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
cpu_we_reg <= '0';
|
||||
cache_req <= '0';
|
||||
elsif cpu_en = '1' then
|
||||
if cache_busy = '0' then
|
||||
cpu_we2 <= cpu_we;
|
||||
cache_req <= '1';
|
||||
cpu_data_reg <= cpu_din;
|
||||
cpu_be_reg <= cpu_be;
|
||||
cpu_we_reg <= cpu_we;
|
||||
if cpu_we = '1' then
|
||||
hit_cache_index <= cpu_cache_index;
|
||||
end if;
|
||||
end if;
|
||||
elsif cache_ack = '1' then
|
||||
cache_req <= '0';
|
||||
cpu_we2 <= '0';
|
||||
elsif cpu_reg_en = '1' and en = '1' then
|
||||
cpu_data_reg <= cpu_din;
|
||||
cpu_be_reg <= cpu_be;
|
||||
cpu_we_reg <= cpu_we;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_was_wr_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
cpu_en2 <= '0';
|
||||
cpu_we2 <= '0';
|
||||
if cpu_en = '1' and en = '1' then
|
||||
cpu_we2 <= cpu_we;
|
||||
cpu_en2 <= '1';
|
||||
cpu_dram_din <= cpu_din;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
@@ -269,33 +225,25 @@ instant_raw_logic:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
instant_raw <= '0';
|
||||
if cpu_word_index = fill_word_index and cpu_cache_index = hit_cache_index then
|
||||
instant_raw <= cpu_hit_we and cpu_en and not cpu_we;
|
||||
end if;
|
||||
instant_raw <= cpu_hit_we and cpu_en and en and not cpu_we;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_tag_ram : dpram_2w2r
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => tag_ram_addr_width,
|
||||
data_width => tag_ram_data_width
|
||||
inst_tag_ram : dpram_1w1r
|
||||
GENERIC MAP (
|
||||
addr_width => tram_addr_width,
|
||||
data_width => tram_data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => CLK_I,
|
||||
clk_b => CLK_I,
|
||||
PORT MAP (
|
||||
clka => CLK_I,
|
||||
clkb => CLK_I,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => tag_ram_we,
|
||||
we_b => '0',
|
||||
addr_a => tag_ram_addr_wr,
|
||||
addr_b => tag_ram_addr_rd,
|
||||
din_a => tag_ram_din,
|
||||
din_b => tag_ram_din,
|
||||
dout_a => tag_ram_dout_inv,
|
||||
dout_b => tag_ram_dout
|
||||
en_b => tram_re,
|
||||
we_a => tram_we,
|
||||
addr_a => tram_addr_wr,
|
||||
addr_b => tram_addr_rd,
|
||||
din_a => tram_din,
|
||||
dout_b => tram_dout
|
||||
);
|
||||
|
||||
gen_data_ram:
|
||||
@@ -303,45 +251,26 @@ gen_data_ram:
|
||||
begin
|
||||
|
||||
inst_data_ram : dpram_2w2r
|
||||
GENERIC MAP
|
||||
(
|
||||
GENERIC MAP (
|
||||
addr_width => lg2(cache_size),
|
||||
data_width => word_t'length/4
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
PORT MAP (
|
||||
clk_a => CLK_I,
|
||||
clk_b => CLK_I,
|
||||
en_a => '1',
|
||||
en_a => ctrl_dram_en,
|
||||
en_b => '1',
|
||||
we_a => cpu_data_ram_we(i),
|
||||
we_b => ctrl_data_ram_we(i),
|
||||
addr_a => ctrl_data_ram_addr,
|
||||
addr_b => cpu_data_ram_addr,
|
||||
din_a => cpu_data_reg(8*(i+1)-1 downto 8*i),
|
||||
din_b => DAT_I(8*(i+1)-1 downto 8*i),
|
||||
we_a => ctrl_dram_we(i),
|
||||
we_b => cpu_dram_we(i),
|
||||
addr_a => ctrl_dram_addr,
|
||||
addr_b => cpu_dram_addr,
|
||||
din_a => ctrl_dram_din(8*(i+1)-1 downto 8*i),
|
||||
din_b => cpu_dram_din(8*(i+1)-1 downto 8*i),
|
||||
dout_a => open,
|
||||
dout_b => cpu_data_ram_dout(8*(i+1)-1 downto 8*i)
|
||||
dout_b => cpu_dram_dout(8*(i+1)-1 downto 8*i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
cache_invalidate_request:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then
|
||||
invalidate_req <= '1';
|
||||
invalidate_all <= ctrl.inv_all or RST_I;
|
||||
tag_reg_inv <= tag_inv;
|
||||
elsif invalidate_ack = '1' then
|
||||
invalidate_req <= '0';
|
||||
invalidate_all <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cache_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
@@ -354,175 +283,146 @@ cache_state_next:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
MRDY_O <= fill_count_en;
|
||||
ADDR_O <= request_addr;
|
||||
cpu_busy <= cache_busy or instant_raw;
|
||||
cpu_dout <= cpu_dram_dout;
|
||||
|
||||
cpu_busy <= cache_busy;
|
||||
cpu_dout <= cpu_data_ram_dout;
|
||||
|
||||
tag_match <= '1' when fill_tag = cache_entry_out.tag else '0';
|
||||
tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0';
|
||||
cache_hit <= tag_match and cache_entry_out.valid;
|
||||
tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
|
||||
cache_hit_inv <= tag_match_inv and cache_entry_out_inv.valid;
|
||||
tag_ram_din <= to_tag_ram_data(cache_entry_in);
|
||||
tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index;
|
||||
tag_ram_addr_rd <= cpu_cache_index when (was_miss = '0' and instant_raw = '0') else fill_cache_index;
|
||||
|
||||
cache_entry_out <= to_dcache_entry(tag_ram_dout);
|
||||
cache_entry_out_inv <= to_dcache_entry(tag_ram_dout_inv);
|
||||
|
||||
cpu_data_ram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (fill_cache_index & fill_word_index);
|
||||
ctrl_data_ram_addr <= fill_cache_index & fill_word_index;
|
||||
ctrl_data_ram_we <= (others => fill_count_en and ACK_I);
|
||||
cpu_data_ram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
|
||||
tram_din <= to_tram_data(cache_entry_in);
|
||||
tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
|
||||
cache_entry_out <= to_dcache_entry(tram_dout);
|
||||
cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_hit_we = '0' and instant_raw = '0') else (cache_index_reg & word_index_reg);
|
||||
ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
|
||||
ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
|
||||
ctrl_dram_din <= DAT_I;
|
||||
ctrl_dram_we <= (others => '1');
|
||||
ctrl_dram_en <= data_write and ACK_I;
|
||||
cpu_dram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
|
||||
|
||||
cache_state:
|
||||
process(s, cache_req, instant_raw, cache_hit, cache_hit_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, cpu_we_reg, invalidate_req, invalidate_all)
|
||||
process(s, instant_raw, cache_hit, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg)
|
||||
begin
|
||||
cache_busy <= cache_req;
|
||||
cache_ack <= '0';
|
||||
tag_ram_we <= '0';
|
||||
flush_count_en <= '0';
|
||||
flush_count_rst <= '0';
|
||||
invalidate_en <= '0';
|
||||
request_count_en <= '0';
|
||||
fill_count_en <= '0';
|
||||
cpu_reg_en <= '0';
|
||||
cache_busy <= '1';
|
||||
tram_we <= '0';
|
||||
cache_index_count_en <= '0';
|
||||
ram_index_count_rst <= '0';
|
||||
mem_index_count_en <= '0';
|
||||
mem_index_count_rst <= '0';
|
||||
CYC_O <= '0';
|
||||
STB_O <= '0';
|
||||
tram_re <= '0';
|
||||
was_miss <= '0';
|
||||
invalidate_ack <= '0';
|
||||
|
||||
data_write <= '0';
|
||||
tram_addr_wr <= to_unsigned(cache_index_count, cache_index_width);
|
||||
cache_entry_in.tv_p <= (others => '0');
|
||||
cache_entry_in.tag <= fill_tag;
|
||||
cache_entry_in.tag <= tag_index_reg;
|
||||
cache_entry_in.valid <= '0';
|
||||
sn <= s;
|
||||
|
||||
case s is
|
||||
when init =>
|
||||
sn <= ready;
|
||||
sn <= flush;
|
||||
when ready =>
|
||||
if invalidate_req = '1' then
|
||||
sn <= invalidate;
|
||||
invalidate_en <= '1';
|
||||
else
|
||||
if cache_req = '1' then
|
||||
if cache_hit = '0' and cpu_we_reg = '0' then
|
||||
sn <= mem_request;
|
||||
CYC_O <= '1';
|
||||
else
|
||||
cache_busy <= instant_raw;
|
||||
cache_ack <= not instant_raw;
|
||||
end if;
|
||||
cache_busy <= '0';
|
||||
cpu_reg_en <= '1';
|
||||
tram_re <= cpu_en;
|
||||
if cpu_en2 = '1' then
|
||||
if cache_hit = '0' and cpu_we_reg = '0' then
|
||||
sn <= mem_request;
|
||||
cpu_reg_en <= '0';
|
||||
cache_busy <= '1';
|
||||
CYC_O <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when invalidate =>
|
||||
sn <= rd_cache;
|
||||
invalidate_en <= '1';
|
||||
invalidate_ack <= '1';
|
||||
if invalidate_all = '1' then
|
||||
sn <= flush;
|
||||
flush_count_rst <= '1';
|
||||
elsif cache_hit_inv = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
sn <= rd_cache;
|
||||
end if;
|
||||
|
||||
when flush =>
|
||||
flush_count_en <= '1';
|
||||
invalidate_en <= '1';
|
||||
tag_ram_we <= '1';
|
||||
cache_index_count_en <= '1';
|
||||
tram_addr_wr <= to_unsigned(cache_index_count, cache_index_width);
|
||||
tram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
if flush_count_rdy = '1' then
|
||||
tag_ram_we <= '0';
|
||||
sn <= rd_cache;
|
||||
if cache_index_count = 0 then
|
||||
sn <= ready;
|
||||
if cpu_en = '1' then
|
||||
cpu_reg_en <= '1';
|
||||
tram_re <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when mem_request =>
|
||||
ram_index_count_rst <= '1';
|
||||
mem_index_count_rst <= '1';
|
||||
CYC_O <= '1';
|
||||
if SRDY_I = '1' then
|
||||
sn <= mem_access;
|
||||
end if;
|
||||
when mem_access =>
|
||||
fill_count_en <= '1';
|
||||
request_count_en <= '1';
|
||||
data_write <= '1';
|
||||
mem_index_count_en <= '1';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
if request_count_rdy = '1' then
|
||||
STB_O <= '0';
|
||||
sn <= mem_data;
|
||||
if mem_index_count = 2**word_index_width-1 then
|
||||
if SRDY_I = '1' then
|
||||
sn <= mem_data;
|
||||
end if;
|
||||
end if;
|
||||
when mem_data =>
|
||||
CYC_O <= '1';
|
||||
fill_count_en <= '1';
|
||||
if fill_count_rdy = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '1';
|
||||
sn <= rd_cache;
|
||||
CYC_O <= '1';
|
||||
data_write <= '1';
|
||||
if ram_index_count = 2**word_index_width-1 then
|
||||
if ACK_I = '1' then
|
||||
sn <= upd_cache;
|
||||
end if;
|
||||
end if;
|
||||
when upd_cache =>
|
||||
tram_addr_wr <= cache_index_reg;
|
||||
tram_we <= '1';
|
||||
cache_entry_in.valid <= '1';
|
||||
sn <= rd_cache;
|
||||
when rd_cache =>
|
||||
tram_re <= '1';
|
||||
was_miss <= '1';
|
||||
sn <= ready;
|
||||
|
||||
when others =>
|
||||
sn <= ready;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
flush_counter:
|
||||
cache_index_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if ctrl.inv_at = '1' then
|
||||
flush_count <= to_integer(cache_index_inv);
|
||||
elsif flush_count_rst = '1' then
|
||||
flush_count_rdy <= '0';
|
||||
flush_count <= 2**cache_index_width-1;
|
||||
elsif flush_count_en = '1' then
|
||||
if flush_count /= 0 then
|
||||
flush_count <= flush_count - 1;
|
||||
else
|
||||
flush_count_rdy <= '1';
|
||||
end if;
|
||||
if cache_index_count_en = '0' then
|
||||
cache_index_count <= 2**cache_index_width-1;
|
||||
elsif cache_index_count /= 0 then
|
||||
cache_index_count <= cache_index_count - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_counter:
|
||||
ram_index_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '0' then
|
||||
request_count_rdy <= '0';
|
||||
request_count <= 2**word_index_width-1;
|
||||
else
|
||||
if SRDY_I = '1' then
|
||||
if request_count /= 0 then
|
||||
request_count <= request_count - 1;
|
||||
else
|
||||
request_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if ram_index_count_rst = '1' then
|
||||
ram_index_count <= 0;
|
||||
elsif data_write = '1' and ACK_I = '1' then
|
||||
if ram_index_count /= 2**word_index_width-1 then
|
||||
ram_index_count <= ram_index_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fill_counter:
|
||||
mem_index_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if fill_count_en = '0' then
|
||||
fill_count_rdy <= '0';
|
||||
fill_count <= 2**word_index_width-1;
|
||||
else
|
||||
if ACK_I = '1' then
|
||||
if fill_count /= 0 then
|
||||
fill_count <= fill_count - 1;
|
||||
else
|
||||
fill_count_rdy <= '1';
|
||||
end if;
|
||||
if mem_index_count_rst = '1' then
|
||||
mem_index_count <= 0;
|
||||
elsif mem_index_count_en = '1' and SRDY_I = '1' then
|
||||
if mem_index_count /= 2**word_index_width-1 then
|
||||
mem_index_count <= mem_index_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
+131
-265
@@ -1,29 +1,7 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: JIPS top file
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
@@ -40,12 +18,11 @@ ENTITY icache IS
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
STB_O : out STD_LOGIC;
|
||||
CYC_O : out STD_LOGIC;
|
||||
ctrl : in cache_ctrl_t;
|
||||
en : in STD_LOGIC;
|
||||
cpu_en : in STD_LOGIC;
|
||||
cpu_addr : in word_t;
|
||||
cpu_dout : out word_t;
|
||||
@@ -74,33 +51,20 @@ COMPONENT dpram_1w1r
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT dpram_2w2r is
|
||||
GENERIC
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
function lg2(x : natural) return natural is
|
||||
begin
|
||||
return natural(ceil(log2(real(x))));
|
||||
end lg2;
|
||||
|
||||
function po2(x : natural) return natural is
|
||||
begin
|
||||
|
||||
return 2**lg2(x);
|
||||
end po2;
|
||||
|
||||
constant addr_width : natural := 32;
|
||||
constant word_index_width : natural := lg2(line_size);
|
||||
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
|
||||
constant tag_width : natural := addr_width - word_index_width - cache_index_width - 2;
|
||||
constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
|
||||
constant tag_parity_width : natural := 3;
|
||||
constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width;
|
||||
constant tag_ram_addr_width : natural := cache_index_width;
|
||||
@@ -113,6 +77,10 @@ END COMPONENT;
|
||||
tag : unsigned(tag_width-1 downto 0);
|
||||
end record;
|
||||
|
||||
alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
|
||||
alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is
|
||||
variable result : icache_entry_t;
|
||||
begin
|
||||
@@ -133,168 +101,88 @@ END COMPONENT;
|
||||
return result;
|
||||
end to_tag_ram_data;
|
||||
|
||||
type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache, upd_cache);
|
||||
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
|
||||
signal s, sn : cache_state_t;
|
||||
|
||||
signal cache_req : std_logic;
|
||||
signal cache_ack : std_logic;
|
||||
signal cache_busy : std_logic;
|
||||
signal cache_miss : std_logic;
|
||||
signal tag_match : std_logic;
|
||||
signal cache_miss_inv : std_logic;
|
||||
signal tag_match_inv : std_logic;
|
||||
signal request_addr : unsigned(addr_width-1 downto 0);
|
||||
signal fill_addr : unsigned(addr_width-1 downto 0);
|
||||
|
||||
signal cache_index_inv : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_inv : unsigned(tag_width-1 downto 0);
|
||||
signal tag_reg_inv : unsigned(tag_width-1 downto 0);
|
||||
signal word_index_reg : unsigned(word_index_width-1 downto 0);
|
||||
signal cache_index_reg : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_index_reg : unsigned(tag_width-1 downto 0);
|
||||
|
||||
signal cache_entry_in : icache_entry_t;
|
||||
signal cache_entry_out : icache_entry_t;
|
||||
signal cache_entry_out_inv : icache_entry_t;
|
||||
signal data_ram_addr_rd : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal data_ram_data_rd : word_t;
|
||||
signal data_ram_addr_wr : unsigned(lg2(cache_size)-1 downto 0);
|
||||
signal data_ram_data_wr : word_t;
|
||||
signal data_ram_we : std_logic;
|
||||
signal data_ram_re : std_logic;
|
||||
|
||||
signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_data_rd : tag_ram_data_t;
|
||||
signal tag_ram_data_rd_inv : tag_ram_data_t;
|
||||
signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_ram_data_wr : tag_ram_data_t;
|
||||
signal tag_ram_re : std_logic;
|
||||
signal tag_ram_we : std_logic;
|
||||
|
||||
signal fill_count : natural range 0 to 2**word_index_width-1;
|
||||
signal fill_count_en : std_logic;
|
||||
signal fill_count_rdy : std_logic;
|
||||
signal flush_count : natural range 0 to 2**cache_index_width-1;
|
||||
signal flush_count_rst : std_logic;
|
||||
signal flush_count_en : std_logic;
|
||||
signal flush_count_rdy : std_logic;
|
||||
signal request_count : natural range 0 to 2**word_index_width-1;
|
||||
signal request_count_en : std_logic;
|
||||
signal request_count_rdy : std_logic;
|
||||
signal ram_read_en : std_logic;
|
||||
signal was_miss : std_logic;
|
||||
signal invalidate_all : std_logic;
|
||||
signal invalidate_ack : std_logic;
|
||||
signal invalidate_en : std_logic;
|
||||
signal invalidate_req : std_logic;
|
||||
|
||||
alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
|
||||
alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias fill_word_index is fill_addr(word_index_width+1 downto 2);
|
||||
alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias req_word_index is request_addr(word_index_width+1 downto 2);
|
||||
alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
signal ram_index_count : natural range 0 to 2**word_index_width-1;
|
||||
signal ram_index_count_rst : std_logic;
|
||||
signal cache_index_count : natural range 0 to 2**cache_index_width-1;
|
||||
signal cache_index_count_en : std_logic;
|
||||
signal mem_index_count : natural range 0 to 2**word_index_width-1;
|
||||
signal mem_index_count_en : std_logic;
|
||||
signal mem_index_count_rst : std_logic;
|
||||
signal cpu_reg_en : std_logic;
|
||||
signal was_miss : std_logic;
|
||||
signal data_write : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
ram_read_en <= cpu_en or was_miss;
|
||||
cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
|
||||
fill_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if fill_count_en = '1' then
|
||||
if ACK_I = '1' then
|
||||
fill_word_index <= fill_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
fill_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '1'then
|
||||
if SRDY_I = '1' then
|
||||
req_word_index <= req_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
request_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_request_register:
|
||||
cpu_index_reg:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
cache_req <= '0';
|
||||
elsif cpu_en = '1' then
|
||||
if cache_busy = '0' then
|
||||
cache_req <= '1';
|
||||
end if;
|
||||
elsif cache_ack = '1' then
|
||||
cache_req <= '0';
|
||||
cache_index_reg <= (others => '0');
|
||||
tag_index_reg <= (others => '0');
|
||||
elsif cpu_reg_en = '1' then
|
||||
word_index_reg <= cpu_word_index;
|
||||
cache_index_reg <= cpu_cache_index;
|
||||
tag_index_reg <= cpu_tag;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cache_invalidate_request:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then
|
||||
invalidate_req <= '1';
|
||||
invalidate_all <= ctrl.inv_all or RST_I;
|
||||
tag_reg_inv <= tag_inv;
|
||||
elsif invalidate_ack = '1' then
|
||||
invalidate_req <= '0';
|
||||
invalidate_all <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_tag_ram : dpram_2w2r
|
||||
GENERIC MAP
|
||||
(
|
||||
inst_tag_ram : dpram_1w1r
|
||||
GENERIC MAP (
|
||||
addr_width => tag_ram_addr_width,
|
||||
data_width => tag_ram_data_width
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => CLK_I,
|
||||
clk_b => CLK_I,
|
||||
PORT MAP (
|
||||
clka => CLK_I,
|
||||
clkb => CLK_I,
|
||||
en_a => '1',
|
||||
en_b => ram_read_en,
|
||||
en_b => tag_ram_re,
|
||||
we_a => tag_ram_we,
|
||||
we_b => '0',
|
||||
addr_a => tag_ram_addr_wr,
|
||||
addr_b => tag_ram_addr_rd,
|
||||
din_a => tag_ram_data_wr,
|
||||
din_b => tag_ram_data_wr,
|
||||
dout_a => tag_ram_data_rd_inv,
|
||||
dout_b => tag_ram_data_rd
|
||||
);
|
||||
|
||||
inst_data_ram : dpram_1w1r
|
||||
GENERIC MAP
|
||||
(
|
||||
GENERIC MAP (
|
||||
addr_width => lg2(cache_size),
|
||||
data_width => word_t'length
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
PORT MAP (
|
||||
clka => CLK_I,
|
||||
clkb => CLK_I,
|
||||
en_a => '1',
|
||||
en_b => ram_read_en,
|
||||
en_b => data_ram_re,
|
||||
we_a => data_ram_we,
|
||||
addr_a => data_ram_addr_wr,
|
||||
addr_b => data_ram_addr_rd,
|
||||
@@ -302,6 +190,7 @@ inst_data_ram : dpram_1w1r
|
||||
dout_b => data_ram_data_rd
|
||||
);
|
||||
|
||||
|
||||
cache_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
@@ -314,172 +203,149 @@ cache_state_next:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
MRDY_O <= fill_count_en;
|
||||
ADDR_O <= fill_tag & fill_cache_index & req_word_index & "00";
|
||||
|
||||
cpu_busy <= cache_busy;
|
||||
cpu_dout <= data_ram_data_rd;
|
||||
|
||||
cache_entry_out <= to_icache_entry(tag_ram_data_rd);
|
||||
tag_match <= '1' when fill_tag = cache_entry_out.tag else '0';
|
||||
tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0';
|
||||
cache_miss <= not (tag_match and cache_entry_out.valid);
|
||||
|
||||
cache_entry_out_inv <= to_icache_entry(tag_ram_data_rd_inv);
|
||||
tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
|
||||
cache_miss_inv <= not (tag_match_inv and cache_entry_out_inv.valid);
|
||||
|
||||
tag_ram_data_wr <= to_tag_ram_data(cache_entry_in);
|
||||
tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index;
|
||||
tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else fill_cache_index;
|
||||
data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (fill_cache_index & fill_word_index);
|
||||
data_ram_addr_wr <= fill_cache_index & fill_word_index;
|
||||
tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
|
||||
cache_entry_out <= to_icache_entry(tag_ram_data_rd);
|
||||
data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg);
|
||||
ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
|
||||
data_ram_addr_wr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
|
||||
data_ram_data_wr <= DAT_I;
|
||||
data_ram_we <= fill_count_en and ACK_I;
|
||||
data_ram_we <= data_write and ACK_I;
|
||||
|
||||
cache_state:
|
||||
process(s, cache_req, cache_miss, cache_miss_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, invalidate_req, invalidate_all)
|
||||
process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, en)
|
||||
begin
|
||||
cache_busy <= cache_req;
|
||||
cache_ack <= '0';
|
||||
cpu_reg_en <= '0';
|
||||
cache_busy <= '1';
|
||||
tag_ram_we <= '0';
|
||||
flush_count_en <= '0';
|
||||
flush_count_rst <= '0';
|
||||
invalidate_en <= '0';
|
||||
request_count_en <= '0';
|
||||
fill_count_en <= '0';
|
||||
cache_index_count_en <= '0';
|
||||
ram_index_count_rst <= '0';
|
||||
mem_index_count_en <= '0';
|
||||
mem_index_count_rst <= '0';
|
||||
CYC_O <= '0';
|
||||
STB_O <= '0';
|
||||
data_ram_re <= '0';
|
||||
tag_ram_re <= '0';
|
||||
was_miss <= '0';
|
||||
invalidate_ack <= '0';
|
||||
|
||||
data_write <= '0';
|
||||
tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width);
|
||||
cache_entry_in.tv_p <= (others => '0');
|
||||
cache_entry_in.tag <= fill_tag;
|
||||
cache_entry_in.tag <= tag_index_reg;
|
||||
cache_entry_in.valid <= '0';
|
||||
sn <= s;
|
||||
|
||||
case s is
|
||||
when init =>
|
||||
sn <= ready;
|
||||
sn <= flush;
|
||||
when ready =>
|
||||
if invalidate_req = '1' then
|
||||
sn <= invalidate;
|
||||
invalidate_en <= '1';
|
||||
elsif cache_req = '1' then
|
||||
if en = '1' then
|
||||
cache_busy <= '0';
|
||||
if cache_miss = '1' then
|
||||
sn <= mem_request;
|
||||
cpu_reg_en <= '0';
|
||||
cache_busy <= '1';
|
||||
CYC_O <= '1';
|
||||
else
|
||||
cache_busy <= '0';
|
||||
cache_ack <= '1';
|
||||
elsif cpu_en = '1' then
|
||||
cpu_reg_en <= '1';
|
||||
data_ram_re <= '1';
|
||||
tag_ram_re <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when invalidate =>
|
||||
sn <= rd_cache;
|
||||
invalidate_en <= '1';
|
||||
invalidate_ack <= '1';
|
||||
if invalidate_all = '1' then
|
||||
sn <= flush;
|
||||
flush_count_rst <= '1';
|
||||
elsif cache_miss_inv = '0' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
sn <= rd_cache;
|
||||
end if;
|
||||
|
||||
when flush =>
|
||||
flush_count_en <= '1';
|
||||
invalidate_en <= '1';
|
||||
cache_index_count_en <= '1';
|
||||
tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width);
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '0';
|
||||
cache_entry_in.tag <= (others => '0');
|
||||
if flush_count_rdy = '1' then
|
||||
tag_ram_we <= '0';
|
||||
sn <= rd_cache;
|
||||
if cache_index_count = 0 then
|
||||
sn <= ready;
|
||||
if cpu_en = '1' then
|
||||
cpu_reg_en <= '1';
|
||||
data_ram_re <= '1';
|
||||
tag_ram_re <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when mem_request =>
|
||||
ram_index_count_rst <= '1';
|
||||
mem_index_count_rst <= '1';
|
||||
CYC_O <= '1';
|
||||
if SRDY_I = '1' then
|
||||
sn <= mem_access;
|
||||
end if;
|
||||
when mem_access =>
|
||||
request_count_en <= '1';
|
||||
fill_count_en <= '1';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
if request_count_rdy = '1' then
|
||||
STB_O <= '0';
|
||||
sn <= mem_data;
|
||||
mem_index_count_en <= '1';
|
||||
data_write <= '1';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
if mem_index_count = 2**word_index_width-1 then
|
||||
if SRDY_I = '1' then
|
||||
sn <= mem_data;
|
||||
end if;
|
||||
end if;
|
||||
when mem_data =>
|
||||
CYC_O <= '1';
|
||||
fill_count_en <= '1';
|
||||
if fill_count_rdy = '1' then
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '1';
|
||||
sn <= rd_cache;
|
||||
CYC_O <= '1';
|
||||
data_write <= '1';
|
||||
if ram_index_count = 2**word_index_width-1 then
|
||||
if ACK_I = '1' then
|
||||
sn <= upd_cache;
|
||||
end if;
|
||||
end if;
|
||||
when upd_cache =>
|
||||
tag_ram_addr_wr <= cache_index_reg;
|
||||
tag_ram_we <= '1';
|
||||
cache_entry_in.valid <= '1';
|
||||
sn <= rd_cache;
|
||||
|
||||
when rd_cache =>
|
||||
was_miss <= '1';
|
||||
sn <= ready;
|
||||
tag_ram_re <= '1';
|
||||
data_ram_re <= '1';
|
||||
was_miss <= '1';
|
||||
sn <= ready;
|
||||
when others =>
|
||||
sn <= ready;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
flush_counter:
|
||||
cache_index_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if ctrl.inv_at = '1' then
|
||||
flush_count <= to_integer(cache_index_inv);
|
||||
elsif flush_count_rst = '1' then
|
||||
flush_count_rdy <= '0';
|
||||
flush_count <= 2**cache_index_width-1;
|
||||
elsif flush_count_en = '1' then
|
||||
if flush_count /= 0 then
|
||||
flush_count <= flush_count - 1;
|
||||
else
|
||||
flush_count_rdy <= '1';
|
||||
end if;
|
||||
if cache_index_count_en = '0' then
|
||||
cache_index_count <= 2**cache_index_width-1;
|
||||
elsif cache_index_count /= 0 then
|
||||
cache_index_count <= cache_index_count - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
request_counter:
|
||||
ram_index_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '0' then
|
||||
request_count_rdy <= '0';
|
||||
request_count <= 2**word_index_width-1;
|
||||
else
|
||||
if SRDY_I = '1' then
|
||||
if request_count /= 0 then
|
||||
request_count <= request_count - 1;
|
||||
else
|
||||
request_count_rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if ram_index_count_rst = '1' then
|
||||
ram_index_count <= 0;
|
||||
elsif data_write = '1' and ACK_I = '1' then
|
||||
if ram_index_count /= 2**word_index_width-1 then
|
||||
ram_index_count <= ram_index_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fill_counter:
|
||||
mem_index_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if fill_count_en = '0' then
|
||||
fill_count_rdy <= '0';
|
||||
fill_count <= 2**word_index_width-1;
|
||||
else
|
||||
if ACK_I = '1' then
|
||||
if fill_count /= 0 then
|
||||
fill_count <= fill_count - 1;
|
||||
else
|
||||
fill_count_rdy <= '1';
|
||||
end if;
|
||||
if mem_index_count_rst = '1' then
|
||||
mem_index_count <= 0;
|
||||
elsif mem_index_count_en = '1' and SRDY_I = '1' then
|
||||
if mem_index_count /= 2**word_index_width-1 then
|
||||
mem_index_count <= mem_index_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
@@ -32,9 +32,7 @@ entity biu is
|
||||
Generic
|
||||
(
|
||||
icache_size : natural := 2048; -- words
|
||||
icache_line : natural := 8; -- words
|
||||
dcache_size : natural := 2048; -- words
|
||||
dcache_line : natural := 8 -- words
|
||||
dcache_size : natural := 2048 -- words
|
||||
);
|
||||
Port
|
||||
(
|
||||
@@ -42,16 +40,14 @@ entity biu is
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
DAT_O : out word_t;
|
||||
WE_O : out STD_LOGIC;
|
||||
SEL_O : out unsigned(3 downto 0);
|
||||
CYC_O : out STD_LOGIC;
|
||||
STB_O : out STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
cop0_ctrl_in : in cop0_ctrl_out_t;
|
||||
cpu_clk : in STD_LOGIC;
|
||||
cpu_imem_err : out STD_LOGIC;
|
||||
cpu_imem_rdy : out STD_LOGIC;
|
||||
cpu_imem_en : in STD_LOGIC;
|
||||
@@ -82,12 +78,11 @@ architecture behavior of biu is
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
STB_O : out STD_LOGIC;
|
||||
CYC_O : out STD_LOGIC;
|
||||
ctrl : in cache_ctrl_t;
|
||||
en : in STD_LOGIC;
|
||||
cpu_en : in STD_LOGIC;
|
||||
cpu_addr : in word_t;
|
||||
cpu_dout : out word_t;
|
||||
@@ -107,12 +102,11 @@ architecture behavior of biu is
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
STB_O : out STD_LOGIC;
|
||||
CYC_O : out STD_LOGIC;
|
||||
ctrl : in cache_ctrl_t;
|
||||
en : in STD_LOGIC;
|
||||
cpu_en : in STD_LOGIC;
|
||||
cpu_we : in STD_LOGIC;
|
||||
cpu_be : in unsigned(3 downto 0);
|
||||
@@ -142,8 +136,6 @@ architecture behavior of biu is
|
||||
signal CYC_O_dmem_wr : std_logic;
|
||||
signal SRDY_I_icache : std_logic;
|
||||
signal SRDY_I_dcache : std_logic;
|
||||
signal MRDY_O_icache : std_logic;
|
||||
signal MRDY_O_dcache : std_logic;
|
||||
signal ADDR_O_icache : word_t;
|
||||
signal ADDR_O_dcache : word_t;
|
||||
signal ADDR_O_dmem_rd : word_t;
|
||||
@@ -155,14 +147,10 @@ architecture behavior of biu is
|
||||
signal DAT_I_dmem_rd : word_t;
|
||||
signal DAT_O_dmem_wr : word_t;
|
||||
signal SEL_O_dmem_wr : unsigned(3 downto 0);
|
||||
signal SEL_O_dmem_rd : unsigned(3 downto 0);
|
||||
signal dcached : std_logic;
|
||||
signal dcache_en2 : std_logic;
|
||||
signal dcache_en : std_logic;
|
||||
signal uncached_access : std_logic;
|
||||
signal ACK : std_logic;
|
||||
signal DAT : unsigned(31 downto 0);
|
||||
|
||||
|
||||
type timeout_cnt_t is range 0 to 1E5-1;
|
||||
signal bus_timeout_cnt : timeout_cnt_t;
|
||||
signal bus_timeout : std_logic;
|
||||
@@ -175,13 +163,6 @@ architecture behavior of biu is
|
||||
signal bout_fifo_empty : std_logic;
|
||||
signal bout_rdy : std_logic;
|
||||
|
||||
signal bin_fifo_din : unsigned(31 downto 0);
|
||||
signal bin_fifo_dout : unsigned(31 downto 0);
|
||||
signal bin_fifo_re : std_logic;
|
||||
signal bin_fifo_we : std_logic;
|
||||
signal bin_fifo_full : std_logic;
|
||||
signal bin_fifo_empty : std_logic;
|
||||
|
||||
alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
|
||||
alias bout_fifo_data_in is bout_fifo_din(63 downto 32);
|
||||
alias bout_fifo_sel_in is bout_fifo_din(67 downto 64);
|
||||
@@ -197,6 +178,7 @@ architecture behavior of biu is
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
signal write_busy : std_logic;
|
||||
|
||||
alias write_fifo_addr_in is write_fifo_din(31 downto 0);
|
||||
alias write_fifo_data_in is write_fifo_din(63 downto 32);
|
||||
@@ -209,10 +191,13 @@ architecture behavior of biu is
|
||||
|
||||
begin
|
||||
|
||||
|
||||
MRDY_O <= '1';
|
||||
|
||||
read_cyc_register:
|
||||
process(cpu_clk)
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
read_cycle <= '0';
|
||||
else
|
||||
@@ -223,7 +208,6 @@ read_cyc_register:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
MRDY_O <= not bin_fifo_full;
|
||||
CYC_O <= not bout_fifo_empty or read_cycle;
|
||||
STB_O <= not bout_fifo_empty;
|
||||
ADDR_O <= bout_fifo_addr_out;
|
||||
@@ -232,27 +216,26 @@ read_cyc_register:
|
||||
WE_O <= bout_fifo_we_out;
|
||||
|
||||
cpu_imem_rdy <= not icache_busy after 4.5 ns;
|
||||
busy <= CYC_O_dmem_rd or dcache_busy or (write_fifo_full);
|
||||
busy <= CYC_O_dmem_rd or dcache_busy or (write_busy);
|
||||
cpu_dmem_rdy <= not busy after 4.5 ns;
|
||||
|
||||
inst_icache : icache
|
||||
GENERIC MAP
|
||||
(
|
||||
cache_size => icache_size, -- words
|
||||
line_size => icache_line -- words
|
||||
line_size => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => cpu_clk,
|
||||
CLK_I => CLK_I,
|
||||
RST_I => RST_I,
|
||||
STB_O => STB_O_icache,
|
||||
CYC_O => CYC_O_icache,
|
||||
ADDR_O => ADDR_O_icache,
|
||||
MRDY_O => MRDY_O_icache,
|
||||
DAT_I => DAT,
|
||||
ACK_I => ACK,
|
||||
DAT_I => DAT_I,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I_icache,
|
||||
ctrl => cop0_ctrl_in.icache,
|
||||
en => '1',
|
||||
cpu_en => cpu_imem_en,
|
||||
cpu_addr => cpu_imem_addr,
|
||||
cpu_dout => cpu_imem_din,
|
||||
@@ -265,20 +248,19 @@ inst_dcache : dcache
|
||||
GENERIC MAP
|
||||
(
|
||||
cache_size => dcache_size, -- words
|
||||
line_size => dcache_line -- words
|
||||
line_size => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => cpu_clk,
|
||||
CLK_I => CLK_I,
|
||||
RST_I => RST_I,
|
||||
CYC_O => CYC_O_dcache,
|
||||
STB_O => STB_O_dcache,
|
||||
ADDR_O => ADDR_O_dcache,
|
||||
MRDY_O => MRDY_O_dcache,
|
||||
DAT_I => DAT,
|
||||
ACK_I => ACK,
|
||||
DAT_I => DAT_I,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I_dcache,
|
||||
ctrl => cop0_ctrl_in.dcache,
|
||||
en => dcached,
|
||||
cpu_en => dcache_en,
|
||||
cpu_we => cpu_dmem_we,
|
||||
cpu_be => cpu_dmem_be,
|
||||
@@ -290,52 +272,21 @@ inst_dcache : dcache
|
||||
|
||||
SRDY_I_dcache <= bout_rdy and dcache_mem_gnt;
|
||||
|
||||
dcached <= '1' when cpu_dmem_addr(31 downto 29) /= "101" else '0';
|
||||
dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0';
|
||||
cpu_dmem_din <= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd;
|
||||
dcache_en <= dcached and cpu_dmem_en and dcache_en2; -- or write_fifo_full);
|
||||
dcache_en <= cpu_dmem_en and not busy;
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_bin_fifo: entity work.fifo_async
|
||||
inst_bout_fifo: entity work.fifo_sync_dist
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => 32,
|
||||
do_last_read_update => true
|
||||
addr_width => 4,
|
||||
data_width => 69
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST_I,
|
||||
clk_w => CLK_I,
|
||||
clk_r => cpu_clk,
|
||||
we => bin_fifo_we,
|
||||
re => bin_fifo_re,
|
||||
fifo_full => bin_fifo_full,
|
||||
fifo_empty => bin_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => bin_fifo_din,
|
||||
data_r => bin_fifo_dout
|
||||
);
|
||||
|
||||
bin_fifo_din <= DAT_I;
|
||||
DAT <= bin_fifo_dout;
|
||||
ACK <= not bin_fifo_empty;
|
||||
bin_fifo_we <= ACK_I;
|
||||
bin_fifo_re <= dmem_mem_rd_gnt or MRDY_O_icache or MRDY_O_dcache;
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_bout_fifo: entity work.fifo_async
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => 69,
|
||||
do_last_read_update => false
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST_I,
|
||||
clk_w => cpu_clk,
|
||||
clk_r => CLK_I,
|
||||
clk => CLK_I,
|
||||
we => bout_fifo_we,
|
||||
re => bout_fifo_re,
|
||||
fifo_full => bout_fifo_full,
|
||||
@@ -346,7 +297,7 @@ inst_bout_fifo: entity work.fifo_async
|
||||
data_r => bout_fifo_dout
|
||||
);
|
||||
bout_rdy <= not bout_fifo_full;
|
||||
bout_fifo_re <= SRDY_I and not bin_fifo_full;
|
||||
bout_fifo_re <= not bout_fifo_empty and SRDY_I;
|
||||
|
||||
bout_fifo_we <= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
|
||||
|
||||
@@ -357,26 +308,23 @@ inst_bout_fifo: entity work.fifo_async
|
||||
ADDR_O_dcache when dcache_mem_gnt = '1' else
|
||||
ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
|
||||
|
||||
bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else
|
||||
SEL_O_dmem_rd when dmem_mem_rd_gnt = '1' else (others => '1');
|
||||
|
||||
bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '0');
|
||||
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_write_fifo: entity work.fifo_sync
|
||||
inst_write_fifo: entity work.fifo_sync_dist
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 4,
|
||||
data_width => 68,
|
||||
do_last_read_update => true
|
||||
data_width => 68
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => RST_I,
|
||||
clk => cpu_clk,
|
||||
clk => CLK_I,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_full => write_busy,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
@@ -396,23 +344,20 @@ inst_write_fifo: entity work.fifo_sync
|
||||
write_fifo_we <= cpu_dmem_en and not busy and cpu_dmem_we;
|
||||
|
||||
dmem_rd_flags:
|
||||
process(cpu_clk)
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if rising_edge(CLK_I) then
|
||||
uncached_access <= '0';
|
||||
if RST_I = '1' then
|
||||
CYC_O_dmem_rd <= '0';
|
||||
dcache_en2 <= '1';
|
||||
else
|
||||
if ACK = '1' and dmem_mem_rd_gnt = '1' then
|
||||
if ACK_I = '1' and dmem_mem_rd_gnt = '1' then
|
||||
uncached_access <= '1';
|
||||
CYC_O_dmem_rd <= '0';
|
||||
dcache_en2 <= '1';
|
||||
end if;
|
||||
if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then
|
||||
if dcached = '0' then
|
||||
CYC_O_dmem_rd <= '1';
|
||||
dcache_en2 <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
@@ -420,32 +365,31 @@ dmem_rd_flags:
|
||||
end process;
|
||||
|
||||
dmem_rd_data:
|
||||
process(cpu_clk)
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
DAT_I_dmem_rd <= (others => '0');
|
||||
elsif ACK = '1' and CYC_O_dmem_rd = '1' then
|
||||
DAT_I_dmem_rd <= DAT;
|
||||
elsif ACK_I = '1' and CYC_O_dmem_rd = '1' then
|
||||
DAT_I_dmem_rd <= DAT_I;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dmem_rd_regs:
|
||||
process(cpu_clk)
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if rising_edge(CLK_I) then
|
||||
if cpu_dmem_en = '1' and busy = '0' then
|
||||
ADDR_O_dmem_rd <= cpu_dmem_addr;
|
||||
SEL_O_dmem_rd <= cpu_dmem_be;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bus_state_next:
|
||||
process(cpu_clk)
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
s <= init;
|
||||
else
|
||||
@@ -455,7 +399,7 @@ bus_state_next:
|
||||
end process;
|
||||
|
||||
bus_state:
|
||||
process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK)
|
||||
process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK_I)
|
||||
begin
|
||||
|
||||
icache_mem_gnt <= '0';
|
||||
@@ -507,7 +451,7 @@ bus_state:
|
||||
end if;
|
||||
when read_finish =>
|
||||
dmem_mem_rd_gnt <= '1';
|
||||
if ACK = '1' then
|
||||
if ACK_I = '1' then
|
||||
sn <= ready;
|
||||
end if;
|
||||
when others =>
|
||||
@@ -517,9 +461,9 @@ bus_state:
|
||||
end process;
|
||||
|
||||
bus_timeout_counter:
|
||||
process(cpu_clk)
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if rising_edge(CLK_I) then
|
||||
if bus_idle = '0' then
|
||||
if bus_timeout_cnt /= 0 then
|
||||
bus_timeout_cnt <= bus_timeout_cnt - 1;
|
||||
@@ -534,9 +478,9 @@ bus_timeout_counter:
|
||||
end process;
|
||||
|
||||
bus_err:
|
||||
process(cpu_clk)
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
cpu_imem_err <= '0';
|
||||
cpu_dmem_err <= '0';
|
||||
|
||||
+138
-269
@@ -29,24 +29,16 @@ use work.mips_types.all;
|
||||
use work.mips_instr.all;
|
||||
|
||||
entity cop is
|
||||
Generic
|
||||
(
|
||||
icache_size : natural := 2048; -- words
|
||||
icache_line : natural := 8; -- words
|
||||
dcache_size : natural := 2048; -- words
|
||||
dcache_line : natural := 8 -- words
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
eb : in STD_LOGIC;
|
||||
int : in unsigned(5 downto 0);
|
||||
nmi : in STD_LOGIC;
|
||||
ir_en : in STD_LOGIC;
|
||||
ir : in word_t;
|
||||
ctrl_in : in cop0_ctrl_in_t;
|
||||
ctrl_out : out cop0_ctrl_out_t;
|
||||
sdu : in sdu_t;
|
||||
IR_valid : in STD_LOGIC;
|
||||
IR : in word_t;
|
||||
events : in event_t;
|
||||
ctrl_in : in cop_ctrl_in_t;
|
||||
ctrl_out : out cop_ctrl_out_t;
|
||||
din : in word_t;
|
||||
dout : out word_t
|
||||
);
|
||||
@@ -57,8 +49,6 @@ architecture Behavioral of cop is
|
||||
signal epc : word_t;
|
||||
signal cause : word_t;
|
||||
signal status : word_t;
|
||||
signal imem_addr : word_t;
|
||||
signal imem_addr_we : STD_LOGIC;
|
||||
signal BadVAddr : word_t;
|
||||
signal exc_code : unsigned(4 downto 0);
|
||||
signal test_reg : word_t;
|
||||
@@ -69,30 +59,20 @@ architecture Behavioral of cop is
|
||||
signal code_reg_we : STD_LOGIC;
|
||||
signal ip_reg_we : STD_LOGIC;
|
||||
signal bd : STD_LOGIC;
|
||||
signal sw_int : unsigned(1 downto 0);
|
||||
signal ip : unsigned(7 downto 0);
|
||||
signal im : unsigned(7 downto 0);
|
||||
signal status_save : STD_LOGIC;
|
||||
signal status_rest : STD_LOGIC;
|
||||
signal exception : STD_LOGIC;
|
||||
signal exception_end : STD_LOGIC;
|
||||
signal eflags : exc_flags_t;
|
||||
signal EB_reg : STD_LOGIC;
|
||||
signal icache_info : unsigned(7 downto 0);
|
||||
signal dcache_info : unsigned(7 downto 0);
|
||||
signal reg_rptr : reg_ptr_t;
|
||||
signal reg_wptr : reg_ptr_t;
|
||||
signal inject_exc : STD_LOGIC;
|
||||
signal latch_vect_en : STD_LOGIC;
|
||||
signal int_nmi : STD_LOGIC;
|
||||
signal nmi_asserted : std_logic;
|
||||
|
||||
signal exc_enable : STD_LOGIC;
|
||||
signal cop_EX_en : STD_LOGIC;
|
||||
|
||||
type cop_pipe_t is record
|
||||
opc : opcode_t;
|
||||
RFE : std_logic;
|
||||
CO : std_logic;
|
||||
reg_ptr : reg_ptr_t;
|
||||
din : word_t;
|
||||
rs : reg_ptr_t;
|
||||
rd : reg_ptr_t;
|
||||
rt : reg_ptr_t;
|
||||
func : func_t;
|
||||
we : std_logic;
|
||||
re : std_logic;
|
||||
@@ -113,130 +93,93 @@ architecture Behavioral of cop is
|
||||
return result;
|
||||
end eval_int;
|
||||
|
||||
type exc_state_t is (exc_idle, exc_pipe_flush, exc_commit, exc_inject, exc_enter, exc_leave, exc_left);
|
||||
type exc_state_t is (exc_init, exc_idle, exc_commit_ID, exc_commit_EX, exc_commit_MEM);
|
||||
signal exc_state, exc_staten : exc_state_t;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
icache_info <= "00" & to_unsigned(lg2(icache_line), 3) & to_unsigned(lg2(icache_size)-8, 3);
|
||||
dcache_info <= "00" & to_unsigned(lg2(dcache_line), 3) & to_unsigned(lg2(dcache_size)-8, 3);
|
||||
cop_pipe_ID.cs <= ir_en;
|
||||
cop_pipe_ID.opc <= extract_opc(ir);
|
||||
cop_pipe_ID.rs <= extract_rs(ir);
|
||||
cop_pipe_ID.rd <= extract_rd(ir);
|
||||
cop_pipe_ID.rt <= extract_rt(ir);
|
||||
cop_pipe_ID.func <= extract_func(ir);
|
||||
cop_pipe_ID.CO <= ir(25);
|
||||
cop_pipe_ID.re <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00000")) else '0';
|
||||
cop_pipe_ID.we <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00100")) else '0';
|
||||
cop_pipe_ID.RFE <= cop_pipe_ID.cs when (cop_pipe_ID.CO = '1' and cop_pipe_ID.func = "010000") else '0';
|
||||
ctrl_out.EB <= EB_reg xor (status(25) and status(1));
|
||||
cop_pipe_ID.din <= din;
|
||||
cop_pipe_ID.cs <= IR_valid;
|
||||
cop_pipe_ID.rs <= extract_rs(IR);
|
||||
cop_pipe_ID.rd <= extract_rd(IR);
|
||||
cop_pipe_ID.func <= extract_func(IR);
|
||||
cop_pipe_ID.re <= cop_pipe_ID.cs when cop_pipe_ID.rs = "00000" else '0';
|
||||
cop_pipe_ID.we <= cop_pipe_ID.cs when cop_pipe_ID.rs = "00100" else '0';
|
||||
cop_EX_en <= exc_enable and not status_save;
|
||||
|
||||
ctrl_out.ee <= exc_enable;
|
||||
ctrl_out.ec <= status_save;
|
||||
ctrl_out.RE <= status(25);
|
||||
ctrl_out.user_mode <= status(1);
|
||||
ctrl_out.exc_inject <= inject_exc or rst;
|
||||
cop_pipe_ID.reg_ptr <= cop_pipe_ID.rd when cop_pipe_ID.opc = "010000" else cop_pipe_ID.rt;
|
||||
ctrl_out.int <= eflags.Int;
|
||||
|
||||
ctrl_out.cop_read <= cop_pipe_EX.cs and cop_pipe_EX.re after 1 ns;
|
||||
ctrl_out.reg_write <= cop_pipe_ID.re after 1 ns;
|
||||
|
||||
im <= status(15 downto 8);
|
||||
cause <= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00";
|
||||
|
||||
eflags.Ov <= ctrl_in.events.alu_ovf or ctrl_in.events.alu_uvf;
|
||||
eflags.DAdEL <= ctrl_in.events.data_load_err;
|
||||
eflags.DAdES <= ctrl_in.events.data_store_err;
|
||||
eflags.IAdEL <= ctrl_in.events.inst_load_err;
|
||||
eflags.IAdEK <= ctrl_in.events.inst_priv_addr and status(1);
|
||||
eflags.Sys <= ctrl_in.events.syscall;
|
||||
eflags.Bp <= ctrl_in.events.break;
|
||||
eflags.RI <= ctrl_in.events.illegal;
|
||||
eflags.Int <= ctrl_in.events.int;
|
||||
eflags.Ov <= events.alu_ovf or events.alu_uvf;
|
||||
eflags.DAdEL <= events.data_load_err;
|
||||
eflags.DAdES <= events.data_store_err;
|
||||
eflags.IAdEL <= events.inst_load_err;
|
||||
eflags.IAdEK <= events.inst_priv_addr and status(1);
|
||||
eflags.Sys <= events.syscall;
|
||||
eflags.Bp <= events.break;
|
||||
eflags.RI <= events.illegal;
|
||||
eflags.Int <= eval_int(ip) and status(0);
|
||||
|
||||
-- NMI/RST transition detector
|
||||
proc_nmi_transition:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
int_nmi <= '0';
|
||||
nmi_asserted <= '0';
|
||||
elsif latch_vect_en = '1' then
|
||||
int_nmi <= '0';
|
||||
elsif nmi_asserted = '1' then
|
||||
if nmi = '0' then
|
||||
nmi_asserted <= '0';
|
||||
int_nmi <= '1';
|
||||
end if;
|
||||
elsif nmi = '1' then
|
||||
nmi_asserted <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Main exception FSM
|
||||
proc_exc_state:
|
||||
process(exc_state, ctrl_in, cop_pipe_ID)
|
||||
exception <= eflags.Ov or eflags.Sys or eflags.Bp or eflags.RI or eflags.IAdEL or eflags.IAdEK or eflags.DAdEL or eflags.DAdES or eflags.Int after 1 ns;
|
||||
|
||||
exception_state:
|
||||
process(exc_state, ctrl_in, exception, sdu)
|
||||
begin
|
||||
|
||||
exc_enable <= '0';
|
||||
ctrl_out.exc_commit <= '0';
|
||||
ctrl_out.exc_pending <= '0';
|
||||
ctrl_out.exc_exit <= '0';
|
||||
epc_reg_we <= '0';
|
||||
code_reg_we <= '0';
|
||||
status_save <= '0';
|
||||
status_rest <= '0';
|
||||
inject_exc <= '0';
|
||||
imem_addr_we <= '0';
|
||||
latch_vect_en <= '0';
|
||||
eflags_reg_we <= '0';
|
||||
|
||||
exc_staten <= exc_state;
|
||||
|
||||
case exc_state is
|
||||
|
||||
when exc_init =>
|
||||
exc_staten <= exc_idle;
|
||||
|
||||
when exc_idle =>
|
||||
if cop_pipe_ID.RFE = '1' then
|
||||
exc_staten <= exc_leave;
|
||||
ctrl_out.exc_exit <= '1';
|
||||
ctrl_out.exc_commit <= '1';
|
||||
elsif ctrl_in.exc_req = '1' then
|
||||
exc_staten <= exc_pipe_flush;
|
||||
imem_addr_we <= '1';
|
||||
exc_enable <= '1';
|
||||
if exception = '1' then
|
||||
status_save <= '1';
|
||||
eflags_reg_we <= '1';
|
||||
code_reg_we <= '1';
|
||||
exc_staten <= exc_commit_ID;
|
||||
end if;
|
||||
|
||||
when exc_pipe_flush =>
|
||||
when exc_commit_ID =>
|
||||
ctrl_out.exc_pending <= '1';
|
||||
ctrl_out.exc_commit <= '1';
|
||||
if ctrl_in.exc_ack = '1' then
|
||||
exc_staten <= exc_commit;
|
||||
if sdu.ID_stall = '0' then
|
||||
exc_staten <= exc_commit_EX;
|
||||
end if;
|
||||
|
||||
when exc_commit =>
|
||||
latch_vect_en <= '1';
|
||||
when exc_commit_EX =>
|
||||
ctrl_out.exc_pending <= '1';
|
||||
ctrl_out.exc_commit <= '1';
|
||||
if ctrl_in.sdu.ID_stall = '0' then
|
||||
exc_staten <= exc_inject;
|
||||
if sdu.EX_stall = '0' then
|
||||
exc_staten <= exc_commit_MEM;
|
||||
end if;
|
||||
|
||||
when exc_inject =>
|
||||
when exc_commit_MEM =>
|
||||
ctrl_out.exc_pending <= '1';
|
||||
ctrl_out.exc_commit <= '1';
|
||||
code_reg_we <= '1';
|
||||
status_save <= '1';
|
||||
epc_reg_we <= '1';
|
||||
inject_exc <= '1';
|
||||
exc_staten <= exc_enter;
|
||||
|
||||
when exc_enter =>
|
||||
ctrl_out.exc_pending <= '1';
|
||||
exc_staten <= exc_idle;
|
||||
|
||||
when exc_leave =>
|
||||
exc_staten <= exc_left;
|
||||
status_rest <= '1';
|
||||
ctrl_out.exc_exit <= '1';
|
||||
ctrl_out.exc_commit <= '1';
|
||||
|
||||
when exc_left =>
|
||||
exc_staten <= exc_idle;
|
||||
if sdu.MEM_stall = '0' then
|
||||
epc_reg_we <= '1';
|
||||
exc_staten <= exc_idle;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
exc_staten <= exc_idle;
|
||||
@@ -244,48 +187,25 @@ proc_exc_state:
|
||||
end case;
|
||||
end process;
|
||||
|
||||
proc_exc_state_next:
|
||||
exception_state_next:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
exc_state <= exc_idle;
|
||||
exc_state <= exc_init;
|
||||
else
|
||||
exc_state <= exc_staten;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Endian switch sampled at hard reset
|
||||
sample_endian:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
EB_reg <= eb;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Sample imem_addr for later use
|
||||
exception_last_imem_addr:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if imem_addr_we = '1' then
|
||||
imem_addr <= ctrl_in.imem_addr;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- EPC reg and BD-bit write
|
||||
cop_exception_epc_write:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
bd <= '0';
|
||||
epc <= (others => '0');
|
||||
bd <= '0';
|
||||
epc <= (others => '0');
|
||||
elsif epc_reg_we = '1' then
|
||||
bd <= '0';
|
||||
epc <= ctrl_in.epc_mem;
|
||||
@@ -297,7 +217,6 @@ cop_exception_epc_write:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- BadVaddr and exception code write
|
||||
cop_exception_map:
|
||||
process(clk)
|
||||
begin
|
||||
@@ -316,10 +235,10 @@ cop_exception_map:
|
||||
exc_code <= "01010";
|
||||
elsif eflags.IAdEL = '1' then
|
||||
exc_code <= "00100";
|
||||
BadVAddr <= imem_addr;
|
||||
BadVAddr <= ctrl_in.imem_addr;
|
||||
elsif eflags.IAdEK = '1' then
|
||||
exc_code <= "00100";
|
||||
BadVAddr <= imem_addr;
|
||||
BadVAddr <= ctrl_in.imem_addr;
|
||||
elsif eflags.DAdEL = '1' then
|
||||
exc_code <= "00100";
|
||||
BadVAddr <= ctrl_in.dmem_addr;
|
||||
@@ -333,78 +252,51 @@ cop_exception_map:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ctrl_out.icache.inv_addr <= test_reg;
|
||||
ctrl_out.dcache.inv_addr <= test_reg;
|
||||
|
||||
-- Custom I/D-Cache operations: invalidate all/line
|
||||
cop_cache_op:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
ctrl_out.icache.inv_at <= '0';
|
||||
ctrl_out.icache.inv_all <= '0';
|
||||
ctrl_out.dcache.inv_at <= '0';
|
||||
ctrl_out.dcache.inv_all <= '0';
|
||||
if cop_pipe_ID.cs = '1' and cop_pipe_ID.CO = '1' then
|
||||
case cop_pipe_ID.func is
|
||||
when "100000" =>
|
||||
ctrl_out.icache.inv_all <= '1';
|
||||
when "100001" =>
|
||||
ctrl_out.icache.inv_at <= '1';
|
||||
when "100010" =>
|
||||
ctrl_out.dcache.inv_all <= '1';
|
||||
when "100011" =>
|
||||
ctrl_out.dcache.inv_at <= '1';
|
||||
status_rest <= exception_end and ctrl_in.exc_left;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- IP register write and signalling Int to pipeline
|
||||
cop_ip_reg_write:
|
||||
cop_status_restore:
|
||||
process(clk)
|
||||
variable ip_v : unsigned(7 downto 0);
|
||||
variable ipm_v : unsigned(7 downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
sw_int <= (others => '0');
|
||||
elsif ctrl_in.sdu.WB_nop = '0' then
|
||||
if ip_reg_we = '1' then
|
||||
sw_int <= din(9 downto 8);
|
||||
exception_end <= '0';
|
||||
ctrl_out.exc_exit <= '0';
|
||||
else
|
||||
if cop_pipe_ID.func = "10000" and exception_end = '0' then -- RFE
|
||||
exception_end <= cop_pipe_ID.cs;
|
||||
ctrl_out.exc_exit <= cop_pipe_ID.cs;
|
||||
elsif exception_end = '1' and ctrl_in.exc_left = '1' then
|
||||
exception_end <= '0';
|
||||
ctrl_out.exc_exit <= '0';
|
||||
end if;
|
||||
end if;
|
||||
ip_v := (int & sw_int);
|
||||
ipm_v := ip_v and im;
|
||||
ip <= ip_v;
|
||||
ctrl_out.int <= (eval_int(ipm_v) and status(0));
|
||||
ctrl_out.NMI <= int_nmi;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Exception vector dispatch
|
||||
cop_ip_reg_write:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
ip(1 downto 0) <= (others => '0');
|
||||
elsif ip_reg_we = '1' then
|
||||
ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8) and im(1 downto 0);
|
||||
end if;
|
||||
ip(7 downto 2) <= events.Int and im(7 downto 2);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cop_exc_vector:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
ctrl_out.exc_vec <= X"BFC00000";
|
||||
elsif latch_vect_en = '1' then
|
||||
if ctrl_in.events.nmi = '1' then
|
||||
ctrl_out.exc_vec <= X"BFC00000";
|
||||
else
|
||||
ctrl_out.exc_vec <= X"80000080";
|
||||
if status(22) = '1' then
|
||||
ctrl_out.exc_vec <= X"BFC00180";
|
||||
end if;
|
||||
end if;
|
||||
ctrl_out.exc_vec <= X"80000180";
|
||||
if status(22) = '1' then
|
||||
ctrl_out.exc_vec <= X"BFC00180";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Cop pipeline
|
||||
cop_pipe:
|
||||
process(clk)
|
||||
begin
|
||||
@@ -413,53 +305,46 @@ cop_pipe:
|
||||
cop_pipe_EX.cs <= '0';
|
||||
cop_pipe_EX.we <= '0';
|
||||
cop_pipe_EX.re <= '0';
|
||||
elsif ctrl_in.sdu.stall_all = '0' then
|
||||
cop_pipe_EX <= cop_pipe_ID;
|
||||
if cop_pipe_ID.we = '1' then
|
||||
reg_wptr <= cop_pipe_ID.reg_ptr;
|
||||
end if;
|
||||
if cop_pipe_ID.re = '1' then
|
||||
reg_rptr <= cop_pipe_ID.reg_ptr;
|
||||
else
|
||||
if sdu.EX_stall = '0' then
|
||||
cop_pipe_EX <= cop_pipe_ID;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- COP Register read
|
||||
cop_register_read:
|
||||
process(reg_rptr, BadVAddr, status, cause, epc, dcache_info, icache_info, test_reg)
|
||||
process(clk)
|
||||
variable reg : word_t;
|
||||
begin
|
||||
|
||||
case reg_rptr is
|
||||
when "01000" => -- BadVAddr
|
||||
reg := BadVAddr;
|
||||
if rising_edge(clk) and cop_pipe_ID.re = '1' and sdu.ID_stall = '0' then
|
||||
case cop_pipe_ID.rd is
|
||||
when "01000" => -- BadVAddr
|
||||
reg := BadVAddr;
|
||||
|
||||
when "01100" => -- Status
|
||||
reg := status;
|
||||
when "01100" => -- Status
|
||||
reg := status;
|
||||
|
||||
when "01101" => -- Cause
|
||||
reg := cause;
|
||||
when "01101" => -- Cause
|
||||
reg := cause;
|
||||
|
||||
when "01110" => -- EPC (Exception Program Counter)
|
||||
reg := epc;
|
||||
when "01110" => -- EPC (Exception Program Counter)
|
||||
reg := epc;
|
||||
|
||||
when "01111" => -- PRId (Processor Revision Register)
|
||||
reg := dcache_info & icache_info & X"02" & to_unsigned(REVISION ,8);
|
||||
when "01111" => -- PRId (Processor Revision Register)
|
||||
reg := X"000002" & to_unsigned(REVISION ,8);
|
||||
|
||||
when "11111" => -- test_reg
|
||||
reg := test_reg;
|
||||
when "11111" => -- test_reg
|
||||
reg := test_reg;
|
||||
|
||||
when others =>
|
||||
reg := (others => '-');
|
||||
|
||||
end case;
|
||||
|
||||
dout <= reg after 2 ns;
|
||||
when others =>
|
||||
reg := (others => '-');
|
||||
|
||||
end case;
|
||||
dout <= reg after 1 ns;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- COP Register write strobe generation
|
||||
cop_we_gen:
|
||||
process(clk)
|
||||
begin
|
||||
@@ -468,20 +353,20 @@ cop_we_gen:
|
||||
test_reg_we <= '0';
|
||||
stat_reg_we <= '0';
|
||||
ip_reg_we <= '0';
|
||||
elsif ctrl_in.sdu.stall_all = '0' then
|
||||
else
|
||||
test_reg_we <= '0';
|
||||
stat_reg_we <= '0';
|
||||
ip_reg_we <= '0';
|
||||
if cop_pipe_EX.we = '1' then
|
||||
if (cop_EX_en and cop_pipe_EX.we) = '1' then
|
||||
|
||||
case reg_wptr is
|
||||
case cop_pipe_EX.rd is
|
||||
|
||||
when "01100" =>
|
||||
stat_reg_we <= '1'; -- not status(1) or status(28);
|
||||
stat_reg_we <= not status(1) or status(28);
|
||||
when "01101" =>
|
||||
ip_reg_we <= '1'; -- not status(1) or status(28);
|
||||
ip_reg_we <= not status(1) or status(28);
|
||||
when "11111" =>
|
||||
test_reg_we <= '1'; -- not status(1) or status(28);
|
||||
test_reg_we <= not status(1) or status(28);
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
@@ -491,54 +376,38 @@ cop_we_gen:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- COP Test Register
|
||||
cop_test_reg_write:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
test_reg <= (others => '0');
|
||||
elsif ctrl_in.sdu.WB_nop = '0' then
|
||||
else --if ce = '1' then
|
||||
if test_reg_we = '1' then
|
||||
test_reg <= din;
|
||||
test_reg <= cop_pipe_EX.din;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- COP Status Register
|
||||
cop_status_reg_write:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
status <= X"00600000";
|
||||
elsif status_save = '1' then
|
||||
if ctrl_in.events.nmi = '0' then
|
||||
status <= X"00400000";
|
||||
else
|
||||
if status_save = '1' then
|
||||
status(5 downto 4) <= status(3 downto 2);
|
||||
status(3 downto 2) <= status(1 downto 0);
|
||||
else
|
||||
status(22) <= '1';
|
||||
status(1 downto 0) <= "00";
|
||||
elsif status_rest = '1' then
|
||||
status(1 downto 0) <= status(3 downto 2);
|
||||
status(3 downto 2) <= status(5 downto 4);
|
||||
elsif stat_reg_we = '1' then
|
||||
status <= cop_pipe_EX.din;
|
||||
end if;
|
||||
status(1 downto 0) <= "00";
|
||||
elsif status_rest = '1' then
|
||||
status(1 downto 0) <= status(3 downto 2);
|
||||
status(3 downto 2) <= status(5 downto 4);
|
||||
elsif ctrl_in.sdu.WB_nop = '0' then
|
||||
if stat_reg_we = '1' then
|
||||
if status(1) = '0' then
|
||||
status(0) <= din(0); -- IEc
|
||||
status(1) <= din(1); -- KUc
|
||||
status(2) <= din(2); -- IEp
|
||||
status(3) <= din(3); -- KUp
|
||||
status(4) <= din(4); -- IEo
|
||||
status(5) <= din(5); -- KUo
|
||||
end if;
|
||||
status(15 downto 8) <= din(15 downto 8); -- IM
|
||||
status(22) <= din(22); -- BEV
|
||||
status(25) <= din(25); -- RE
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
@@ -0,0 +1,101 @@
|
||||
--------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: The datapath controller
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_instr.all;
|
||||
|
||||
entity idecode_rom is
|
||||
Port
|
||||
(
|
||||
nop : in std_logic;
|
||||
inst_in : in word_t;
|
||||
ctrl_out : out ctrl_lines_t
|
||||
);
|
||||
end idecode_rom;
|
||||
|
||||
architecture Behavioral of idecode_rom is
|
||||
|
||||
signal ctrl_special : ctrl_lines_t;
|
||||
signal ctrl_regimm : ctrl_lines_t;
|
||||
signal ctrl_opcode : ctrl_lines_t;
|
||||
|
||||
signal rom_special : rom_special_t := gen_rom_special;
|
||||
signal rom_regimm : rom_regimm_t := gen_rom_regimm;
|
||||
signal rom_opcode : rom_opcode_t := gen_rom_opcode;
|
||||
|
||||
attribute rom_style : string;
|
||||
|
||||
attribute rom_style of rom_special: signal is "distributed";
|
||||
attribute rom_style of rom_regimm: signal is "distributed";
|
||||
attribute rom_style of rom_opcode: signal is "distributed";
|
||||
|
||||
begin
|
||||
|
||||
i_dec_special:
|
||||
process(inst_in, rom_special)
|
||||
variable func : func_t;
|
||||
begin
|
||||
func := extract_func(inst_in);
|
||||
ctrl_special <= rom_special(to_integer(func));
|
||||
end process;
|
||||
|
||||
i_dec_regimm:
|
||||
process(inst_in, rom_regimm)
|
||||
variable rt : reg_ptr_t;
|
||||
begin
|
||||
rt := extract_rt(inst_in);
|
||||
ctrl_regimm <= rom_regimm(to_integer(rt));
|
||||
end process;
|
||||
|
||||
i_dec_opcode:
|
||||
process(inst_in, rom_opcode)
|
||||
variable opc : opcode_t;
|
||||
begin
|
||||
opc := extract_opc(inst_in);
|
||||
ctrl_opcode <= rom_opcode(to_integer(opc));
|
||||
end process;
|
||||
|
||||
proc_decode:
|
||||
process(inst_in, ctrl_special, ctrl_regimm, ctrl_opcode, nop)
|
||||
variable opclass : opcode_t;
|
||||
begin
|
||||
opclass := extract_opc(inst_in);
|
||||
ctrl_out <= ctrl_lines_default after 2 ns;
|
||||
if nop = '0' then
|
||||
case opclass is
|
||||
when "000000" =>
|
||||
ctrl_out <= ctrl_special after 2 ns;
|
||||
when "000001" =>
|
||||
ctrl_out <= ctrl_regimm after 2 ns;
|
||||
when others =>
|
||||
ctrl_out <= ctrl_opcode after 2 ns;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -43,7 +43,12 @@ package mips_instr is
|
||||
function extract_bimm18(instr, pc : word_t) return word_t;
|
||||
function decode_op(instr : word_t) return op_t;
|
||||
function ctrl_lines_default return ctrl_lines_t;
|
||||
function opcode_ctrl_lines(instr : word_t) return ctrl_lines_t;
|
||||
function special_ctrl_lines(func : func_t) return ctrl_lines_t;
|
||||
function regimm_ctrl_lines(rt : reg_ptr_t) return ctrl_lines_t;
|
||||
function opcode_ctrl_lines(opc : opcode_t) return ctrl_lines_t;
|
||||
function gen_rom_opcode return rom_opcode_t;
|
||||
function gen_rom_regimm return rom_regimm_t;
|
||||
function gen_rom_special return rom_special_t;
|
||||
|
||||
end mips_instr;
|
||||
|
||||
@@ -148,16 +153,14 @@ package body mips_instr is
|
||||
variable opc : natural range 0 to 63;
|
||||
variable func : natural range 0 to 63;
|
||||
variable rt : natural range 0 to 31;
|
||||
variable rs : natural range 0 to 31;
|
||||
|
||||
begin
|
||||
|
||||
opc := to_integer(extract_opc(instr));
|
||||
func := to_integer(extract_func(instr));
|
||||
rt := to_integer(extract_rt(instr));
|
||||
rs := to_integer(extract_rs(instr));
|
||||
|
||||
result := reserved;
|
||||
result := op_sll;
|
||||
|
||||
case opc is
|
||||
|
||||
@@ -315,103 +318,15 @@ package body mips_instr is
|
||||
|
||||
when 16 =>
|
||||
result := op_cop0;
|
||||
case rs is
|
||||
when 0 =>
|
||||
result := op_mfc0;
|
||||
when 2 =>
|
||||
result := op_cfc0; -- illegal
|
||||
when 4 =>
|
||||
result := op_mtc0;
|
||||
when 6 =>
|
||||
result := op_ctc0; -- illegal
|
||||
when 8 =>
|
||||
case rt is
|
||||
when 0 =>
|
||||
result := op_bcf0; -- illegal
|
||||
when 1 =>
|
||||
result := op_bct0; -- illegal
|
||||
|
||||
when others => null; -- undef
|
||||
end case;
|
||||
|
||||
when others => null; -- undef
|
||||
|
||||
end case;
|
||||
|
||||
when 17 =>
|
||||
result := op_cop1;
|
||||
case rs is
|
||||
when 0 =>
|
||||
result := op_mfc1;
|
||||
when 2 =>
|
||||
result := op_cfc1;
|
||||
when 4 =>
|
||||
result := op_mtc1;
|
||||
when 6 =>
|
||||
result := op_ctc1;
|
||||
when 8 =>
|
||||
case rt is
|
||||
when 0 =>
|
||||
result := op_bcf1;
|
||||
when 1 =>
|
||||
result := op_bct1;
|
||||
|
||||
when others => null; -- undef
|
||||
end case;
|
||||
|
||||
when others => null; -- undef
|
||||
|
||||
end case;
|
||||
|
||||
when 18 =>
|
||||
result := op_cop2;
|
||||
case rs is
|
||||
when 0 =>
|
||||
result := op_mfc2;
|
||||
when 2 =>
|
||||
result := op_cfc2;
|
||||
when 4 =>
|
||||
result := op_mtc2;
|
||||
when 6 =>
|
||||
result := op_ctc2;
|
||||
when 8 =>
|
||||
case rt is
|
||||
when 0 =>
|
||||
result := op_bcf2;
|
||||
when 1 =>
|
||||
result := op_bct2;
|
||||
|
||||
when others => null; -- undef
|
||||
end case;
|
||||
|
||||
when others => null; -- undef
|
||||
|
||||
end case;
|
||||
|
||||
when 19 =>
|
||||
result := op_cop3;
|
||||
case rs is
|
||||
when 0 =>
|
||||
result := op_mfc3;
|
||||
when 2 =>
|
||||
result := op_cfc3;
|
||||
when 4 =>
|
||||
result := op_mtc3;
|
||||
when 6 =>
|
||||
result := op_ctc3;
|
||||
when 8 =>
|
||||
case rt is
|
||||
when 0 =>
|
||||
result := op_bcf3;
|
||||
when 1 =>
|
||||
result := op_bct3;
|
||||
|
||||
when others => null; -- undef
|
||||
end case;
|
||||
|
||||
when others => null; -- undef
|
||||
|
||||
end case;
|
||||
|
||||
when 32 =>
|
||||
result := op_lb;
|
||||
@@ -449,9 +364,6 @@ package body mips_instr is
|
||||
when 46 =>
|
||||
result := op_swr;
|
||||
|
||||
when 48 =>
|
||||
result := op_lwc0; -- illegal
|
||||
|
||||
when 49 =>
|
||||
result := op_lwc1;
|
||||
|
||||
@@ -461,9 +373,6 @@ package body mips_instr is
|
||||
when 51 =>
|
||||
result := op_lwc3;
|
||||
|
||||
when 56 =>
|
||||
result := op_swc0; -- illegal
|
||||
|
||||
when 57 =>
|
||||
result := op_swc1;
|
||||
|
||||
@@ -485,7 +394,6 @@ package body mips_instr is
|
||||
variable result : ctrl_lines_t;
|
||||
begin
|
||||
result.cop_instr_en := '0';
|
||||
result.cop_read := '0';
|
||||
result.jump := '0';
|
||||
result.jump_long := '0';
|
||||
result.branch := '0';
|
||||
@@ -528,286 +436,312 @@ package body mips_instr is
|
||||
|
||||
end ctrl_lines_default;
|
||||
|
||||
function opcode_ctrl_lines(instr : word_t) return ctrl_lines_t is
|
||||
|
||||
function special_ctrl_lines(func : func_t) return ctrl_lines_t is
|
||||
variable result : ctrl_lines_t;
|
||||
variable opc : integer range 0 to 2**opcode_t'length-1;
|
||||
variable func : integer range 0 to 2**func_t'length-1;
|
||||
variable rt : integer range 0 to 2**reg_ptr_t'length-1;
|
||||
variable rs : integer range 0 to 2**reg_ptr_t'length-1;
|
||||
variable op : integer range 0 to 2**func_t'length-1;
|
||||
begin
|
||||
|
||||
result := ctrl_lines_default;
|
||||
opc := to_integer(extract_opc(instr));
|
||||
func := to_integer(extract_func(instr));
|
||||
rt := to_integer(extract_rt(instr));
|
||||
rs := to_integer(extract_rs(instr));
|
||||
result := ctrl_lines_default;
|
||||
|
||||
op := to_integer(func);
|
||||
case op is
|
||||
|
||||
case opc is
|
||||
-- SPECIAL
|
||||
when 0 =>
|
||||
case func is
|
||||
-- when op_add =>
|
||||
when 32 =>
|
||||
result.alu.outsel := alu_adder;
|
||||
result.alu.add := '1';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
result.alu_exc_en := '1';
|
||||
|
||||
-- when op_add =>
|
||||
when 32 =>
|
||||
result.alu.outsel := alu_adder;
|
||||
result.alu.add := '1';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
result.alu_exc_en := '1';
|
||||
-- when op_addu =>
|
||||
when 33 =>
|
||||
result.alu.outsel := alu_adder;
|
||||
result.alu.add := '1';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_addu =>
|
||||
when 33 =>
|
||||
result.alu.outsel := alu_adder;
|
||||
result.alu.add := '1';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
-- when op_and =>
|
||||
when 36 =>
|
||||
result.alu.outsel := alu_and;
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_and =>
|
||||
when 36 =>
|
||||
result.alu.outsel := alu_and;
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
-- when op_break =>
|
||||
when 13 =>
|
||||
result.exc_break := '1';
|
||||
result.except_en := '1';
|
||||
|
||||
-- when op_break =>
|
||||
when 13 =>
|
||||
result.exc_break := '1';
|
||||
result.except_en := '1';
|
||||
|
||||
-- when op_div =>
|
||||
when 26 =>
|
||||
result.mul_access := '1';
|
||||
result.mul_start := '1';
|
||||
result.mul_s_un := '1';
|
||||
result.mul_mul_divn := '0';
|
||||
|
||||
-- when op_divu =>
|
||||
when 27 =>
|
||||
result.mul_access := '1';
|
||||
result.mul_start := '1';
|
||||
result.mul_s_un := '0';
|
||||
result.mul_mul_divn := '0';
|
||||
|
||||
-- when op_jalr =>
|
||||
when 9 =>
|
||||
result.jump_long := '1';
|
||||
result.wptr_srcsel := wptr_src_imm;
|
||||
result.reg_write := '1';
|
||||
result.reg_link := '1';
|
||||
|
||||
-- when op_jr =>
|
||||
when 8 =>
|
||||
result.jump_long := '1';
|
||||
|
||||
-- when op_mfhi =>
|
||||
when 16 =>
|
||||
result.reg_write := '1';
|
||||
result.mul_access := '1';
|
||||
result.mul_hilo_sel := '1';
|
||||
|
||||
-- when op_mflo =>
|
||||
when 18 =>
|
||||
result.reg_write := '1';
|
||||
result.mul_access := '1';
|
||||
result.mul_hilo_sel := '0';
|
||||
|
||||
-- when op_mthi =>
|
||||
when 17 =>
|
||||
result.mul_hilo_we := '1';
|
||||
result.mul_hilo_sel := '1';
|
||||
|
||||
-- when op_mtlo =>
|
||||
when 19 =>
|
||||
result.mul_hilo_we := '1';
|
||||
result.mul_hilo_sel := '0';
|
||||
|
||||
-- when op_mult =>
|
||||
when 24 =>
|
||||
result.mul_access := '1';
|
||||
result.mul_start := '1';
|
||||
result.mul_s_un := '1';
|
||||
result.mul_mul_divn := '1';
|
||||
|
||||
-- when op_multu =>
|
||||
when 25 =>
|
||||
result.mul_access := '1';
|
||||
result.mul_start := '1';
|
||||
result.mul_s_un := '0';
|
||||
result.mul_mul_divn := '1';
|
||||
|
||||
-- when op_or =>
|
||||
when 37 =>
|
||||
result.alu.outsel := alu_or;
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_nor =>
|
||||
when 39 =>
|
||||
result.alu.outsel := alu_nor;
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sll =>
|
||||
when 0 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '0';
|
||||
result.shamt2_srcsel := sa_src_imm;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sllv =>
|
||||
when 4 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '0';
|
||||
result.shamt2_srcsel := sa_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_slt =>
|
||||
when 42 =>
|
||||
result.alu.outsel := alu_lts;
|
||||
result.alu.add := '0';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sltu =>
|
||||
when 43 =>
|
||||
result.alu.outsel := alu_ltu;
|
||||
result.alu.add := '0';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sra =>
|
||||
when 3 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '1';
|
||||
result.alu.shift_arith := '1';
|
||||
result.shamt2_srcsel := sa_src_imm;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_srav =>
|
||||
when 7 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '1';
|
||||
result.alu.shift_arith := '1';
|
||||
result.shamt2_srcsel := sa_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_srl =>
|
||||
when 2 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '1';
|
||||
result.alu.shift_arith := '0';
|
||||
result.shamt2_srcsel := sa_src_imm;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_srlv =>
|
||||
when 6 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '1';
|
||||
result.alu.shift_arith := '0';
|
||||
result.shamt2_srcsel := sa_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sub =>
|
||||
when 34 =>
|
||||
result.alu.outsel := alu_adder;
|
||||
result.alu.add := '0';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
result.alu_exc_en := '1';
|
||||
|
||||
-- when op_subu =>
|
||||
when 35 =>
|
||||
result.alu.outsel := alu_adder;
|
||||
result.alu.add := '0';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_syscall =>
|
||||
when 12 =>
|
||||
result.exc_syscall := '1';
|
||||
result.except_en := '1';
|
||||
|
||||
-- when op_xor =>
|
||||
when 38 =>
|
||||
result.alu.outsel := alu_xor;
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
when others =>
|
||||
result.exc_illegal := '1';
|
||||
|
||||
end case;
|
||||
|
||||
-- REGIMM
|
||||
when 1 =>
|
||||
case rt is
|
||||
|
||||
-- when op_bgez =>
|
||||
when 1 =>
|
||||
result.branch := '1';
|
||||
result.bc_src := bc_ltz_gez;
|
||||
result.bc_not := '1';
|
||||
|
||||
-- when op_bgezal =>
|
||||
when 17 =>
|
||||
result.branch := '1';
|
||||
result.bc_src := bc_ltz_gez;
|
||||
result.bc_not := '1';
|
||||
result.wptr_srcsel := wptr_src_const;
|
||||
result.reg_write := '1';
|
||||
result.reg_link := '1';
|
||||
|
||||
-- when op_bltz =>
|
||||
when 0 =>
|
||||
result.branch := '1';
|
||||
result.bc_src := bc_ltz_gez;
|
||||
result.bc_not := '0';
|
||||
|
||||
-- when op_bltzal =>
|
||||
when 16 =>
|
||||
result.branch := '1';
|
||||
result.bc_src := bc_ltz_gez;
|
||||
result.bc_not := '0';
|
||||
result.wptr_srcsel := wptr_src_const;
|
||||
result.reg_write := '1';
|
||||
result.reg_link := '1';
|
||||
|
||||
when others =>
|
||||
result.exc_illegal := '1';
|
||||
|
||||
end case;
|
||||
|
||||
-- when COPz =>
|
||||
when 16 | 17 | 18 | 19 =>
|
||||
result.cop_instr_en := '1';
|
||||
case rs is
|
||||
when 0 => -- MFCz
|
||||
result.cop_read := '1';
|
||||
result.reg_write := '1';
|
||||
when 2 => -- CFCz
|
||||
result.cop_read := '1';
|
||||
result.reg_write := '1';
|
||||
|
||||
when others => null; -- undef
|
||||
-- when op_div =>
|
||||
when 26 =>
|
||||
result.mul_access := '1';
|
||||
result.mul_start := '1';
|
||||
result.mul_s_un := '1';
|
||||
result.mul_mul_divn := '0';
|
||||
|
||||
end case;
|
||||
-- when op_divu =>
|
||||
when 27 =>
|
||||
result.mul_access := '1';
|
||||
result.mul_start := '1';
|
||||
result.mul_s_un := '0';
|
||||
result.mul_mul_divn := '0';
|
||||
|
||||
-- when op_jalr =>
|
||||
when 9 =>
|
||||
result.jump_long := '1';
|
||||
result.wptr_srcsel := wptr_src_imm;
|
||||
result.reg_write := '1';
|
||||
result.reg_link := '1';
|
||||
|
||||
-- when op_jr =>
|
||||
when 8 =>
|
||||
result.jump_long := '1';
|
||||
|
||||
-- when op_mfhi =>
|
||||
when 16 =>
|
||||
result.reg_write := '1';
|
||||
result.mul_access := '1';
|
||||
result.mul_hilo_sel := '1';
|
||||
|
||||
-- when op_mflo =>
|
||||
when 18 =>
|
||||
result.reg_write := '1';
|
||||
result.mul_access := '1';
|
||||
result.mul_hilo_sel := '0';
|
||||
|
||||
-- when op_mthi =>
|
||||
when 17 =>
|
||||
result.mul_hilo_we := '1';
|
||||
result.mul_hilo_sel := '1';
|
||||
|
||||
-- when op_mtlo =>
|
||||
when 19 =>
|
||||
result.mul_hilo_we := '1';
|
||||
result.mul_hilo_sel := '0';
|
||||
|
||||
-- when op_mult =>
|
||||
when 24 =>
|
||||
result.mul_access := '1';
|
||||
result.mul_start := '1';
|
||||
result.mul_s_un := '1';
|
||||
result.mul_mul_divn := '1';
|
||||
|
||||
-- when op_multu =>
|
||||
when 25 =>
|
||||
result.mul_access := '1';
|
||||
result.mul_start := '1';
|
||||
result.mul_s_un := '0';
|
||||
result.mul_mul_divn := '1';
|
||||
|
||||
-- when op_or =>
|
||||
when 37 =>
|
||||
result.alu.outsel := alu_or;
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_nor =>
|
||||
when 39 =>
|
||||
result.alu.outsel := alu_nor;
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sll =>
|
||||
when 0 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '0';
|
||||
result.shamt2_srcsel := sa_src_imm;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sllv =>
|
||||
when 4 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '0';
|
||||
result.shamt2_srcsel := sa_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_slt =>
|
||||
when 42 =>
|
||||
result.alu.outsel := alu_lts;
|
||||
result.alu.add := '0';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sltu =>
|
||||
when 43 =>
|
||||
result.alu.outsel := alu_ltu;
|
||||
result.alu.add := '0';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sra =>
|
||||
when 3 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '1';
|
||||
result.alu.shift_arith := '1';
|
||||
result.shamt2_srcsel := sa_src_imm;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_srav =>
|
||||
when 7 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '1';
|
||||
result.alu.shift_arith := '1';
|
||||
result.shamt2_srcsel := sa_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_srl =>
|
||||
when 2 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '1';
|
||||
result.alu.shift_arith := '0';
|
||||
result.shamt2_srcsel := sa_src_imm;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_srlv =>
|
||||
when 6 =>
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.alu.outsel := alu_shift2;
|
||||
result.alu.shift_right := '1';
|
||||
result.alu.shift_arith := '0';
|
||||
result.shamt2_srcsel := sa_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_sub =>
|
||||
when 34 =>
|
||||
result.alu.outsel := alu_adder;
|
||||
result.alu.add := '0';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
result.alu_exc_en := '1';
|
||||
|
||||
-- when op_subu =>
|
||||
when 35 =>
|
||||
result.alu.outsel := alu_adder;
|
||||
result.alu.add := '0';
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
-- when op_syscall =>
|
||||
when 12 =>
|
||||
result.exc_syscall := '1';
|
||||
result.except_en := '1';
|
||||
|
||||
-- when op_xor =>
|
||||
when 38 =>
|
||||
result.alu.outsel := alu_xor;
|
||||
result.alu.op1_src := alu_src_reg;
|
||||
result.alu.op2_src := alu_src_reg;
|
||||
result.reg_write := '1';
|
||||
|
||||
when others =>
|
||||
result.exc_illegal := '1';
|
||||
|
||||
end case;
|
||||
|
||||
return result;
|
||||
|
||||
end special_ctrl_lines;
|
||||
|
||||
function gen_rom_special return rom_special_t is
|
||||
variable result : rom_special_t;
|
||||
variable func : func_t;
|
||||
begin
|
||||
|
||||
for i in 0 to 2**func_t'length-1 loop
|
||||
func := to_unsigned(i, func_t'length);
|
||||
result(i) := special_ctrl_lines(func);
|
||||
end loop;
|
||||
|
||||
return result;
|
||||
end gen_rom_special;
|
||||
|
||||
function regimm_ctrl_lines(rt : reg_ptr_t) return ctrl_lines_t is
|
||||
variable result : ctrl_lines_t;
|
||||
variable op : integer range 0 to 2**reg_ptr_t'length-1;
|
||||
begin
|
||||
|
||||
result := ctrl_lines_default;
|
||||
|
||||
op := to_integer(rt);
|
||||
case op is
|
||||
|
||||
-- when op_bgez =>
|
||||
when 1 =>
|
||||
result.branch := '1';
|
||||
result.bc_src := bc_ltz_gez;
|
||||
result.bc_not := '1';
|
||||
|
||||
-- when op_bgezal =>
|
||||
when 17 =>
|
||||
result.branch := '1';
|
||||
result.bc_src := bc_ltz_gez;
|
||||
result.bc_not := '1';
|
||||
result.wptr_srcsel := wptr_src_const;
|
||||
result.reg_write := '1';
|
||||
result.reg_link := '1';
|
||||
|
||||
-- when op_bltz =>
|
||||
when 0 =>
|
||||
result.branch := '1';
|
||||
result.bc_src := bc_ltz_gez;
|
||||
result.bc_not := '0';
|
||||
|
||||
-- when op_bltzal =>
|
||||
when 16 =>
|
||||
result.branch := '1';
|
||||
result.bc_src := bc_ltz_gez;
|
||||
result.bc_not := '0';
|
||||
result.wptr_srcsel := wptr_src_const;
|
||||
result.reg_write := '1';
|
||||
result.reg_link := '1';
|
||||
|
||||
when others =>
|
||||
result.exc_illegal := '1';
|
||||
|
||||
end case;
|
||||
|
||||
return result;
|
||||
|
||||
end regimm_ctrl_lines;
|
||||
|
||||
function gen_rom_regimm return rom_regimm_t is
|
||||
variable result : rom_regimm_t;
|
||||
variable rt : reg_ptr_t;
|
||||
begin
|
||||
|
||||
for i in 0 to 2**reg_ptr_t'length-1 loop
|
||||
rt := to_unsigned(i, reg_ptr_t'length);
|
||||
result(i) := regimm_ctrl_lines(rt);
|
||||
end loop;
|
||||
|
||||
return result;
|
||||
end gen_rom_regimm;
|
||||
|
||||
function opcode_ctrl_lines(opc : opcode_t) return ctrl_lines_t is
|
||||
variable result : ctrl_lines_t;
|
||||
variable op : integer range 0 to 2**opcode_t'length-1;
|
||||
begin
|
||||
|
||||
result := ctrl_lines_default;
|
||||
|
||||
op := to_integer(opc);
|
||||
case op is
|
||||
|
||||
-- when op_addi =>
|
||||
when 8 =>
|
||||
result.imm_src := src_imm32;
|
||||
@@ -859,6 +793,10 @@ package body mips_instr is
|
||||
result.bc_src := bc_eq_ne;
|
||||
result.bc_not := '1';
|
||||
|
||||
-- when op_cop =>
|
||||
when 16 | 17 | 18 | 19 =>
|
||||
result.cop_instr_en := '1';
|
||||
|
||||
-- when op_j =>
|
||||
when 2 =>
|
||||
result.jump := '1';
|
||||
@@ -932,13 +870,6 @@ package body mips_instr is
|
||||
result.reg_write := '1';
|
||||
result.except_en := '1';
|
||||
|
||||
-- when op_lwcz =>
|
||||
when 48 | 49 | 50 | 51 =>
|
||||
-- result.imm_src := src_imm32;
|
||||
result.dmem_en := '1';
|
||||
result.except_en := '1';
|
||||
result.cop_instr_en := '1';
|
||||
|
||||
-- when op_lwl =>
|
||||
when 34 =>
|
||||
-- result.imm_src := src_imm32;
|
||||
@@ -1011,15 +942,6 @@ package body mips_instr is
|
||||
-- result.imm_src := src_imm32;
|
||||
result.except_en := '1';
|
||||
|
||||
-- when op_swcz =>
|
||||
when 56 | 57 | 58 | 59 =>
|
||||
result.dmem_en := '1';
|
||||
result.dmem_we := '1';
|
||||
-- result.imm_src := src_imm32;
|
||||
result.except_en := '1';
|
||||
result.cop_instr_en := '1';
|
||||
result.cop_read := '1';
|
||||
|
||||
-- when op_swl =>
|
||||
when 42 =>
|
||||
result.dmem_en := '1';
|
||||
@@ -1055,6 +977,19 @@ package body mips_instr is
|
||||
|
||||
end opcode_ctrl_lines;
|
||||
|
||||
function gen_rom_opcode return rom_opcode_t is
|
||||
variable result : rom_opcode_t;
|
||||
variable opc : opcode_t;
|
||||
begin
|
||||
|
||||
for i in 0 to 2**opcode_t'length-1 loop
|
||||
opc := to_unsigned(i, opcode_t'length);
|
||||
result(i) := opcode_ctrl_lines(opc);
|
||||
end loop;
|
||||
|
||||
return result;
|
||||
end gen_rom_opcode;
|
||||
|
||||
end mips_instr;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
@@ -33,7 +33,8 @@ entity pipeline is
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
halt : in STD_LOGIC;
|
||||
int : in unsigned(5 downto 0);
|
||||
imem_err : in STD_LOGIC;
|
||||
imem_rdy : in STD_LOGIC;
|
||||
imem_en : out STD_LOGIC;
|
||||
@@ -46,14 +47,7 @@ entity pipeline is
|
||||
dmem_be : out unsigned(3 downto 0);
|
||||
dmem_addr : out word_t;
|
||||
dmem_din : in word_t;
|
||||
dmem_dout : out word_t;
|
||||
cop_ir : out word_t;
|
||||
cop_ir_en : out STD_LOGIC;
|
||||
cop_din : in word_t;
|
||||
cop_dout : out word_t;
|
||||
c0_ctrl_out : out cop0_ctrl_in_t;
|
||||
c0_ctrl_in : in cop0_ctrl_out_t
|
||||
|
||||
dmem_dout : out word_t
|
||||
);
|
||||
end pipeline;
|
||||
|
||||
@@ -80,6 +74,16 @@ architecture Behavioral of pipeline is
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
COMPONENT idecode_rom is
|
||||
Port
|
||||
(
|
||||
nop : in std_logic;
|
||||
inst_in : in word_t;
|
||||
ctrl_out : out ctrl_lines_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
COMPONENT shifter is
|
||||
Generic
|
||||
@@ -125,6 +129,23 @@ architecture Behavioral of pipeline is
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
COMPONENT cop is
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
sdu : in sdu_t;
|
||||
IR_valid : in STD_LOGIC;
|
||||
IR : in word_t;
|
||||
events : in event_t;
|
||||
ctrl_in : in cop_ctrl_in_t;
|
||||
ctrl_out : out cop_ctrl_out_t;
|
||||
din : in word_t;
|
||||
dout : out word_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
COMPONENT muldiv is
|
||||
Port
|
||||
@@ -144,6 +165,8 @@ architecture Behavioral of pipeline is
|
||||
END COMPONENT;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
constant RESET_VECTOR : word_t := X"BFC00000";
|
||||
|
||||
signal ID_stage : ID_t;
|
||||
signal EX_stage : EX_t;
|
||||
signal MEM_stage : MEM_t;
|
||||
@@ -151,10 +174,20 @@ architecture Behavioral of pipeline is
|
||||
signal clk_2, clk_1 : STD_LOGIC;
|
||||
signal hdu : hdu_t;
|
||||
signal sdu : sdu_t;
|
||||
signal cpu_rst : STD_LOGIC;
|
||||
signal reg_a : word_t;
|
||||
signal reg_b : word_t;
|
||||
signal branch_ce : STD_LOGIC;
|
||||
signal ctrl_lines : ctrl_lines_t;
|
||||
signal cpu_run : STD_LOGIC;
|
||||
signal branch_ce : STD_LOGIC;
|
||||
signal run_en : STD_LOGIC;
|
||||
signal mul_dep : STD_LOGIC;
|
||||
signal imem_dep : STD_LOGIC;
|
||||
signal dmem_dep : STD_LOGIC;
|
||||
signal cop_ctrl : cop_ctrl_in_t;
|
||||
signal cop_stat : cop_ctrl_out_t;
|
||||
signal cop_din : word_t;
|
||||
signal cop_dout : word_t;
|
||||
signal alu_result : word_t;
|
||||
signal mul_result : word_t;
|
||||
signal mul_busy : STD_LOGIC;
|
||||
@@ -167,10 +200,12 @@ architecture Behavioral of pipeline is
|
||||
signal bcu_op_b : word_t;
|
||||
signal bcu_flags : bcu_flags_t;
|
||||
signal vaddr : word_t;
|
||||
signal dmem_src : word_t;
|
||||
signal stage_rst : unsigned(3 downto 0);
|
||||
signal pipe_rst : STD_LOGIC;
|
||||
|
||||
attribute ram_style : string;
|
||||
|
||||
attribute ram_style of reg_a: signal is "distributed";
|
||||
attribute ram_style of reg_b: signal is "distributed";
|
||||
|
||||
signal pc : pc_t;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
@@ -178,49 +213,32 @@ begin
|
||||
|
||||
clk_1 <= clk;
|
||||
clk_2 <= not clk;
|
||||
cpu_run <= ce;
|
||||
cpu_run <= run_en;
|
||||
|
||||
-- Stall Detection Unit ---------------------------------------------------
|
||||
sdu.ID_nop <= sdu.imem_dep or c0_ctrl_in.exc_pending or ID_stage.exc or EX_stage.exc or MEM_stage.exc;
|
||||
sdu.EX_nop <= sdu.mul_dep or ID_stage.nop or ID_stage.exc;
|
||||
sdu.ID_nop <= imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc;
|
||||
sdu.EX_nop <= mul_dep or ID_stage.nop or ID_stage.exc;
|
||||
sdu.MEM_nop <= EX_stage.nop or EX_stage.exc;
|
||||
sdu.WB_nop <= sdu.dmem_dep or MEM_stage.nop;
|
||||
sdu.WB_nop <= dmem_dep or MEM_stage.nop;
|
||||
|
||||
sdu.stall_all <= sdu.dmem_dep;
|
||||
sdu.ID_stall <= sdu.stall_all or sdu.imem_dep or sdu.mul_dep or c0_ctrl_in.exc_exit;
|
||||
sdu.EX_stall <= sdu.stall_all;
|
||||
sdu.MEM_stall <= sdu.stall_all;
|
||||
sdu.ID_stall <= dmem_dep or imem_dep or mul_dep or ID_stage.exc;
|
||||
sdu.EX_stall <= dmem_dep;
|
||||
sdu.MEM_stall <= dmem_dep;
|
||||
sdu.WB_stall <= '0';
|
||||
|
||||
sdu.mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
|
||||
sdu.imem_dep <= not imem_rdy;
|
||||
sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en;
|
||||
mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
|
||||
imem_dep <= not imem_rdy;
|
||||
dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en;
|
||||
---------------------------------------------------------------------------
|
||||
imem_en <= cpu_run and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Coprocessor assignments
|
||||
--------------------------------------------------------------------------
|
||||
c0_ctrl_out.bd_wb <= WB_stage.bd;
|
||||
c0_ctrl_out.epc_mem <= MEM_stage.pcn;
|
||||
c0_ctrl_out.epc_wb <= MEM_stage.epc;
|
||||
c0_ctrl_out.imem_addr <= EX_stage.epc;
|
||||
c0_ctrl_out.dmem_addr <= MEM_stage.va;
|
||||
c0_ctrl_out.sdu <= sdu;
|
||||
c0_ctrl_out.events <= WB_stage.events;
|
||||
c0_ctrl_out.exc_req <= MEM_stage.exc;
|
||||
c0_ctrl_out.exc_ack <= WB_stage.exc;
|
||||
cop_ir <= ID_stage.IR;
|
||||
cop_ir_en <= ID_stage.ctrl.cop_instr_en;
|
||||
cop_dout <= dmem_din when MEM_stage.ctrl.dmem_en = '1' else MEM_stage.ex_result;
|
||||
|
||||
imem_en <= cpu_run and not (mul_dep or dmem_dep or cop_stat.exc_commit);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Muldiv
|
||||
--------------------------------------------------------------------------
|
||||
inst_muldiv: muldiv
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
rst => cpu_rst,
|
||||
clk => clk,
|
||||
hilo_we => EX_stage.ctrl.mul_hilo_we,
|
||||
din_hi => EX_stage.reg_a,
|
||||
@@ -233,32 +251,46 @@ inst_muldiv: muldiv
|
||||
dout => mul_result
|
||||
);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Coprocessor
|
||||
--------------------------------------------------------------------------
|
||||
inst_cop: cop
|
||||
PORT MAP
|
||||
(
|
||||
rst => cpu_rst,
|
||||
clk => clk,
|
||||
sdu => sdu,
|
||||
events => MEM_stage.events,
|
||||
IR_valid => ID_stage.ctrl.cop_instr_en,
|
||||
IR => ID_stage.IR,
|
||||
ctrl_in => cop_ctrl,
|
||||
ctrl_out => cop_stat,
|
||||
dout => cop_dout,
|
||||
din => cop_din
|
||||
);
|
||||
|
||||
cop_ctrl.bd_wb <= WB_stage.bd;
|
||||
cop_ctrl.epc_mem <= MEM_stage.pcn;
|
||||
cop_ctrl.epc_wb <= MEM_stage.epc;
|
||||
cop_ctrl.imem_addr <= pc.nxt;
|
||||
cop_ctrl.dmem_addr <= MEM_stage.va;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- IF stage
|
||||
--------------------------------------------------------------------------
|
||||
imem_addr <= pc.curr;
|
||||
|
||||
pipe_rst <= stage_rst(0);
|
||||
|
||||
proc_stage_reset:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if rst = '1' then
|
||||
stage_rst <= (others => '1');
|
||||
else
|
||||
stage_rst <= stage_rst(stage_rst'left-1 downto 0) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_pc:
|
||||
process(pc)
|
||||
process(pc, rst, cop_stat)
|
||||
begin
|
||||
if pc.branch_take = '1' then
|
||||
pc.curr <= pc.pc_branch after 2 ns;
|
||||
if rst = '1' then
|
||||
pc.curr <= RESET_VECTOR after 2 ns;
|
||||
else
|
||||
pc.curr <= pc.nxt after 2 ns;
|
||||
if pc.is_branch and cop_stat.exc_pending = '0' then
|
||||
pc.curr <= pc.pc_branch after 2 ns;
|
||||
else
|
||||
pc.curr <= pc.nxt after 2 ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
@@ -272,35 +304,29 @@ proc_stage_pc_branch:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_branch_ce:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if pipe_rst = '1' then
|
||||
branch_ce <= '1';
|
||||
else
|
||||
branch_ce <= c0_ctrl_in.exc_pending;
|
||||
if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then
|
||||
branch_ce <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_stage_pc_next:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if c0_ctrl_in.exc_inject = '1' then
|
||||
pc.nxt <= c0_ctrl_in.exc_vec;
|
||||
elsif sdu.ID_stall = '0' then
|
||||
branch_ce <= '0';
|
||||
cop_ctrl.exc_left <= '0';
|
||||
if rst = '1' then
|
||||
pc.nxt <= pc.curr;
|
||||
pc.last <= pc.curr;
|
||||
if ID_stage.ctrl.jump = '1' then
|
||||
pc.nxt <= ID_stage.jimm32;
|
||||
elsif ID_stage.ctrl.jump_long = '1' then
|
||||
pc.nxt <= ID_stage.reg_a;
|
||||
else
|
||||
pc.nxt <= pc.curr + 4;
|
||||
else
|
||||
if cop_stat.exc_commit = '1' then
|
||||
pc.nxt <= cop_stat.exc_vec;
|
||||
elsif sdu.ID_stall = '0' then
|
||||
cop_ctrl.exc_left <= cop_stat.exc_exit;
|
||||
branch_ce <= '1';
|
||||
pc.last <= pc.curr;
|
||||
if ID_stage.ctrl.jump = '1' then
|
||||
pc.nxt <= ID_stage.jimm32;
|
||||
elsif ID_stage.ctrl.jump_long = '1' then
|
||||
pc.nxt <= ID_stage.reg_a;
|
||||
else
|
||||
pc.nxt <= pc.curr + 4;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
@@ -310,19 +336,25 @@ proc_stage_branch:
|
||||
process(clk_2)
|
||||
begin
|
||||
if rising_edge(clk_2) and branch_ce = '1' then
|
||||
pc.branch_take <= '0';
|
||||
pc.is_branch <= false;
|
||||
if EX_stage.ctrl.branch = '1' then
|
||||
|
||||
case EX_stage.ctrl.bc_src is
|
||||
|
||||
when bc_eq_ne =>
|
||||
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
|
||||
if (EX_stage.ctrl.bc_not xor bcu_flags.eq) = '1' then
|
||||
pc.is_branch <= true;
|
||||
end if;
|
||||
|
||||
when bc_lez_gtz =>
|
||||
pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
|
||||
if (EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz)) = '1' then
|
||||
pc.is_branch <= true;
|
||||
end if;
|
||||
|
||||
when bc_ltz_gez =>
|
||||
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
|
||||
if (EX_stage.ctrl.bc_not xor bcu_flags.ltz) = '1' then
|
||||
pc.is_branch <= true;
|
||||
end if;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
@@ -330,6 +362,25 @@ proc_stage_branch:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(rst, clk_1)
|
||||
variable reset_delay : unsigned (5 downto 0);
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if rst = '1' then
|
||||
reset_delay := (others => '1');
|
||||
cpu_rst <= '1';
|
||||
run_en <= '0';
|
||||
elsif reset_delay /= (5 downto 0 => '0') then
|
||||
reset_delay := reset_delay - 1;
|
||||
else
|
||||
cpu_rst <= '0';
|
||||
end if;
|
||||
if reset_delay(reset_delay'left-1) = '0' then
|
||||
run_en <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ID stage
|
||||
--------------------------------------------------------------------------
|
||||
@@ -341,18 +392,18 @@ proc_stage_branch:
|
||||
ID_stage.shamt <= extract_shamt(ID_stage.IR);
|
||||
ID_stage.reg_a_rptr <= extract_rs(ID_stage.IR);
|
||||
ID_stage.reg_b_rptr <= extract_rt(ID_stage.IR);
|
||||
ID_stage.ctrl <= opcode_ctrl_lines(ID_stage.IR) when sdu.ID_nop = '0' else ctrl_lines_default;
|
||||
ID_stage.reg_write <= ID_stage.ctrl.reg_write;
|
||||
ID_stage.ctrl <= ctrl_lines;
|
||||
ID_stage.reg_write <= ID_stage.ctrl.reg_write or cop_stat.reg_write;
|
||||
ID_stage.epc <= pc.last;
|
||||
ID_stage.exc <= event_is_active(ID_stage.events); -- Todo: works
|
||||
ID_stage.nop <= sdu.ID_nop;
|
||||
|
||||
proc_ID_except:
|
||||
process(ID_stage, c0_ctrl_in, pc)
|
||||
process(ID_stage, cop_stat, pc)
|
||||
begin
|
||||
ID_stage.events <= events_clr;
|
||||
ID_stage.events.inst_load_err <= not c0_ctrl_in.exc_pending and (pc.nxt(1) or pc.nxt(0));
|
||||
ID_stage.events.inst_priv_addr <= not c0_ctrl_in.exc_pending and (pc.nxt(word_t'left) and c0_ctrl_in.user_mode);
|
||||
ID_stage.events.inst_load_err <= pc.nxt(1) or pc.nxt(0);
|
||||
ID_stage.events.inst_priv_addr <= pc.nxt(word_t'left) and cop_stat.user_mode;
|
||||
end process;
|
||||
|
||||
proc_stage_hdu:
|
||||
@@ -438,6 +489,14 @@ proc_imm_mux:
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
inst_idecode_rom: idecode_rom
|
||||
PORT MAP
|
||||
(
|
||||
nop => sdu.ID_nop,
|
||||
inst_in => ID_stage.IR,
|
||||
ctrl_out => ctrl_lines
|
||||
);
|
||||
|
||||
inst_reg_dual: reg_dual
|
||||
GENERIC MAP
|
||||
(
|
||||
@@ -468,7 +527,7 @@ proc_stage_ID_EX_1:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if stage_rst(1) = '1' then
|
||||
if rst = '1' then
|
||||
EX_stage.op <= NOP;
|
||||
EX_stage.IR <= (others => '0');
|
||||
EX_stage.ctrl <= ctrl_lines_default;
|
||||
@@ -486,12 +545,13 @@ proc_stage_ID_EX_1:
|
||||
EX_stage.nop <= sdu.EX_nop;
|
||||
EX_stage.IR <= ID_stage.IR;
|
||||
EX_stage.pcn <= ID_stage.pcn;
|
||||
EX_stage.epc <= ID_stage.epc;
|
||||
if sdu.EX_nop = '1' then
|
||||
EX_stage.op <= NOP;
|
||||
EX_stage.IR <= (others => '0');
|
||||
EX_stage.ctrl <= ctrl_lines_default;
|
||||
EX_stage.reg_write <= '0';
|
||||
else
|
||||
EX_stage.epc <= ID_stage.epc;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
@@ -526,7 +586,7 @@ proc_stage_EX_mem_except:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if pipe_rst = '1' then
|
||||
if rst = '1' then
|
||||
dmem_en <= '0';
|
||||
elsif sdu.EX_stall = '0' then
|
||||
EX_events_mem <= events_clr;
|
||||
@@ -557,23 +617,19 @@ proc_stage_DMEM_ADDR:
|
||||
if rising_edge(clk_1) then
|
||||
if sdu.EX_stall = '0' then
|
||||
EX_stage.va <= vaddr;
|
||||
if c0_ctrl_in.EB = '1' then
|
||||
if ID_stage.ctrl.word2_en = '0' then
|
||||
EX_stage.pa_off <= not vaddr(1 downto 0);
|
||||
else
|
||||
EX_stage.pa_off <= not vaddr(1) & vaddr(0);
|
||||
end if;
|
||||
if cop_stat.RE = '1' then
|
||||
EX_stage.pa_off <= not vaddr(1 downto 0);
|
||||
else
|
||||
EX_stage.pa_off <= vaddr(1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dmem_src <= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b;
|
||||
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns;
|
||||
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
|
||||
dmem_we <= EX_stage.ctrl.dmem_we;
|
||||
dmem_dout <= store_shift(dmem_src, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
|
||||
dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
|
||||
dmem_addr <= EX_stage.va;
|
||||
cop_din <= EX_stage.reg_b;
|
||||
EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
|
||||
EX_stage.exc <= event_is_active(EX_stage.events);
|
||||
|
||||
@@ -727,7 +783,7 @@ proc_stage_MEM_n:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if stage_rst(2) = '1' then
|
||||
if rst = '1' then
|
||||
MEM_stage.op <= NOP;
|
||||
MEM_stage.wreg_we <= '0';
|
||||
MEM_stage.ctrl <= ctrl_lines_default;
|
||||
@@ -738,25 +794,17 @@ proc_stage_MEM_n:
|
||||
MEM_stage.op <= EX_stage.op;
|
||||
MEM_stage.wreg_we <= EX_stage.wreg_we;
|
||||
MEM_stage.ctrl <= EX_stage.ctrl;
|
||||
if EX_stage.ctrl.dmem_en = '1' then
|
||||
MEM_stage.va <= EX_stage.va;
|
||||
end if;
|
||||
MEM_stage.va <= EX_stage.va;
|
||||
MEM_stage.pa_off <= EX_stage.pa_off;
|
||||
MEM_stage.reg_wptr <= EX_stage.reg_wptr;
|
||||
MEM_stage.nop <= sdu.MEM_nop;
|
||||
if MEM_stage.reg_wptr = EX_stage.reg_wptr then
|
||||
if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then
|
||||
MEM_stage.ex_result <= MEM_stage.data;
|
||||
end if;
|
||||
else
|
||||
if EX_stage.ctrl.dmem_en = '1' then
|
||||
MEM_stage.ex_result <= EX_stage.reg_b;
|
||||
end if;
|
||||
if EX_stage.ctrl.cop_instr_en = '1' then
|
||||
if EX_stage.ctrl.cop_read = '1' then
|
||||
MEM_stage.ex_result <= cop_din;
|
||||
end if;
|
||||
elsif EX_stage.ctrl.dmem_en = '0' then
|
||||
else
|
||||
MEM_stage.ex_result <= EX_stage.result;
|
||||
if cop_stat.cop_read = '1' then
|
||||
MEM_stage.ex_result <= cop_dout;
|
||||
end if;
|
||||
end if;
|
||||
if sdu.MEM_nop = '1' then
|
||||
MEM_stage.op <= NOP;
|
||||
@@ -778,12 +826,12 @@ proc_stage_MEM_mux:
|
||||
variable be : unsigned(3 downto 0);
|
||||
begin
|
||||
data := MEM_stage.ex_result;
|
||||
be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
|
||||
if MEM_stage.ctrl.reg_link = '1' then
|
||||
data := MEM_stage.epc + 8;
|
||||
data := MEM_stage.pcn + 4;
|
||||
elsif MEM_stage.ctrl.dmem_en = '1' then
|
||||
temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
|
||||
temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
|
||||
be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
|
||||
if be(0) = '1' then
|
||||
data(7 downto 0) := temp2(7 downto 0);
|
||||
end if;
|
||||
@@ -802,14 +850,13 @@ proc_stage_MEM_mux:
|
||||
end process;
|
||||
|
||||
proc_stage_MEM_except:
|
||||
process(MEM_stage, c0_ctrl_in)
|
||||
process(MEM_stage, int)
|
||||
begin
|
||||
MEM_stage.events <= MEM_stage.events_in;
|
||||
MEM_stage.events.Int <= c0_ctrl_in.int;
|
||||
MEM_stage.events.NMI <= c0_ctrl_in.NMI;
|
||||
MEM_stage.events.Int <= int;
|
||||
end process;
|
||||
|
||||
MEM_stage.exc <= event_is_active(MEM_stage.events);
|
||||
MEM_stage.exc <= cop_stat.int or event_is_active(MEM_stage.events_in);
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- WB stage
|
||||
@@ -818,29 +865,20 @@ proc_stage_WB_p:
|
||||
process(clk_1)
|
||||
begin
|
||||
if rising_edge(clk_1) then
|
||||
if stage_rst(3) = '1' then
|
||||
if rst = '1' then
|
||||
WB_stage.op <= NOP;
|
||||
WB_stage.wreg_we <= '1';
|
||||
WB_stage.reg_wptr <= (others => '0');
|
||||
WB_stage.data <= (others => '0');
|
||||
WB_stage.events <= events_clr;
|
||||
WB_stage.wreg_we <= '0';
|
||||
elsif sdu.WB_stall = '0' then
|
||||
WB_stage.op <= MEM_stage.op;
|
||||
WB_stage.wreg_we <= MEM_stage.wreg_we;
|
||||
WB_stage.reg_wptr <= MEM_stage.reg_wptr;
|
||||
WB_stage.data <= MEM_stage.data;
|
||||
WB_stage.exc <= '0';
|
||||
if sdu.stall_all = '0' then
|
||||
WB_stage.exc <= MEM_stage.exc;
|
||||
if MEM_stage.exc = '1' then
|
||||
WB_stage.events <= MEM_stage.events;
|
||||
end if;
|
||||
end if;
|
||||
WB_stage.nop <= sdu.WB_nop;
|
||||
if sdu.WB_nop = '1' then
|
||||
WB_stage.op <= NOP;
|
||||
WB_stage.wreg_we <= '0';
|
||||
else
|
||||
WB_stage.epc <= MEM_stage.epc;
|
||||
WB_stage.bd <= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works
|
||||
end if;
|
||||
end if;
|
||||
|
||||
@@ -51,7 +51,16 @@ architecture Behavioral of reg_dual is
|
||||
constant depth : integer := 2**addr_width;
|
||||
type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
|
||||
signal reg_mem : mem_t;
|
||||
function mem_clear(depth : natural) return mem_t is
|
||||
variable result : mem_t;
|
||||
begin
|
||||
for i in 0 to depth-1 loop
|
||||
result(i) := (others => '0');
|
||||
end loop;
|
||||
return result;
|
||||
end mem_clear;
|
||||
|
||||
signal reg_mem : mem_t := mem_clear(depth);
|
||||
|
||||
begin
|
||||
|
||||
|
||||
@@ -49,23 +49,7 @@ architecture Behavioral of shifter is
|
||||
signal sa_rnd : unsigned (4 downto 0);
|
||||
signal fill : std_logic;
|
||||
|
||||
type fill_mask_rom_t is array (0 to 2*data_width-1) of unsigned(data_width-1 downto 0);
|
||||
--------------------------------------------------------------------------
|
||||
function gen_fill_mask_rom(data_width : natural) return fill_mask_rom_t is
|
||||
variable result : fill_mask_rom_t;
|
||||
begin
|
||||
result(0) := (data_width-1 downto 0 => '0');
|
||||
for i in 1 to data_width-1 loop
|
||||
result(i) := (data_width-1-i downto 0 => '0') & (i-1 downto 0 => '1');
|
||||
end loop;
|
||||
result(data_width) := (data_width-1 downto 0 => '0');
|
||||
for i in 1 to data_width-1 loop
|
||||
result(data_width+i) := (i-1 downto 0 => '1') & (data_width-1-i downto 0 => '0');
|
||||
end loop;
|
||||
return result;
|
||||
|
||||
end gen_fill_mask_rom;
|
||||
|
||||
function rot_stage(x : unsigned; en : std_logic; stage_num : natural) return unsigned is
|
||||
variable result : unsigned(x'range);
|
||||
constant sa : natural := 2**stage_num;
|
||||
@@ -79,39 +63,52 @@ function rot_stage(x : unsigned; en : std_logic; stage_num : natural) return uns
|
||||
|
||||
end rot_stage;
|
||||
|
||||
constant fill_mask_rom : fill_mask_rom_t := gen_fill_mask_rom(data_width);
|
||||
signal fill_mask : unsigned(data_width-1 downto 0);
|
||||
signal fill_mask_addr : unsigned(5 downto 0);
|
||||
signal dout_filled : unsigned (data_width-1 downto 0);
|
||||
function rot_fill(x : unsigned; fill : std_logic; shift_right : std_logic; sa : natural) return unsigned is
|
||||
variable result : unsigned(x'range) := (others => '0');
|
||||
variable j : integer;
|
||||
begin
|
||||
|
||||
if shift_right = '0' then
|
||||
for i in 0 to x'left loop
|
||||
if i >= sa then
|
||||
result(i) := x(i);
|
||||
else
|
||||
result(i) := fill;
|
||||
end if;
|
||||
end loop;
|
||||
else
|
||||
j := x'left;
|
||||
for i in 0 to x'left loop
|
||||
if i < sa then
|
||||
result(j) := fill;
|
||||
else
|
||||
result(j) := x(j);
|
||||
end if;
|
||||
j := j - 1;
|
||||
end loop;
|
||||
end if;
|
||||
return result;
|
||||
|
||||
end rot_fill;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
rot_data(0) <= din;
|
||||
|
||||
rot_data(0) <= din;
|
||||
|
||||
gen_rotate_right:
|
||||
for stage in 0 to 4 generate
|
||||
begin
|
||||
rot_data(stage+1) <= rot_stage(rot_data(stage), sa_rnd(stage), stage);
|
||||
end generate;
|
||||
|
||||
sa_rnd <= shift_ctrl.shamt_rnd;
|
||||
fill <= shift_ctrl.shift_arith and din(data_width-1);
|
||||
fill_mask_addr <= shift_ctrl.shift_right & shift_ctrl.shamt_nrm;
|
||||
fill_mask <= fill_mask_rom(to_integer(fill_mask_addr));
|
||||
sa_rnd <= shift_ctrl.shamt_rnd;
|
||||
fill <= shift_ctrl.shift_arith and din(data_width-1);
|
||||
dout <= rot_fill(rot_data(5), fill, shift_ctrl.shift_right, to_integer(shift_ctrl.shamt_nrm)) after 5 ns;
|
||||
-- dout <= rot_data(5);
|
||||
|
||||
|
||||
|
||||
proc_fill_neu:
|
||||
process(fill_mask, fill, rot_data(5))
|
||||
begin
|
||||
if fill = '1' then
|
||||
dout_filled <= rot_data(5) or fill_mask;
|
||||
else
|
||||
dout_filled <= rot_data(5) and not fill_mask;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dout <= dout_filled after 5 ns;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end Behavioral;
|
||||
|
||||
|
||||
@@ -29,26 +29,16 @@ library work;
|
||||
use work.mips_types.all;
|
||||
|
||||
entity mips_top is
|
||||
Generic
|
||||
(
|
||||
icache_size : natural := 8192; -- words
|
||||
icache_line : natural := 8; -- words
|
||||
dcache_size : natural := 4096; -- words
|
||||
dcache_line : natural := 8 -- words
|
||||
);
|
||||
Port
|
||||
(
|
||||
debug : out unsigned(1 downto 0);
|
||||
eb : in STD_LOGIC;
|
||||
nmi : in STD_LOGIC;
|
||||
cpu_clk : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
DAT_O : out word_t;
|
||||
WE_O : out STD_LOGIC;
|
||||
SEL_O : out unsigned(3 downto 0);
|
||||
CYC_O : out STD_LOGIC;
|
||||
@@ -61,15 +51,13 @@ end mips_top;
|
||||
|
||||
architecture rtl of mips_top is
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Pipeline
|
||||
--------------------------------------------------------------------------
|
||||
COMPONENT pipeline is
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
halt : in STD_LOGIC;
|
||||
int : in unsigned (5 downto 0);
|
||||
imem_err : in STD_LOGIC;
|
||||
imem_rdy : in STD_LOGIC;
|
||||
imem_en : out STD_LOGIC;
|
||||
@@ -82,13 +70,7 @@ architecture rtl of mips_top is
|
||||
dmem_be : out unsigned(3 downto 0);
|
||||
dmem_addr : out word_t;
|
||||
dmem_din : in word_t;
|
||||
dmem_dout : out word_t;
|
||||
cop_ir : out word_t;
|
||||
cop_ir_en : out STD_LOGIC;
|
||||
cop_din : in word_t;
|
||||
cop_dout : out word_t;
|
||||
c0_ctrl_out : out cop0_ctrl_in_t;
|
||||
c0_ctrl_in : in cop0_ctrl_out_t
|
||||
dmem_dout : out word_t
|
||||
);
|
||||
END COMPONENT;
|
||||
signal imem_err : std_logic;
|
||||
@@ -105,54 +87,12 @@ architecture rtl of mips_top is
|
||||
signal dmem_din : word_t;
|
||||
signal dmem_be : unsigned(3 downto 0);
|
||||
|
||||
signal biu_rst : STD_LOGIC;
|
||||
signal cpu_rst : STD_LOGIC;
|
||||
signal cpu_run : STD_LOGIC;
|
||||
|
||||
signal pipe_cop_ir : word_t;
|
||||
signal pipe_cop_ir_en : STD_LOGIC;
|
||||
signal pipe_cop_din : word_t;
|
||||
signal pipe_cop_dout : word_t;
|
||||
signal pipe_c0_ctrl_out : cop0_ctrl_in_t;
|
||||
signal pipe_c0_ctrl_in : cop0_ctrl_out_t;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Coprocessor
|
||||
--------------------------------------------------------------------------
|
||||
COMPONENT cop is
|
||||
GENERIC
|
||||
(
|
||||
icache_size : natural;
|
||||
icache_line : natural;
|
||||
dcache_size : natural;
|
||||
dcache_line : natural
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
nmi : in STD_LOGIC;
|
||||
eb : in STD_LOGIC;
|
||||
int : in unsigned (5 downto 0);
|
||||
ir_en : in STD_LOGIC;
|
||||
ir : in word_t;
|
||||
ctrl_in : in cop0_ctrl_in_t;
|
||||
ctrl_out : out cop0_ctrl_out_t;
|
||||
din : in word_t;
|
||||
dout : out word_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Bus Interface Unit
|
||||
--------------------------------------------------------------------------
|
||||
COMPONENT biu
|
||||
GENERIC
|
||||
(
|
||||
icache_size : natural;
|
||||
icache_line : natural;
|
||||
dcache_size : natural;
|
||||
dcache_line : natural
|
||||
dcache_size : natural
|
||||
);
|
||||
PORT
|
||||
(
|
||||
@@ -160,16 +100,14 @@ architecture rtl of mips_top is
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
DAT_O : out word_t;
|
||||
WE_O : out STD_LOGIC;
|
||||
SEL_O : out unsigned(3 downto 0);
|
||||
CYC_O : out STD_LOGIC;
|
||||
STB_O : out STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
cop0_ctrl_in : in cop0_ctrl_out_t;
|
||||
cpu_clk : in STD_LOGIC;
|
||||
cpu_imem_err : out STD_LOGIC;
|
||||
cpu_imem_rdy : out STD_LOGIC;
|
||||
cpu_imem_en : in STD_LOGIC;
|
||||
@@ -192,36 +130,13 @@ begin
|
||||
debug(0) <= imem_err;
|
||||
debug(1) <= dmem_err;
|
||||
|
||||
process(CLK_I)
|
||||
variable reset_delay : unsigned (31 downto 0);
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
reset_delay := (others => '0');
|
||||
biu_rst <= '1';
|
||||
cpu_rst <= '1';
|
||||
cpu_run <= '0';
|
||||
else
|
||||
reset_delay := reset_delay(reset_delay'left-1 downto 0) & '1';
|
||||
if reset_delay(20) = '1' then
|
||||
biu_rst <= '0';
|
||||
end if;
|
||||
if reset_delay(31) = '1' then
|
||||
cpu_rst <= '0';
|
||||
end if;
|
||||
if reset_delay(16) = '1' then
|
||||
cpu_run <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_pipeline: pipeline
|
||||
PORT MAP
|
||||
(
|
||||
rst => cpu_rst,
|
||||
clk => cpu_clk,
|
||||
ce => cpu_run,
|
||||
rst => RST_I,
|
||||
clk => CLK_I,
|
||||
halt => '0',
|
||||
int => INT,
|
||||
imem_err => imem_err,
|
||||
imem_rdy => imem_rdy,
|
||||
imem_en => imem_en,
|
||||
@@ -234,49 +149,18 @@ inst_pipeline: pipeline
|
||||
dmem_be => dmem_be,
|
||||
dmem_addr => dmem_addr,
|
||||
dmem_din => dmem_din,
|
||||
dmem_dout => dmem_dout,
|
||||
cop_ir => pipe_cop_ir,
|
||||
cop_ir_en => pipe_cop_ir_en,
|
||||
cop_din => pipe_cop_din,
|
||||
cop_dout => pipe_cop_dout,
|
||||
c0_ctrl_out => pipe_c0_ctrl_out,
|
||||
c0_ctrl_in => pipe_c0_ctrl_in
|
||||
dmem_dout => dmem_dout
|
||||
);
|
||||
|
||||
inst_cop: cop
|
||||
GENERIC MAP
|
||||
(
|
||||
icache_size => icache_size, -- words
|
||||
icache_line => icache_line, -- words
|
||||
dcache_size => dcache_size, -- words
|
||||
dcache_line => dcache_line -- words
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => cpu_rst,
|
||||
clk => cpu_clk,
|
||||
nmi => nmi,
|
||||
eb => eb,
|
||||
int => INT,
|
||||
ir_en => pipe_cop_ir_en,
|
||||
ir => pipe_cop_ir,
|
||||
ctrl_in => pipe_c0_ctrl_out,
|
||||
ctrl_out => pipe_c0_ctrl_in,
|
||||
dout => pipe_cop_din,
|
||||
din => pipe_cop_dout
|
||||
);
|
||||
|
||||
inst_biu: biu
|
||||
GENERIC MAP
|
||||
(
|
||||
icache_size => icache_size, -- words
|
||||
icache_line => icache_line, -- words
|
||||
dcache_size => dcache_size, -- words
|
||||
dcache_line => dcache_line -- words
|
||||
icache_size => 4096, -- words
|
||||
dcache_size => 4096 -- words
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
RST_I => biu_rst,
|
||||
RST_I => RST_I,
|
||||
CLK_I => CLK_I,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
@@ -288,8 +172,6 @@ inst_biu: biu
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
MRDY_O => MRDY_O,
|
||||
cop0_ctrl_in => pipe_c0_ctrl_in,
|
||||
cpu_clk => cpu_clk,
|
||||
cpu_imem_err => imem_err,
|
||||
cpu_imem_rdy => imem_rdy,
|
||||
cpu_imem_en => imem_en,
|
||||
|
||||
@@ -23,14 +23,14 @@
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
package mips_types is
|
||||
|
||||
-- Revision of the CPU
|
||||
constant REVISION : integer := 13;
|
||||
constant REVISION : integer := 9;
|
||||
constant WORD_WIDTH : integer := 32;
|
||||
|
||||
--Types
|
||||
@@ -43,9 +43,10 @@ package mips_types is
|
||||
subtype sa_t is natural range 0 to 63;
|
||||
subtype func_t is unsigned(5 downto 0);
|
||||
|
||||
type opclass_t is (special, regimm, opcode);
|
||||
|
||||
type op_t is
|
||||
(
|
||||
reserved,
|
||||
nop,
|
||||
op_sll,
|
||||
op_srl,
|
||||
@@ -109,35 +110,9 @@ package mips_types is
|
||||
op_cop1,
|
||||
op_cop2,
|
||||
op_cop3,
|
||||
op_mfc0,
|
||||
op_cfc0,
|
||||
op_mtc0,
|
||||
op_ctc0,
|
||||
op_bcf0,
|
||||
op_bct0,
|
||||
op_mfc1,
|
||||
op_cfc1,
|
||||
op_mtc1,
|
||||
op_ctc1,
|
||||
op_bcf1,
|
||||
op_bct1,
|
||||
op_mfc2,
|
||||
op_cfc2,
|
||||
op_mtc2,
|
||||
op_ctc2,
|
||||
op_bcf2,
|
||||
op_bct2,
|
||||
op_mfc3,
|
||||
op_cfc3,
|
||||
op_mtc3,
|
||||
op_ctc3,
|
||||
op_bcf3,
|
||||
op_bct3,
|
||||
op_lwc0,
|
||||
op_lwc1,
|
||||
op_lwc2,
|
||||
op_lwc3,
|
||||
op_swc0,
|
||||
op_swc1,
|
||||
op_swc2,
|
||||
op_swc3
|
||||
@@ -160,7 +135,7 @@ package mips_types is
|
||||
last : word_t;
|
||||
nxt : word_t;
|
||||
pc_branch : word_t;
|
||||
branch_take : std_logic;
|
||||
is_branch : boolean;
|
||||
end record;
|
||||
|
||||
type alu_outsel_t is
|
||||
@@ -175,30 +150,6 @@ package mips_types is
|
||||
alu_lts
|
||||
);
|
||||
|
||||
type sdu_t is record
|
||||
imem_dep : STD_LOGIC;
|
||||
dmem_dep : STD_LOGIC;
|
||||
mul_dep : STD_LOGIC;
|
||||
ID_nop : STD_LOGIC;
|
||||
EX_nop : STD_LOGIC;
|
||||
MEM_nop : STD_LOGIC;
|
||||
WB_nop : STD_LOGIC;
|
||||
ID_stall : STD_LOGIC;
|
||||
EX_stall : STD_LOGIC;
|
||||
MEM_stall : STD_LOGIC;
|
||||
WB_stall : STD_LOGIC;
|
||||
stall_all : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type hdu_t is record
|
||||
alu_fwd_a_ex : boolean;
|
||||
alu_fwd_a_mem : boolean;
|
||||
alu_fwd_a_wb : boolean;
|
||||
alu_fwd_b_ex : boolean;
|
||||
alu_fwd_b_mem : boolean;
|
||||
alu_fwd_b_wb : boolean;
|
||||
end record;
|
||||
|
||||
type alu_flags_t is record
|
||||
c : STD_LOGIC;
|
||||
uvf : STD_LOGIC;
|
||||
@@ -213,8 +164,7 @@ package mips_types is
|
||||
end record;
|
||||
|
||||
type event_t is record
|
||||
NMI : STD_LOGIC;
|
||||
Int : STD_LOGIC;
|
||||
Int : unsigned(5 downto 0);
|
||||
data_load_err : STD_LOGIC;
|
||||
data_store_err : STD_LOGIC;
|
||||
inst_load_err : STD_LOGIC;
|
||||
@@ -246,38 +196,49 @@ package mips_types is
|
||||
cause : word_t;
|
||||
end record;
|
||||
|
||||
type cache_ctrl_t is record
|
||||
inv_addr : word_t;
|
||||
inv_at : STD_LOGIC;
|
||||
inv_all : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type cop0_ctrl_in_t is record
|
||||
sdu : sdu_t;
|
||||
events : event_t;
|
||||
type cop_ctrl_in_t is record
|
||||
bd_wb : STD_LOGIC;
|
||||
epc_mem : word_t;
|
||||
epc_wb : word_t;
|
||||
imem_addr : word_t;
|
||||
dmem_addr : word_t;
|
||||
exc_req : STD_LOGIC;
|
||||
exc_ack : STD_LOGIC;
|
||||
exc_left : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type cop0_ctrl_out_t is record
|
||||
EB : STD_LOGIC;
|
||||
exc_inject : STD_LOGIC;
|
||||
type cop_ctrl_out_t is record
|
||||
RE : STD_LOGIC;
|
||||
ee : STD_LOGIC;
|
||||
ec : STD_LOGIC;
|
||||
exc_commit : STD_LOGIC;
|
||||
exc_pending : STD_LOGIC;
|
||||
exc_exit : STD_LOGIC;
|
||||
reg_write : STD_LOGIC;
|
||||
cop_read : STD_LOGIC;
|
||||
user_mode : STD_LOGIC;
|
||||
NMI : STD_LOGIC;
|
||||
int : STD_LOGIC;
|
||||
exc_vec : word_t;
|
||||
icache : cache_ctrl_t;
|
||||
dcache : cache_ctrl_t;
|
||||
end record;
|
||||
|
||||
type sdu_t is record
|
||||
ID_nop : STD_LOGIC;
|
||||
EX_nop : STD_LOGIC;
|
||||
MEM_nop : STD_LOGIC;
|
||||
WB_nop : STD_LOGIC;
|
||||
ID_stall : STD_LOGIC;
|
||||
EX_stall : STD_LOGIC;
|
||||
MEM_stall : STD_LOGIC;
|
||||
WB_stall : STD_LOGIC;
|
||||
end record;
|
||||
|
||||
type hdu_t is record
|
||||
alu_fwd_a_ex : boolean;
|
||||
alu_fwd_a_mem : boolean;
|
||||
alu_fwd_a_wb : boolean;
|
||||
alu_fwd_b_ex : boolean;
|
||||
alu_fwd_b_mem : boolean;
|
||||
alu_fwd_b_wb : boolean;
|
||||
end record;
|
||||
|
||||
type alu_ctrl_t is record
|
||||
outsel : alu_outsel_t;
|
||||
add : STD_LOGIC;
|
||||
@@ -309,7 +270,6 @@ package mips_types is
|
||||
shamt2_srcsel : sa_src_t;
|
||||
wptr_srcsel : wptr_src_t;
|
||||
cop_instr_en : STD_LOGIC;
|
||||
cop_read : STD_LOGIC;
|
||||
shift_offset : unsigned(1 downto 0);
|
||||
shift_byp : STD_LOGIC;
|
||||
byte_en_byp : STD_LOGIC;
|
||||
@@ -397,9 +357,8 @@ package mips_types is
|
||||
|
||||
type WB_t is record
|
||||
nop : STD_LOGIC;
|
||||
exc : std_logic;
|
||||
events : event_t;
|
||||
op : op_t;
|
||||
epc : word_t;
|
||||
reg_wptr : reg_ptr_t;
|
||||
wreg_we : STD_LOGIC;
|
||||
data : word_t;
|
||||
@@ -420,9 +379,6 @@ package mips_types is
|
||||
function event_is_active(e : event_t) return std_logic;
|
||||
function "or" (a, b : event_t) return event_t;
|
||||
|
||||
function lg2(x : natural) return natural;
|
||||
function po2(x : natural) return natural;
|
||||
|
||||
end mips_types;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
@@ -456,53 +412,56 @@ package body mips_types is
|
||||
function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned is
|
||||
variable result : unsigned(3 downto 0);
|
||||
begin
|
||||
result := (3 downto 0 => be_src);
|
||||
if bypass = '0' then
|
||||
if word2_en = '1' then
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "00" & be_src & be_src;
|
||||
when "10" =>
|
||||
result := be_src & be_src & "00";
|
||||
when others => null;
|
||||
end case;
|
||||
elsif word4_en = '1' then
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "000" & be_src;
|
||||
when "01" =>
|
||||
result := "00" & be_src & '0';
|
||||
when "10" =>
|
||||
result := '0' & be_src & "00";
|
||||
when "11" =>
|
||||
result := be_src & "000";
|
||||
when others => null;
|
||||
end case;
|
||||
elsif align_left = '1' then
|
||||
case va is
|
||||
when "00" =>
|
||||
result := be_src & be_src & be_src & be_src;
|
||||
when "01" =>
|
||||
result := be_src & be_src & be_src & '0';
|
||||
when "10" =>
|
||||
result := be_src & be_src & "00";
|
||||
when "11" =>
|
||||
result := be_src & "000";
|
||||
when others => null;
|
||||
end case;
|
||||
else
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "000" & be_src;
|
||||
when "01" =>
|
||||
result := "00" & be_src & be_src;
|
||||
when "10" =>
|
||||
result := '0' & be_src & be_src & be_src;
|
||||
when "11" =>
|
||||
result := be_src & be_src & be_src & be_src;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
if bypass = '1' then
|
||||
result := (3 downto 0 => be_src);
|
||||
elsif word2_en = '1' then
|
||||
case va is
|
||||
when "00" | "01" =>
|
||||
result := "00" & be_src & be_src;
|
||||
when "10" | "11" =>
|
||||
result := be_src & be_src & "00";
|
||||
when others =>
|
||||
result := "0000";
|
||||
end case;
|
||||
elsif word4_en = '1' then
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "000" & be_src;
|
||||
when "01" =>
|
||||
result := "00" & be_src & '0';
|
||||
when "10" =>
|
||||
result := '0' & be_src & "00";
|
||||
when "11" =>
|
||||
result := be_src & "000";
|
||||
when others =>
|
||||
result := "0000";
|
||||
end case;
|
||||
elsif align_left = '1' then
|
||||
case va is
|
||||
when "00" =>
|
||||
result := be_src & be_src & be_src & be_src;
|
||||
when "01" =>
|
||||
result := be_src & be_src & be_src & '0';
|
||||
when "10" =>
|
||||
result := be_src & be_src & "00";
|
||||
when "11" =>
|
||||
result := be_src & "000";
|
||||
when others =>
|
||||
result := "0000";
|
||||
end case;
|
||||
else
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "000" & be_src;
|
||||
when "01" =>
|
||||
result := "00" & be_src & be_src;
|
||||
when "10" =>
|
||||
result := '0' & be_src & be_src & be_src;
|
||||
when "11" =>
|
||||
result := be_src & be_src & be_src & be_src;
|
||||
when others =>
|
||||
result := "0000";
|
||||
end case;
|
||||
end if;
|
||||
|
||||
return result;
|
||||
@@ -538,33 +497,34 @@ package body mips_types is
|
||||
function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned is
|
||||
variable result : unsigned(3 downto 0);
|
||||
begin
|
||||
result := (3 downto 0 => '1');
|
||||
if bypass = '0' then
|
||||
if align_left = '1' then
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "1000";
|
||||
when "01" =>
|
||||
result := "1100";
|
||||
when "10" =>
|
||||
result := "1110";
|
||||
when "11" =>
|
||||
result := "1111";
|
||||
when others => null;
|
||||
end case;
|
||||
else
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "1111";
|
||||
when "01" =>
|
||||
result := "0111";
|
||||
when "10" =>
|
||||
result := "0011";
|
||||
when "11" =>
|
||||
result := "0001";
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
if bypass = '1' then
|
||||
result := (3 downto 0 => '1');
|
||||
elsif align_left = '1' then
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "1000";
|
||||
when "01" =>
|
||||
result := "1100";
|
||||
when "10" =>
|
||||
result := "1110";
|
||||
when "11" =>
|
||||
result := "1111";
|
||||
when others =>
|
||||
result := "0000";
|
||||
end case;
|
||||
else
|
||||
case va is
|
||||
when "00" =>
|
||||
result := "1111";
|
||||
when "01" =>
|
||||
result := "0111";
|
||||
when "10" =>
|
||||
result := "0011";
|
||||
when "11" =>
|
||||
result := "0001";
|
||||
when others =>
|
||||
result := "0000";
|
||||
end case;
|
||||
end if;
|
||||
|
||||
return result;
|
||||
@@ -594,8 +554,7 @@ package body mips_types is
|
||||
function events_clr return event_t is
|
||||
variable result : event_t;
|
||||
begin
|
||||
result.NMI := '0';
|
||||
result.Int := '0';
|
||||
result.Int := (others => '0');
|
||||
result.data_load_err := '0';
|
||||
result.data_store_err := '0';
|
||||
result.inst_load_err := '0';
|
||||
@@ -610,14 +569,15 @@ package body mips_types is
|
||||
|
||||
end events_clr;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function event_is_active(e : event_t) return std_logic is
|
||||
variable result : std_logic;
|
||||
begin
|
||||
result := '0';
|
||||
|
||||
result := result or e.NMI;
|
||||
result := result or e.Int;
|
||||
for i in e.Int'range loop
|
||||
result := result or e.Int(i);
|
||||
end loop;
|
||||
|
||||
result := result or e.data_load_err;
|
||||
result := result or e.data_store_err;
|
||||
result := result or e.inst_load_err;
|
||||
@@ -632,12 +592,12 @@ package body mips_types is
|
||||
|
||||
end event_is_active;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function "or" (a, b : event_t) return event_t is
|
||||
variable result : event_t;
|
||||
begin
|
||||
result.NMI := a.NMI or b.NMI;
|
||||
result.Int := a.Int or b.Int;
|
||||
for i in a.Int'range loop
|
||||
result.Int(i) := a.Int(i) or b.Int(i);
|
||||
end loop;
|
||||
result.data_load_err := a.data_load_err or b.data_load_err;
|
||||
result.data_store_err := a.data_store_err or b.data_store_err;
|
||||
result.inst_load_err := a.inst_load_err or b.inst_load_err;
|
||||
@@ -652,19 +612,8 @@ package body mips_types is
|
||||
|
||||
end "or";
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function lg2(x : natural) return natural is
|
||||
begin
|
||||
return natural(ceil(log2(real(x))));
|
||||
end lg2;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
function po2(x : natural) return natural is
|
||||
begin
|
||||
|
||||
return 2**lg2(x);
|
||||
end po2;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end mips_types;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,332 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: Testbench for JCPU
|
||||
-- also writes 'opc.lst' for JASM-assembler
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_instr.all;
|
||||
|
||||
ENTITY tb_mips_muldiv IS
|
||||
END tb_mips_muldiv;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mips_muldiv IS
|
||||
|
||||
COMPONENT muldiv is
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
hilo_we : in std_logic;
|
||||
din_hi : in word_t;
|
||||
din_lo : in word_t;
|
||||
mul_divn : in std_logic;
|
||||
s_un : in std_logic;
|
||||
start : in std_logic;
|
||||
hilo_sel : in std_logic;
|
||||
busy : out std_logic;
|
||||
dout : out word_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal ENABLE_FAIL_REPORT : boolean := true;
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '1';
|
||||
signal busy : std_logic;
|
||||
signal mul_divn : std_logic := '0';
|
||||
signal s_un : std_logic := '1';
|
||||
signal hilo_we : std_logic := '0';
|
||||
signal start : std_logic := '0';
|
||||
signal din_hi : word_t := (others => '-');
|
||||
signal din_lo : word_t := (others => '-');
|
||||
signal dout : word_t;
|
||||
signal hilo_sel : std_logic := '0';
|
||||
signal md_result : unsigned (2*word_t'length-1 downto 0) := (others => '0');
|
||||
signal ref_result : unsigned (2*word_t'length-1 downto 0);
|
||||
signal ref_hi : unsigned (word_t'length-1 downto 0);
|
||||
signal rtmp : unsigned (2*word_t'length-1 downto 0);
|
||||
signal tmp2 : unsigned (word_t'length-1 downto 0);
|
||||
signal check : std_logic;
|
||||
|
||||
type word_array_t is array (natural range <>) of word_t;
|
||||
|
||||
constant operands : word_array_t(0 to 63) :=
|
||||
(
|
||||
X"00000000",
|
||||
X"00000001",
|
||||
X"00000010",
|
||||
X"00000100",
|
||||
X"00001000",
|
||||
X"00010000",
|
||||
X"00100000",
|
||||
X"01000000",
|
||||
X"10000000",
|
||||
X"0000000F",
|
||||
X"000000FF",
|
||||
X"00000FFF",
|
||||
X"0000FFFF",
|
||||
X"000FFFFF",
|
||||
X"00FFFFFF",
|
||||
X"0FFFFFFF",
|
||||
X"12345678",
|
||||
X"23456789",
|
||||
X"7FFFFFFF",
|
||||
X"80000000",
|
||||
X"A541B3B9",
|
||||
X"80000001",
|
||||
X"80000010",
|
||||
X"80000100",
|
||||
X"80001000",
|
||||
X"80010000",
|
||||
X"80100000",
|
||||
X"81000000",
|
||||
X"87654321",
|
||||
X"98765432",
|
||||
X"FFFFFFFF",
|
||||
X"FFFFFFFE",
|
||||
X"FFFFFFFD",
|
||||
X"FFFFFFFB",
|
||||
X"FFFFFFF7",
|
||||
X"FFFFFFEF",
|
||||
X"FFFFFFDF",
|
||||
X"FFFFFFBF",
|
||||
X"FFFFFF7F",
|
||||
X"FFFFFEFF",
|
||||
X"FFFFFDFF",
|
||||
X"FFFFFBFF",
|
||||
X"FFFFF7FF",
|
||||
X"FFFFEFFF",
|
||||
X"FFFFDFFF",
|
||||
X"FFFFBFFF",
|
||||
X"FFFF7FFF",
|
||||
X"FFFEFFFF",
|
||||
X"FFFDFFFF",
|
||||
X"FFFBFFFF",
|
||||
X"FFF7FFFF",
|
||||
X"FFEFFFFF",
|
||||
X"FFDFFFFF",
|
||||
X"FFBFFFFF",
|
||||
X"FF7FFFFF",
|
||||
X"FEFFFFFF",
|
||||
X"FDFFFFFF",
|
||||
X"FBFFFFFF",
|
||||
X"F7FFFFFF",
|
||||
X"EFFFFFFF",
|
||||
X"DFFFFFFF",
|
||||
X"BFFFFFFF",
|
||||
X"CFFFFFFF",
|
||||
X"7FFFFFFF"
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: muldiv
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
hilo_we => hilo_we,
|
||||
din_hi => din_hi,
|
||||
din_lo => din_lo,
|
||||
mul_divn => mul_divn,
|
||||
s_un => s_un,
|
||||
start => start,
|
||||
hilo_sel => hilo_sel,
|
||||
busy => busy,
|
||||
dout => dout
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
REF_GEN: process
|
||||
begin
|
||||
if mul_divn = '0' then
|
||||
wait until rising_edge(clk) and check = '1';
|
||||
if s_un = '1' then
|
||||
rtmp <= unsigned(signed(md_result(31 downto 0)) * signed(din_lo));
|
||||
wait until rising_edge(clk);
|
||||
tmp2 <= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32)));
|
||||
wait until rising_edge(clk);
|
||||
ref_hi <= tmp2(31 downto 0);
|
||||
else
|
||||
rtmp <= md_result(31 downto 0) * din_lo;
|
||||
wait until rising_edge(clk);
|
||||
tmp2 <= rtmp(31 downto 0) + md_result(63 downto 32);
|
||||
wait until rising_edge(clk);
|
||||
ref_hi <= tmp2(31 downto 0);
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
if din_lo /= X"00000000" then
|
||||
if ENABLE_FAIL_REPORT then
|
||||
assert din_hi = ref_hi report "Error on divison" severity failure;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
wait until rising_edge(clk) and check = '1';
|
||||
if s_un = '1' then
|
||||
ref_result <= unsigned(signed(din_hi) * signed(din_lo));
|
||||
else
|
||||
ref_result <= unsigned(din_hi) * unsigned(din_lo);
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
if ENABLE_FAIL_REPORT then
|
||||
assert ref_result = md_result report "Error on multiplication" severity failure;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
rst <= '0';
|
||||
wait for 2*CLK_PERIOD;
|
||||
|
||||
mul_divn <= '0';
|
||||
s_un <= '0';
|
||||
for i in 0 to operands'length-1 loop
|
||||
for j in 0 to operands'length-1 loop
|
||||
check <= '0';
|
||||
wait until rising_edge(clk) and busy = '0';
|
||||
din_hi <= operands(i);
|
||||
din_lo <= operands(j);
|
||||
start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
start <= '0';
|
||||
hilo_sel <= '0';
|
||||
|
||||
-- Read result
|
||||
wait until rising_edge(clk) and busy = '0';
|
||||
wait until rising_edge(clk);
|
||||
md_result(31 downto 0) <= dout;
|
||||
wait until rising_edge(clk);
|
||||
hilo_sel <= '1';
|
||||
wait until rising_edge(clk);
|
||||
md_result(63 downto 32) <= dout;
|
||||
check <= '1';
|
||||
wait until rising_edge(clk);
|
||||
check <= '0';
|
||||
wait for 8*CLK_PERIOD;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
s_un <= '1';
|
||||
for i in 0 to operands'length-1 loop
|
||||
for j in 0 to operands'length-1 loop
|
||||
check <= '0';
|
||||
wait until rising_edge(clk) and busy = '0';
|
||||
din_hi <= operands(i);
|
||||
din_lo <= operands(j);
|
||||
start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
start <= '0';
|
||||
hilo_sel <= '0';
|
||||
|
||||
-- Read result
|
||||
wait until rising_edge(clk) and busy = '0';
|
||||
wait until rising_edge(clk);
|
||||
md_result(31 downto 0) <= dout;
|
||||
wait until rising_edge(clk);
|
||||
hilo_sel <= '1';
|
||||
wait until rising_edge(clk);
|
||||
md_result(63 downto 32) <= dout;
|
||||
check <= '1';
|
||||
wait until rising_edge(clk);
|
||||
check <= '0';
|
||||
wait for 8*CLK_PERIOD;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
mul_divn <= '1';
|
||||
s_un <= '0';
|
||||
for i in 0 to operands'length-1 loop
|
||||
for j in 0 to operands'length-1 loop
|
||||
check <= '0';
|
||||
wait until rising_edge(clk) and busy = '0';
|
||||
din_hi <= operands(i);
|
||||
din_lo <= operands(j);
|
||||
start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
start <= '0';
|
||||
hilo_sel <= '0';
|
||||
|
||||
-- Read result
|
||||
wait until rising_edge(clk) and busy = '0';
|
||||
wait until rising_edge(clk);
|
||||
md_result(31 downto 0) <= dout;
|
||||
wait until rising_edge(clk);
|
||||
hilo_sel <= '1';
|
||||
wait until rising_edge(clk);
|
||||
md_result(63 downto 32) <= dout;
|
||||
check <= '1';
|
||||
wait until rising_edge(clk);
|
||||
check <= '0';
|
||||
wait for 8*CLK_PERIOD;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
s_un <= '1';
|
||||
for i in 0 to operands'length-1 loop
|
||||
for j in 0 to operands'length-1 loop
|
||||
check <= '0';
|
||||
wait until rising_edge(clk) and busy = '0';
|
||||
din_hi <= operands(i);
|
||||
din_lo <= operands(j);
|
||||
start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
start <= '0';
|
||||
hilo_sel <= '0';
|
||||
|
||||
-- Read result
|
||||
wait until rising_edge(clk) and busy = '0';
|
||||
wait until rising_edge(clk);
|
||||
md_result(31 downto 0) <= dout;
|
||||
wait until rising_edge(clk);
|
||||
hilo_sel <= '1';
|
||||
wait until rising_edge(clk);
|
||||
md_result(63 downto 32) <= dout;
|
||||
check <= '1';
|
||||
wait until rising_edge(clk);
|
||||
check <= '0';
|
||||
wait for 8*CLK_PERIOD;
|
||||
end loop;
|
||||
end loop;
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -1,233 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: Testbench for JCPU
|
||||
-- also writes 'opc.lst' for JASM-assembler
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.mips_instr.all;
|
||||
use work.async_types.all;
|
||||
use work.async_defs.all;
|
||||
|
||||
ENTITY tb_mips_sys IS
|
||||
END tb_mips_sys;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mips_sys IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant ICACHE_SIZE : natural := 512; -- words
|
||||
constant DCACHE_SIZE : natural := 512; -- words
|
||||
constant SRAM_ADDR_WIDTH : integer := 17; -- bits
|
||||
constant FLASH_ADDR_WIDTH : integer := 17; -- bits
|
||||
|
||||
signal debug : unsigned(1 downto 0);
|
||||
|
||||
-- Master
|
||||
signal nmi : STD_LOGIC := '0';
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk : STD_LOGIC := '0';
|
||||
signal eb : STD_LOGIC := '1';
|
||||
|
||||
signal flash_cs_n : std_logic;
|
||||
signal flash_we_n : std_logic;
|
||||
signal flash_oe_n : std_logic;
|
||||
signal flash_be_n : unsigned(3 downto 0);
|
||||
signal sram_cs_n : std_logic;
|
||||
signal sram_be_n : unsigned(3 downto 0);
|
||||
signal sram_wr_n : std_logic;
|
||||
signal sram_oe_n : std_logic;
|
||||
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
|
||||
signal sram_d : unsigned(31 downto 0);
|
||||
signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
|
||||
signal flash_d : unsigned(31 downto 0);
|
||||
|
||||
signal gpo0 : unsigned(31 downto 0);
|
||||
signal gpo1 : unsigned(31 downto 0);
|
||||
signal gpi0 : unsigned(31 downto 0) := (others => '0');
|
||||
signal gpi1 : unsigned(31 downto 0) := (others => '0');
|
||||
|
||||
signal int_timer : std_logic;
|
||||
signal int_uart : std_logic;
|
||||
signal rx : std_logic := '1';
|
||||
signal tx : std_logic;
|
||||
|
||||
type word_array_t is array (natural range <>) of unsigned(31 downto 0);
|
||||
signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
|
||||
signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
|
||||
|
||||
BEGIN
|
||||
|
||||
------------------------------------------------------------------
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
uut : entity work.mips_sys
|
||||
GENERIC MAP
|
||||
(
|
||||
ICACHE_SIZE => ICACHE_SIZE, -- words
|
||||
DCACHE_SIZE => DCACHE_SIZE, -- words
|
||||
SRAM_ADDR_WIDTH => SRAM_ADDR_WIDTH,
|
||||
FLASH_ADDR_WIDTH => FLASH_ADDR_WIDTH
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
eb => eb,
|
||||
nmi => nmi,
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
flash_cs_n => flash_cs_n,
|
||||
flash_oe_n => flash_oe_n,
|
||||
flash_we_n => flash_we_n,
|
||||
flash_be_n => flash_be_n,
|
||||
sram_cs_n => sram_cs_n,
|
||||
sram_we_n => sram_wr_n,
|
||||
sram_oe_n => sram_oe_n,
|
||||
sram_be_n => sram_be_n,
|
||||
sram_a => sram_a,
|
||||
sram_d => sram_d,
|
||||
flash_a => flash_a,
|
||||
flash_d => flash_d,
|
||||
|
||||
gpo0 => gpo0,
|
||||
gpo1 => gpo1,
|
||||
gpi0 => gpi0,
|
||||
gpi1 => gpi1,
|
||||
|
||||
rx => rx,
|
||||
tx => tx,
|
||||
|
||||
debug => debug
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRAM_READ:
|
||||
process(sram_a, sram_cs_n, sram_oe_n, sram_be_n)
|
||||
begin
|
||||
sram_d <= (others => 'Z') after 10 ns;
|
||||
if sram_oe_n = '0' then
|
||||
if sram_cs_n = '0' then
|
||||
if sram_be_n(0) = '0' then
|
||||
sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
|
||||
end if;
|
||||
if sram_be_n(1) = '0' then
|
||||
sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
|
||||
end if;
|
||||
if sram_be_n(2) = '0' then
|
||||
sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
|
||||
end if;
|
||||
if sram_be_n(3) = '0' then
|
||||
sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
SRAM_WRITE:
|
||||
process(sram_wr_n)
|
||||
begin
|
||||
if rising_edge(sram_wr_n) then
|
||||
if sram_cs_n = '0' then
|
||||
if sram_be_n(0) = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
|
||||
end if;
|
||||
if sram_be_n(1) = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
|
||||
end if;
|
||||
if sram_be_n(2) = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
|
||||
end if;
|
||||
if sram_be_n(3) = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
FLASH_READ:
|
||||
process(rst, flash_cs_n, flash_oe_n, flash_a)
|
||||
type file_t is file of integer;
|
||||
file load_flash : file_t open read_mode is "hello.flash.bin";
|
||||
variable instr : integer;
|
||||
variable index : natural;
|
||||
variable temp : signed(31 downto 0);
|
||||
constant tpd : time := 25 ns;
|
||||
begin
|
||||
if rst = '1' then
|
||||
index := 0;
|
||||
while not endfile(load_flash) loop
|
||||
read(load_flash, instr);
|
||||
temp := to_signed(instr, word_t'length);
|
||||
flash_data(index) <= unsigned(temp);
|
||||
index := index + 1;
|
||||
end loop;
|
||||
else
|
||||
flash_d <= (others => 'Z') after tpd;
|
||||
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
|
||||
if flash_oe_n = '0' then
|
||||
if flash_cs_n = '0' then
|
||||
if flash_be_n(0) = '0' then
|
||||
flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd;
|
||||
end if;
|
||||
if flash_be_n(1) = '0' then
|
||||
flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd;
|
||||
end if;
|
||||
if flash_be_n(2) = '0' then
|
||||
flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd;
|
||||
end if;
|
||||
if flash_be_n(3) = '0' then
|
||||
flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
rst <= '0';
|
||||
wait for 778254*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
nmi <= '0';
|
||||
wait for 3000*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
nmi <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -32,53 +32,25 @@ use work.mips_instr.all;
|
||||
use work.async_types.all;
|
||||
use work.async_defs.all;
|
||||
|
||||
ENTITY mips_sys IS
|
||||
GENERIC
|
||||
(
|
||||
ICACHE_SIZE : natural := 512; -- words
|
||||
DCACHE_SIZE : natural := 512; -- words
|
||||
SRAM_ADDR_WIDTH : integer := 14;
|
||||
FLASH_ADDR_WIDTH : integer := 14
|
||||
);
|
||||
PORT
|
||||
(
|
||||
eb : in std_logic;
|
||||
nmi : in std_logic;
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
flash_cs_n : out std_logic;
|
||||
flash_oe_n : out std_logic;
|
||||
flash_we_n : out std_logic;
|
||||
flash_be_n : out unsigned(3 downto 0);
|
||||
sram_cs_n : out std_logic;
|
||||
sram_we_n : out std_logic;
|
||||
sram_oe_n : out std_logic;
|
||||
sram_be_n : out unsigned(3 downto 0);
|
||||
sram_a : out unsigned(SRAM_ADDR_WIDTH-1 downto 0);
|
||||
sram_d : inout unsigned(31 downto 0);
|
||||
flash_a : out unsigned(FLASH_ADDR_WIDTH-1 downto 0);
|
||||
flash_d : inout unsigned(31 downto 0);
|
||||
|
||||
gpo0 : out unsigned(31 downto 0);
|
||||
gpo1 : out unsigned(31 downto 0);
|
||||
gpi0 : in unsigned(31 downto 0);
|
||||
gpi1 : in unsigned(31 downto 0);
|
||||
ENTITY tb_mips_top IS
|
||||
END tb_mips_top;
|
||||
|
||||
rx : in std_logic;
|
||||
tx : out std_logic;
|
||||
ARCHITECTURE behavior OF tb_mips_top IS
|
||||
|
||||
debug : out unsigned(1 downto 0)
|
||||
);
|
||||
END mips_sys;
|
||||
|
||||
ARCHITECTURE behavior OF mips_sys IS
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant SRAM_ADDR_WIDTH : integer := 14; -- bits
|
||||
constant FLASH_ADDR_WIDTH : integer := 14; -- bits
|
||||
|
||||
signal debug : unsigned(1 downto 0);
|
||||
|
||||
-- Master
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk : STD_LOGIC := '0';
|
||||
signal ACK_I : STD_LOGIC := '0';
|
||||
signal SRDY_I : STD_LOGIC := '0';
|
||||
signal ADDR_O : unsigned(31 downto 0);
|
||||
signal DAT_I : unsigned(31 downto 0) := (others => '0');
|
||||
signal DAT_O : unsigned(31 downto 0);
|
||||
signal ADDR_O : word_t;
|
||||
signal DAT_I : word_t := (others => '0');
|
||||
signal DAT_O : word_t;
|
||||
signal WE_O : STD_LOGIC;
|
||||
signal SEL_O : unsigned(3 downto 0);
|
||||
signal CYC_O : STD_LOGIC;
|
||||
@@ -112,14 +84,41 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
signal SRDY_O_uart : std_logic;
|
||||
signal DAT_O_uart : unsigned(31 downto 0);
|
||||
|
||||
signal int_timer : std_logic;
|
||||
signal int_uart : std_logic;
|
||||
signal flash_cs_n : std_logic;
|
||||
signal flash_oe_n : std_logic;
|
||||
signal sram_cs_n : std_logic;
|
||||
signal sram_wr_n : unsigned(3 downto 0);
|
||||
signal sram_oe_n : std_logic;
|
||||
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
|
||||
signal sram_d : unsigned(31 downto 0);
|
||||
signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
|
||||
signal flash_d : unsigned(31 downto 0);
|
||||
|
||||
signal gpo0 : unsigned(31 downto 0);
|
||||
signal gpo1 : unsigned(31 downto 0);
|
||||
signal gpi0 : unsigned(31 downto 0) := (others => '0');
|
||||
signal gpi1 : unsigned(31 downto 0) := (others => '0');
|
||||
|
||||
signal int_uart_rx : std_logic;
|
||||
signal rx : std_logic := '1';
|
||||
signal tx : std_logic;
|
||||
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
|
||||
signal mem_area : mem_area_t;
|
||||
|
||||
type word_array_t is array (natural range <>) of word_t;
|
||||
signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
|
||||
signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
|
||||
|
||||
BEGIN
|
||||
|
||||
------------------------------------------------------------------
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Memory mux
|
||||
------------------------------------------------------------------
|
||||
@@ -189,18 +188,10 @@ signal_mux:
|
||||
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_mips_top: entity work.mips_top
|
||||
GENERIC MAP
|
||||
(
|
||||
icache_size => ICACHE_SIZE, -- words
|
||||
dcache_size => DCACHE_SIZE -- words
|
||||
)
|
||||
uut: entity work.mips_top
|
||||
PORT MAP
|
||||
(
|
||||
debug => debug,
|
||||
nmi => nmi,
|
||||
eb => eb,
|
||||
cpu_clk => clk,
|
||||
RST_I => rst,
|
||||
CLK_I => clk,
|
||||
ACK_I => ACK_I,
|
||||
@@ -215,8 +206,7 @@ inst_mips_top: entity work.mips_top
|
||||
MRDY_O => MRDY_O,
|
||||
INT => INT
|
||||
);
|
||||
INT(1) <= int_uart;
|
||||
INT(5) <= int_timer;
|
||||
INT(1) <= int_uart_rx;
|
||||
|
||||
inst_rom : entity work.rom_wb
|
||||
PORT MAP
|
||||
@@ -247,7 +237,7 @@ inst_gpio : entity work.gpio_wb
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_gpio,
|
||||
INT_TIM_O => int_timer,
|
||||
|
||||
sys_gpo0 => gpo0,
|
||||
sys_gpo1 => gpo1,
|
||||
sys_gpi0 => gpi0,
|
||||
@@ -259,7 +249,7 @@ inst_flash_port : entity work.async_port_wb
|
||||
(
|
||||
addr_width => FLASH_ADDR_WIDTH,
|
||||
data_width => 32,
|
||||
byte_sel_width => 4,
|
||||
byte_sel_width => 1,
|
||||
async_timespec => ts_flash
|
||||
)
|
||||
PORT MAP
|
||||
@@ -276,13 +266,11 @@ inst_flash_port : entity work.async_port_wb
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_flash,
|
||||
page_mode_en => '0',
|
||||
async_a => flash_a,
|
||||
async_d => flash_d,
|
||||
async_cs => flash_cs_n,
|
||||
async_wr => flash_we_n,
|
||||
async_wr => open,
|
||||
async_rd => flash_oe_n,
|
||||
async_be => flash_be_n,
|
||||
async_rst => open
|
||||
);
|
||||
|
||||
@@ -308,13 +296,11 @@ inst_sram_port : entity work.async_port_wb
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_sram,
|
||||
page_mode_en => '0',
|
||||
async_a => sram_a,
|
||||
async_d => sram_d,
|
||||
async_cs => sram_cs_n,
|
||||
async_wr => sram_we_n,
|
||||
async_wr => sram_wr_n,
|
||||
async_rd => sram_oe_n,
|
||||
async_be => sram_be_n,
|
||||
async_rst => open
|
||||
);
|
||||
|
||||
@@ -333,9 +319,87 @@ inst_uart : entity work.uart_wb
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_uart,
|
||||
INT_O => int_uart,
|
||||
INT_RX_O => int_uart_rx,
|
||||
INT_TX_O => open,
|
||||
ser_rx => rx,
|
||||
ser_tx => tx
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRAM_READ:
|
||||
process(sram_a, sram_cs_n, sram_oe_n)
|
||||
begin
|
||||
sram_d <= (others => 'Z');
|
||||
if sram_oe_n = '0' then
|
||||
if sram_cs_n = '0' then
|
||||
sram_d <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
SRAM_WRITE:
|
||||
process(sram_a, sram_cs_n, sram_wr_n)
|
||||
begin
|
||||
if rising_edge(sram_wr_n(0)) then
|
||||
if sram_cs_n = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(1)) then
|
||||
if sram_cs_n = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(2)) then
|
||||
if sram_cs_n = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(3)) then
|
||||
if sram_cs_n = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
FLASH_READ:
|
||||
process(rst, flash_cs_n, flash_oe_n, flash_a)
|
||||
type file_t is file of integer;
|
||||
file load_flash : file_t open read_mode is "hello.flash.bin";
|
||||
variable instr : integer;
|
||||
variable index : natural;
|
||||
variable temp : signed(31 downto 0);
|
||||
begin
|
||||
if rst = '1' then
|
||||
index := 0;
|
||||
while not endfile(load_flash) loop
|
||||
read(load_flash, instr);
|
||||
temp := to_signed(instr, word_t'length);
|
||||
flash_data(index) <= unsigned(temp);
|
||||
index := index + 1;
|
||||
end loop;
|
||||
else
|
||||
flash_d <= (others => 'Z') after 10 ns;
|
||||
if flash_oe_n = '0' and flash_cs_n = '0' then
|
||||
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
|
||||
flash_d <= flash_data(index) after 10 ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
rst <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,20 @@
|
||||
vhdl work "../../src/core/mips_types.vhd"
|
||||
vhdl work "../../../../misc/dpram_2w2r.vhd"
|
||||
vhdl work "../../../../misc/dpram_1w1r_dist.vhd"
|
||||
vhdl work "../../../../misc/dpram_1w1r.vhd"
|
||||
vhdl work "../../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../src/core/mips_instr.vhd"
|
||||
vhdl work "../../../../FIFO/src/fifo_sync_dist.vhd"
|
||||
vhdl work "../../src/core/mips_shifter.vhd"
|
||||
vhdl work "../../src/core/mips_reg.vhd"
|
||||
vhdl work "../../src/core/mips_muldiv.vhd"
|
||||
vhdl work "../../src/core/mips_idecode_rom.vhd"
|
||||
vhdl work "../../src/core/mips_icache.vhd"
|
||||
vhdl work "../../src/core/mips_dcache.vhd"
|
||||
vhdl work "../../src/core/mips_cop.vhd"
|
||||
vhdl work "../../src/core/mips_bcu.vhd"
|
||||
vhdl work "../../src/core/mips_alu.vhd"
|
||||
vhdl work "../../src/core/mips_pipeline.vhd"
|
||||
vhdl work "../../src/core/mips_biu.vhd"
|
||||
vhdl work "../../src/core/mips_top.vhd"
|
||||
@@ -0,0 +1,20 @@
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
|
||||
@@ -0,0 +1,5 @@
|
||||
2008-10-26
|
||||
- Optimierung: MUL32x32 primitive für Virtex-4
|
||||
- External COP 1..3 interface
|
||||
- FPU (COP1)
|
||||
- MMU
|
||||
@@ -1,20 +1,17 @@
|
||||
CFLAGS=-O2
|
||||
|
||||
CC=gcc
|
||||
PREFIX=/usr/local
|
||||
|
||||
all: romgen ramgen flashgen
|
||||
|
||||
romgen: ./src/romgen.c
|
||||
$(CC) $(CFLAGS) ./src/romgen.c -lm -o ./romgen
|
||||
$(CC) $(CFLAGS) ./src/romgen.c -o ./romgen
|
||||
|
||||
ramgen: ./src/ramgen.c
|
||||
$(CC) $(CFLAGS) ./src/ramgen.c -lm -o ./ramgen
|
||||
$(CC) $(CFLAGS) ./src/ramgen.c -o ./ramgen
|
||||
|
||||
flashgen: ./src/flashgen.c
|
||||
$(CC) $(CFLAGS) ./src/flashgen.c -lm -o ./flashgen
|
||||
$(CC) $(CFLAGS) ./src/flashgen.c -o ./flashgen
|
||||
|
||||
install:
|
||||
cp romgen $(PREFIX)/bin
|
||||
cp ramgen $(PREFIX)/bin
|
||||
cp flashgen $(PREFIX)/bin
|
||||
clean:
|
||||
rm -rf romgen* ramgen* flashgen*
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -17,25 +17,10 @@
|
||||
#define SDRAM_BASE 0x40000000
|
||||
#define FLASH_OFFSET 0x00000000
|
||||
|
||||
#define MAGIC_EB 0x4A464931 // "JFI1" in big-endian;
|
||||
#define MAGIC_EL 0x3149464A // "JFI1" in little-endian;
|
||||
|
||||
UINT32 conv_endian32(UINT32 src)
|
||||
{
|
||||
UINT32 dst;
|
||||
|
||||
dst = (0xFF000000 & (src << 24))
|
||||
| (0x00FF0000 & (src << 8))
|
||||
| (0x0000FF00 & (src >> 8))
|
||||
| (0x000000FF & (src >> 24));
|
||||
|
||||
return dst;
|
||||
};
|
||||
|
||||
// --------------------------------------------------------------
|
||||
typedef struct _sflash_img_hdr_t
|
||||
{
|
||||
UINT32 magic;
|
||||
UINT8 magic[4];
|
||||
UINT32 target_addr;
|
||||
UINT32 img_offset;
|
||||
UINT32 img_size;
|
||||
@@ -69,7 +54,6 @@ int main(int argc, char *argv[])
|
||||
char name_flash[1024];
|
||||
char name_prj[1024];
|
||||
char *pBuf;
|
||||
UINT32 *pBuf32;
|
||||
flash_img_hdr_t img_hdr = {0};
|
||||
|
||||
FILE *pFile;
|
||||
@@ -79,7 +63,7 @@ int main(int argc, char *argv[])
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
fprintf(stderr, "Usage: flashgen <input file> [-{EL|EB}]\n");
|
||||
fprintf(stderr, "Usage: flashgen <input file>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -114,22 +98,15 @@ int main(int argc, char *argv[])
|
||||
return 1;
|
||||
}
|
||||
|
||||
img_hdr.magic = MAGIC_EL;
|
||||
img_hdr.magic[0] = 'J';
|
||||
img_hdr.magic[1] = 'F';
|
||||
img_hdr.magic[2] = 'I';
|
||||
img_hdr.magic[3] = '1';
|
||||
img_hdr.target_addr = SDRAM_BASE;
|
||||
img_hdr.img_size = filesize;
|
||||
img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
|
||||
img_hdr.hdr_next = FLASH_OFFSET;
|
||||
|
||||
if (argc == 3)
|
||||
{
|
||||
if ((argv[2][0] == '-') && (toupper(argv[2][1]) == 'E') && (toupper(argv[2][2]) == 'B'))
|
||||
{
|
||||
img_hdr.magic = MAGIC_EB;
|
||||
pBuf32 = (UINT32*)pBuf;
|
||||
for (i=0; i < filesize/4; i ++)
|
||||
pBuf32[i] = conv_endian32(pBuf32[i]);
|
||||
}
|
||||
}
|
||||
fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
|
||||
fwrite(pBuf, 1, filesize, pFile);
|
||||
|
||||
|
||||
@@ -3,54 +3,11 @@
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#define INT8 char
|
||||
#define INT16 short
|
||||
#define INT32 long
|
||||
#define UINT8 unsigned char
|
||||
#define UINT16 unsigned short
|
||||
#define UINT32 unsigned long
|
||||
#define INT int
|
||||
#define UINT unsigned int
|
||||
#define FLOAT32 float
|
||||
#define FLOAT64 double
|
||||
|
||||
#define ARCH_NAME "data"
|
||||
#define ENT_NAME "rom"
|
||||
#define JTAG_ADDR_WIDTH 16
|
||||
|
||||
UINT32 g_endianess_EB;
|
||||
|
||||
// --------------------------------------------------------------
|
||||
UINT32 conv_endian32(UINT32 src)
|
||||
{
|
||||
UINT32 dst;
|
||||
|
||||
dst = (0xFF000000 & (src << 24))
|
||||
| (0x00FF0000 & (src << 8))
|
||||
| (0x0000FF00 & (src >> 8))
|
||||
| (0x000000FF & (src >> 24));
|
||||
|
||||
return dst;
|
||||
};
|
||||
|
||||
UINT32 to_big_endian32(UINT32 src)
|
||||
{
|
||||
#ifndef NATIVE_IS_BIG_ENDIAN
|
||||
return conv_endian32(src);
|
||||
#else
|
||||
return src;
|
||||
#endif
|
||||
}
|
||||
|
||||
UINT32 from_big_endian32(UINT32 src)
|
||||
{
|
||||
#ifndef NATIVE_IS_BIG_ENDIAN
|
||||
return conv_endian32(src);
|
||||
#else
|
||||
return src;
|
||||
#endif
|
||||
}
|
||||
|
||||
void basename(char *pSrc, char *pDst)
|
||||
{
|
||||
int i, size;
|
||||
@@ -133,11 +90,7 @@ int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntNa
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
if (g_endianess_EB)
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word));
|
||||
else
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
@@ -255,11 +208,7 @@ int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *p
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
if (g_endianess_EB)
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word));
|
||||
else
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
@@ -320,8 +269,7 @@ int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pE
|
||||
char binstr_addr[33];
|
||||
char binstr_data[33];
|
||||
|
||||
char tpl[] =
|
||||
{"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
@@ -365,10 +313,7 @@ int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pE
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
if (g_endianess_EB)
|
||||
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, to_big_endian32(word));
|
||||
else
|
||||
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
|
||||
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
|
||||
word_addr++;
|
||||
}
|
||||
fprintf(pFileOut, "\n");
|
||||
@@ -399,19 +344,14 @@ int main(int argc, char *argv[])
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
fprintf(stderr, "Usage: romgen <input file> <num. word address bits> [-{EL|EB}]\n");
|
||||
fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFilenameIn = argv[1];
|
||||
nbits_addr = atoi(argv[2]);
|
||||
if (argc == 3)
|
||||
nbits_addr = atoi(argv[2]);
|
||||
|
||||
g_endianess_EB = 0;
|
||||
if (argc == 4)
|
||||
{
|
||||
if ((argv[3][0] == '-') && (toupper(argv[3][1]) == 'E') && (toupper(argv[3][2]) == 'B'))
|
||||
g_endianess_EB = 1;
|
||||
}
|
||||
|
||||
basename(pFilenameIn, name_prj);
|
||||
sprintf(name_rom, "%s.vhd", name_prj);
|
||||
|
||||
@@ -1,8 +0,0 @@
|
||||
VHDL/lib/FIFO/src/async_fifo_ctrl.vhd
|
||||
VHDL/lib/FIFO/src/fifo_async_ctrl.vhd
|
||||
VHDL/lib/FIFO/src/fifo_async_ctrl.vhd
|
||||
|
||||
VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd
|
||||
|
||||
VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd
|
||||
VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd
|
||||
@@ -1,248 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: FIFO, generic FIFOs written in VHDL
|
||||
-- Release 1
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
entity fifo_async_ctrl is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
almost_full_thresh : integer := 6;
|
||||
almost_empty_thresh : integer := 2
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk_w : in STD_LOGIC;
|
||||
clk_r : in STD_LOGIC;
|
||||
winc : in STD_LOGIC;
|
||||
rinc : in STD_LOGIC;
|
||||
ptr_w : out unsigned (addr_width-1 downto 0);
|
||||
ptr_r : out unsigned (addr_width-1 downto 0);
|
||||
fifo_pre_full : out STD_LOGIC;
|
||||
fifo_pre_empty : out STD_LOGIC;
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC
|
||||
);
|
||||
end fifo_async_ctrl;
|
||||
|
||||
architecture Behavioral of fifo_async_ctrl is
|
||||
|
||||
signal gcnt_w : unsigned (addr_width downto 0);
|
||||
signal gcnt2_w : unsigned (addr_width downto 0);
|
||||
signal bcnt2_aw : unsigned (addr_width downto 0);
|
||||
signal bcnt_w : unsigned (addr_width downto 0);
|
||||
signal gnxt_w : unsigned (addr_width downto 0);
|
||||
signal bnxt_w : unsigned (addr_width downto 0);
|
||||
signal gcnt_r : unsigned (addr_width downto 0);
|
||||
signal gcnt2_r : unsigned (addr_width downto 0);
|
||||
signal bcnt2_ar : unsigned (addr_width downto 0);
|
||||
signal bcnt_r : unsigned (addr_width downto 0);
|
||||
signal gnxt_r : unsigned (addr_width downto 0);
|
||||
signal bnxt_r : unsigned (addr_width downto 0);
|
||||
|
||||
signal pre_empty, pre_full : std_logic;
|
||||
signal full, empty : std_logic;
|
||||
|
||||
-- synthesis translate_off
|
||||
signal diffw : signed (addr_width downto 0);
|
||||
signal diffr : signed (addr_width downto 0);
|
||||
-- synthesis translate_on
|
||||
|
||||
begin
|
||||
|
||||
ptr_w <= bcnt_w(addr_width-1 downto 0);
|
||||
ptr_r <= bnxt_r(addr_width-1 downto 0);
|
||||
fifo_full <= full;
|
||||
fifo_empty <= empty;
|
||||
fifo_pre_full <= pre_full;
|
||||
fifo_pre_empty <= pre_empty;
|
||||
|
||||
proc_write_inhibit:
|
||||
process(rst, clk_w)
|
||||
begin
|
||||
if rst = '1' then
|
||||
full <= '0';
|
||||
elsif rising_edge(clk_w) then
|
||||
full <= pre_full;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_read_inhibit:
|
||||
process(rst, clk_r)
|
||||
begin
|
||||
if rst = '1' then
|
||||
empty <= '1';
|
||||
elsif rising_edge(clk_r) then
|
||||
empty <= pre_empty;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_sync_grptr:
|
||||
process(clk_w)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_w) then
|
||||
gcnt2_r <= p2;
|
||||
p2 := p1;
|
||||
p1 := gcnt_r;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_gwptr:
|
||||
process(clk_r)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_r) then
|
||||
gcnt2_w <= p2;
|
||||
p2 := p1;
|
||||
p1 := gcnt_w;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_full:
|
||||
process(gnxt_w, gcnt2_r)
|
||||
begin
|
||||
if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
|
||||
pre_full <= '1';
|
||||
else
|
||||
pre_full <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_empty:
|
||||
process(gnxt_r, gcnt2_w)
|
||||
begin
|
||||
if (gnxt_r = gcnt2_w) then
|
||||
pre_empty <= '1';
|
||||
else
|
||||
pre_empty <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_sync_arptr:
|
||||
process(clk_w)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_w) then
|
||||
bcnt2_ar <= p2;
|
||||
p2 := p1;
|
||||
p1 := bcnt_r;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_awptr:
|
||||
process(clk_r)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_r) then
|
||||
bcnt2_aw <= p2;
|
||||
p2 := p1;
|
||||
p1 := bcnt_w;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_full:
|
||||
process(rst, clk_w)
|
||||
variable diff : unsigned (addr_width downto 0);
|
||||
begin
|
||||
-- synthesis translate_off
|
||||
diffw <= signed(diff);
|
||||
-- synthesis translate_on
|
||||
if rst = '1' then
|
||||
fifo_afull <= '0';
|
||||
diff := (others => '0');
|
||||
elsif rising_edge(clk_w) then
|
||||
if diff >= almost_full_thresh-1 then
|
||||
fifo_afull <= '1';
|
||||
else
|
||||
fifo_afull <= '0';
|
||||
end if;
|
||||
diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_empty:
|
||||
process(rst, clk_r)
|
||||
variable diff : unsigned (addr_width downto 0);
|
||||
begin
|
||||
-- synthesis translate_off
|
||||
diffr <= signed(diff);
|
||||
-- synthesis translate_on
|
||||
if rst = '1' then
|
||||
fifo_aempty <= '1';
|
||||
diff := (others => '0');
|
||||
elsif rising_edge(clk_r) then
|
||||
if diff <= almost_empty_thresh+1 then
|
||||
fifo_aempty <= '1';
|
||||
else
|
||||
fifo_aempty <= '0';
|
||||
end if;
|
||||
diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_gray_counter_w : entity work.gray_counter
|
||||
generic map
|
||||
(
|
||||
width => addr_width+1,
|
||||
init_value => 0
|
||||
)
|
||||
port map
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk_w,
|
||||
ce => winc,
|
||||
bcnt => bcnt_w,
|
||||
bnxt => bnxt_w,
|
||||
gcnt => gcnt_w,
|
||||
gnxt => gnxt_w
|
||||
);
|
||||
|
||||
inst_gray_counter_r : entity work.gray_counter
|
||||
generic map
|
||||
(
|
||||
width => addr_width+1,
|
||||
init_value => 0
|
||||
)
|
||||
port map
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk_r,
|
||||
ce => rinc,
|
||||
bcnt => bcnt_r,
|
||||
bnxt => bnxt_r,
|
||||
gcnt => gcnt_r,
|
||||
gnxt => gnxt_r
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,124 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: FIFO, generic FIFOs written in VHDL
|
||||
-- Release 1
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.fifo_ctrl_pkg.all;
|
||||
|
||||
entity fifo_async is
|
||||
Generic
|
||||
(
|
||||
addr_width : natural := 4;
|
||||
data_width : natural := 8;
|
||||
almost_full_thresh : integer := 12;
|
||||
almost_empty_thresh : integer := 4;
|
||||
allow_full_writes : boolean := false;
|
||||
allow_empty_reads : boolean := false;
|
||||
do_last_read_update : boolean := true
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk_w : in STD_LOGIC;
|
||||
clk_r : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC;
|
||||
data_w : in unsigned (data_width-1 downto 0);
|
||||
data_r : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end fifo_async;
|
||||
|
||||
architecture Behavioral of fifo_async is
|
||||
|
||||
signal mem_wr_en : STD_LOGIC;
|
||||
signal mem_rd_en : STD_LOGIC;
|
||||
signal ptr_w : unsigned (addr_width-1 downto 0);
|
||||
signal ptr_r : unsigned (addr_width-1 downto 0);
|
||||
signal full : std_logic;
|
||||
signal empty : std_logic;
|
||||
signal pre_full : STD_LOGIC;
|
||||
signal pre_empty : STD_LOGIC;
|
||||
signal rinc : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
fifo_full <= full;
|
||||
fifo_empty <= empty;
|
||||
|
||||
mem_wr_en <= (we and not full) when allow_full_writes = false else we;
|
||||
rinc <= (re and not empty) when allow_empty_reads = false else re;
|
||||
mem_rd_en <= not pre_empty when do_last_read_update = false else '1';
|
||||
|
||||
|
||||
inst_fifo_async_ctrl: entity work.fifo_async_ctrl
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
almost_full_thresh => almost_full_thresh,
|
||||
almost_empty_thresh => almost_empty_thresh
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => clk_w,
|
||||
clk_r => clk_r,
|
||||
winc => mem_wr_en,
|
||||
rinc => rinc,
|
||||
ptr_w => ptr_w,
|
||||
ptr_r => ptr_r,
|
||||
fifo_full => full,
|
||||
fifo_empty => empty,
|
||||
fifo_pre_full => pre_full,
|
||||
fifo_pre_empty => pre_empty,
|
||||
fifo_afull => fifo_afull,
|
||||
fifo_aempty => fifo_aempty
|
||||
|
||||
);
|
||||
|
||||
inst_dpram_1w1r: entity work.dpram_1w1r
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => data_width
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk_w,
|
||||
clkb => clk_r,
|
||||
en_a => '1',
|
||||
en_b => mem_rd_en,
|
||||
we_a => mem_wr_en,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => data_w,
|
||||
dout_b => data_r
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,67 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: FIFO, generic FIFOs written in VHDL
|
||||
-- Release 1
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package fifo_ctrl_pkg is
|
||||
|
||||
-- Constants
|
||||
-- Types
|
||||
|
||||
-- Functions
|
||||
function bin2gray(xb : unsigned) return unsigned;
|
||||
function gray2bin(xg : unsigned) return unsigned;
|
||||
|
||||
end fifo_ctrl_pkg;
|
||||
|
||||
package body fifo_ctrl_pkg is
|
||||
|
||||
function bin2gray(xb : unsigned) return unsigned is
|
||||
variable xg : unsigned(xb'left downto xb'right);
|
||||
begin
|
||||
|
||||
xg(xg'left) := xb(xb'left);
|
||||
for i in 1 to xb'left loop
|
||||
xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
|
||||
end loop;
|
||||
|
||||
return xg;
|
||||
end bin2gray;
|
||||
|
||||
function gray2bin(xg : unsigned) return unsigned is
|
||||
variable xb : unsigned(xg'left downto xg'right);
|
||||
begin
|
||||
|
||||
xb(xb'left) := xg(xg'left);
|
||||
for i in 1 to xg'left loop
|
||||
xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
|
||||
end loop;
|
||||
|
||||
return xb;
|
||||
end gray2bin;
|
||||
|
||||
end fifo_ctrl_pkg;
|
||||
|
||||
@@ -1,123 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: FIFO, generic FIFOs written in VHDL
|
||||
-- Release 1
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.fifo_ctrl_pkg.all;
|
||||
|
||||
entity fifo_sync is
|
||||
Generic
|
||||
(
|
||||
addr_width : natural := 4;
|
||||
data_width : natural := 8;
|
||||
almost_full_thresh : integer := 12;
|
||||
almost_empty_thresh : integer := 4;
|
||||
allow_full_writes : boolean := false;
|
||||
allow_empty_reads : boolean := false;
|
||||
do_last_read_update : boolean := true
|
||||
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC;
|
||||
data_w : in unsigned (data_width-1 downto 0);
|
||||
data_r : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end fifo_sync;
|
||||
|
||||
architecture Behavioral of fifo_sync is
|
||||
|
||||
signal mem_wr_en : STD_LOGIC;
|
||||
signal mem_rd_en : STD_LOGIC;
|
||||
signal ptr_w : unsigned (addr_width-1 downto 0);
|
||||
signal ptr_r : unsigned (addr_width-1 downto 0);
|
||||
signal full : STD_LOGIC;
|
||||
signal empty : std_logic;
|
||||
signal pre_full : STD_LOGIC;
|
||||
signal pre_empty : STD_LOGIC;
|
||||
signal rinc : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
fifo_full <= full;
|
||||
fifo_empty <= empty;
|
||||
|
||||
mem_wr_en <= (we and not full) when allow_full_writes = false else we;
|
||||
rinc <= (re and not empty) when allow_empty_reads = false else re;
|
||||
mem_rd_en <= not pre_empty when do_last_read_update = false else '1';
|
||||
|
||||
|
||||
inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
almost_full_thresh => almost_full_thresh,
|
||||
almost_empty_thresh => almost_empty_thresh
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
winc => mem_wr_en,
|
||||
rinc => rinc,
|
||||
ptr_w => ptr_w,
|
||||
ptr_r => ptr_r,
|
||||
fifo_full => full,
|
||||
fifo_empty => empty,
|
||||
fifo_pre_full => pre_full,
|
||||
fifo_pre_empty => pre_empty,
|
||||
fifo_afull => fifo_afull,
|
||||
fifo_aempty => fifo_aempty
|
||||
|
||||
);
|
||||
|
||||
inst_dpram_1w1r: entity work.dpram_1w1r
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => data_width
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk,
|
||||
clkb => clk,
|
||||
en_a => '1',
|
||||
en_b => mem_rd_en,
|
||||
we_a => mem_wr_en,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => data_w,
|
||||
dout_b => data_r
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,84 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: FIFO, generic FIFOs written in VHDL
|
||||
-- Release 1
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
entity gray_counter is
|
||||
Generic (
|
||||
width : natural := 3;
|
||||
init_value : natural := 0
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
bcnt : out unsigned (width-1 downto 0);
|
||||
bnxt : out unsigned (width-1 downto 0);
|
||||
gcnt : out unsigned (width-1 downto 0);
|
||||
gnxt : out unsigned (width-1 downto 0)
|
||||
);
|
||||
end gray_counter;
|
||||
|
||||
architecture Behavioral of gray_counter is
|
||||
|
||||
signal cntg : unsigned (width-1 downto 0);
|
||||
signal cntb : unsigned (width-1 downto 0);
|
||||
signal nxtb : unsigned (width-1 downto 0);
|
||||
signal nxtg : unsigned (width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
bnxt <= nxtb;
|
||||
gnxt <= nxtg;
|
||||
bcnt <= cntb;
|
||||
gcnt <= cntg;
|
||||
|
||||
process(rst, clk, ce, cntb, nxtb)
|
||||
begin
|
||||
if rst = '1' then
|
||||
cntb <= to_unsigned(init_value, width);
|
||||
nxtb <= to_unsigned(init_value, width);
|
||||
nxtg <= to_unsigned(init_value, width);
|
||||
cntg <= to_unsigned(init_value, width);
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
cntg <= nxtg;
|
||||
cntb <= nxtb;
|
||||
end if;
|
||||
nxtg <= bin2gray(nxtb);
|
||||
nxtb <= cntb;
|
||||
if ce = '1' then
|
||||
nxtb <= cntb + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,198 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: FIFO, generic FIFOs written in VHDL
|
||||
-- Release 1
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
--
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity fifo_sync_ctrl is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
almost_full_thresh : integer := 6;
|
||||
almost_empty_thresh : integer := 2
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
winc : in STD_LOGIC;
|
||||
rinc : in STD_LOGIC;
|
||||
ptr_w : out unsigned (addr_width-1 downto 0);
|
||||
ptr_r : out unsigned (addr_width-1 downto 0);
|
||||
fifo_pre_full : out STD_LOGIC;
|
||||
fifo_pre_empty : out STD_LOGIC;
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC
|
||||
);
|
||||
end fifo_sync_ctrl;
|
||||
|
||||
architecture Behavioral of fifo_sync_ctrl is
|
||||
|
||||
signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
|
||||
signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
|
||||
signal empty, full : std_logic;
|
||||
signal pre_empty, pre_full : std_logic;
|
||||
signal was_write : std_logic;
|
||||
signal diff : unsigned (addr_width downto 0);
|
||||
|
||||
begin
|
||||
|
||||
fifo_full <= full;
|
||||
fifo_empty <= empty;
|
||||
fifo_pre_full <= pre_full;
|
||||
fifo_pre_empty <= pre_empty;
|
||||
|
||||
|
||||
proc_diff_gen:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
diff <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if winc = '1' and rinc = '0' then
|
||||
diff <= diff + 1;
|
||||
elsif winc = '0' and rinc = '1' then
|
||||
diff <= diff - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_full:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
fifo_afull <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if diff >= almost_full_thresh-1 then
|
||||
fifo_afull <= '1';
|
||||
else
|
||||
fifo_afull <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_empty:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
fifo_aempty <= '1';
|
||||
elsif rising_edge(clk) then
|
||||
if diff <= almost_empty_thresh+1 then
|
||||
fifo_aempty <= '1';
|
||||
else
|
||||
fifo_aempty <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_full_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
full <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
full <= pre_full;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_empty_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
empty <= '1';
|
||||
elsif rising_edge(clk) then
|
||||
empty <= pre_empty;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_w:
|
||||
process(was_write, pW_next, pR_next, pW, pR, winc, rinc)
|
||||
begin
|
||||
if (pW_next = pR) and (winc = '1' or was_write = '1') then
|
||||
pre_full <= '1';
|
||||
else
|
||||
pre_full <= '0';
|
||||
end if;
|
||||
if (pR_next = pW) and (rinc = '1' or was_write = '0') then
|
||||
pre_empty <= '1';
|
||||
else
|
||||
pre_empty <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_flag_write:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
was_write <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if winc = '1' then
|
||||
was_write <= '1';
|
||||
elsif rinc = '1' then
|
||||
was_write <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_w:
|
||||
process(rst, clk, pW, winc)
|
||||
begin
|
||||
if rst = '1' then
|
||||
pW <= to_unsigned(0, addr_width);
|
||||
pW_next <= to_unsigned(0, addr_width);
|
||||
elsif rising_edge(clk) then
|
||||
if winc = '1' then
|
||||
pW <= pW_next;
|
||||
end if;
|
||||
end if;
|
||||
pW_next <= pW;
|
||||
if winc = '1' then
|
||||
pW_next <= pW + 1;
|
||||
end if;
|
||||
ptr_w <= pW;
|
||||
end process;
|
||||
|
||||
proc_ptr_r:
|
||||
process(rst, clk, pR_next, pR, rinc)
|
||||
begin
|
||||
if rst = '1' then
|
||||
pR <= to_unsigned(0, addr_width);
|
||||
pR_next <= to_unsigned(0, addr_width);
|
||||
elsif rising_edge(clk) then
|
||||
if rinc = '1' then
|
||||
pR <= pR_next;
|
||||
end if;
|
||||
end if;
|
||||
pR_next <= pR;
|
||||
if rinc = '1' then
|
||||
pR_next <= pR + 1;
|
||||
end if;
|
||||
ptr_r <= pR_next;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,317 +0,0 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use work.async_types.all;
|
||||
|
||||
------------------------------------------------------------------
|
||||
entity async_port_wb is
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0;
|
||||
addr_width : natural := 32;
|
||||
data_width : natural := 32;
|
||||
byte_sel_width : natural := 4;
|
||||
async_timespec : async_timespec_t
|
||||
);
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
page_mode_en : in STD_LOGIC;
|
||||
async_a : out unsigned(addr_width-1 downto 0);
|
||||
async_d : inout unsigned(data_width-1 downto 0);
|
||||
async_cs : out std_logic;
|
||||
async_wr : out std_logic;
|
||||
async_rd : out std_logic;
|
||||
async_be : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_rst : out std_logic
|
||||
);
|
||||
end async_port_wb;
|
||||
|
||||
architecture Behavioral of async_port_wb is
|
||||
|
||||
type async_t is record
|
||||
cs : std_logic;
|
||||
wr : std_logic;
|
||||
rd : std_logic;
|
||||
rst : std_logic;
|
||||
drive_d : std_logic;
|
||||
end record;
|
||||
|
||||
type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
|
||||
|
||||
signal s, sn : async_state_t;
|
||||
signal as : async_t;
|
||||
signal ack : std_logic;
|
||||
signal cc_rst : std_logic;
|
||||
signal cycle_cnt : natural range 0 to 31;
|
||||
signal cycle_reload : natural range 0 to 31;
|
||||
signal rdy : std_logic;
|
||||
signal rdyo : std_logic;
|
||||
signal en : std_logic;
|
||||
signal is_idle : std_logic;
|
||||
signal DAT_I_r : unsigned(data_width-1 downto 0);
|
||||
signal SEL_I_r : unsigned(byte_sel_width-1 downto 0);
|
||||
signal WE_I_r : std_logic;
|
||||
signal ADDR_I_r : unsigned(addr_width-1 downto 0);
|
||||
signal page_mode_en_r : std_logic;
|
||||
signal do_page_read : std_logic;
|
||||
|
||||
------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
|
||||
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
|
||||
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
|
||||
|
||||
SRDY_O <= CYC_I and rdyo;
|
||||
en <= CYC_I and STB_I;
|
||||
|
||||
do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
|
||||
|
||||
proc_cycle_counter:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if cc_rst = '1' then
|
||||
cycle_cnt <= cycle_reload;
|
||||
elsif cycle_cnt /= 0 then
|
||||
cycle_cnt <= cycle_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
proc_state_next:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
s <= start;
|
||||
else
|
||||
s <= sn;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_state:
|
||||
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
|
||||
begin
|
||||
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
|
||||
cc_rst <= '0';
|
||||
as.rst <= '0';
|
||||
as.cs <= '0';
|
||||
as.wr <= '0';
|
||||
as.rd <= '0';
|
||||
as.drive_d <= '0';
|
||||
ack <= '0';
|
||||
rdy <= '0';
|
||||
is_idle <= '0';
|
||||
|
||||
sn <= s;
|
||||
case s is
|
||||
|
||||
when start =>
|
||||
cc_rst <= '1';
|
||||
sn <= reset;
|
||||
when reset =>
|
||||
as.rst <= '1';
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
when idle =>
|
||||
rdy <= '1';
|
||||
is_idle <= '1';
|
||||
if en = '1' then
|
||||
as.cs <= '1';
|
||||
cc_rst <= '1';
|
||||
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
|
||||
sn <= pulse;
|
||||
if WE_I = '1' then
|
||||
cycle_reload <= 0;
|
||||
sn <= leadin; -- always lead-in for writes
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
|
||||
as.rd <= '1';
|
||||
end if;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
|
||||
sn <= leadin;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when leadin =>
|
||||
as.cs <= '1';
|
||||
as.rd <= not WE_I_r;
|
||||
as.drive_d <= WE_I_r;
|
||||
as.wr <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
sn <= pulse;
|
||||
if WE_I_r = '1' then
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when pulse =>
|
||||
as.cs <= '1';
|
||||
as.rd <= not WE_I_r;
|
||||
as.drive_d <= WE_I_r;
|
||||
as.wr <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
as.wr <= '0';
|
||||
cc_rst <= '1';
|
||||
ack <= not WE_I_r;
|
||||
rdy <= do_page_read;
|
||||
if en = '1' and do_page_read = '1' then
|
||||
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
|
||||
sn <= pulse;
|
||||
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
|
||||
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
|
||||
sn <= idle;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
|
||||
sn <= release;
|
||||
end if;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
|
||||
sn <= leadout;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when leadout =>
|
||||
as.cs <= '1';
|
||||
as.drive_d <= WE_I_r;
|
||||
if cycle_cnt = 0 then
|
||||
cc_rst <= '1';
|
||||
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
|
||||
sn <= idle;
|
||||
else
|
||||
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
|
||||
sn <= release;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when release =>
|
||||
if cycle_cnt = 0 then
|
||||
sn <= idle;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
sn <= idle;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ctrl:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
async_cs <= (not async_timespec.pol_cs) xor as.cs;
|
||||
async_wr <= (not async_timespec.pol_we) xor as.wr;
|
||||
async_rd <= (not async_timespec.pol_oe) xor as.rd;
|
||||
async_rst <= (not async_timespec.pol_rst) xor as.rst;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
din_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if as.rd = '1' then
|
||||
DAT_O(data_width-1 downto 0) <= async_d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_addr:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
async_a <= (others => '0');
|
||||
SEL_I_r <= (others => '0');
|
||||
elsif en = '1' and rdy = '1' then
|
||||
async_a <= ADDR_I(addr_width-1 downto 0);
|
||||
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
|
||||
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
|
||||
if is_idle = '1' then
|
||||
ADDR_I_r <= ADDR_I(addr_width-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
data_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
page_mode_en_r <= page_mode_en;
|
||||
if en = '1' and rdy = '1' then
|
||||
DAT_I_r <= DAT_I(data_width-1 downto 0);
|
||||
WE_I_r <= WE_I;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_SRDY:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
rdyo <= '1';
|
||||
elsif en = '1' then
|
||||
rdyo <= rdy and not rdyo;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_ACK:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
ACK_O <= '0';
|
||||
else
|
||||
ACK_O <= ack;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
output_data:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
async_d <= (others => 'Z');
|
||||
if as.drive_d = '1' then
|
||||
async_d <= DAT_I_r;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,60 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: MIPS System controller
|
||||
-- This file:
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
|
||||
package async_types is
|
||||
|
||||
type async_timespec_t is record
|
||||
T_leadin : real;
|
||||
T_pulse_rd : real;
|
||||
T_pulse_wr : real;
|
||||
T_leadout : real;
|
||||
T_release : real;
|
||||
T_pulse_rst : real;
|
||||
T_pulse_page_rd : real;
|
||||
can_page_rd : boolean;
|
||||
nbits_page_rd : natural;
|
||||
pol_cs : std_logic;
|
||||
pol_oe : std_logic;
|
||||
pol_we : std_logic;
|
||||
pol_be : std_logic;
|
||||
pol_rst : std_logic;
|
||||
end record;
|
||||
|
||||
function to_cycles(T_ns : real; f_Mhz : real) return natural;
|
||||
|
||||
end async_types;
|
||||
|
||||
package body async_types is
|
||||
|
||||
function to_cycles(T_ns : real; f_Mhz : real) return natural is
|
||||
begin
|
||||
|
||||
return natural(ceil(1.0E-3*T_ns*f_Mhz));
|
||||
|
||||
end to_cycles;
|
||||
end async_types;
|
||||
@@ -1,79 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram_1w1r is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_1w1r;
|
||||
|
||||
architecture Behavioral of dpram_1w1r is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,88 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity dpram_2w2r is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram_2w2r;
|
||||
|
||||
architecture Behavioral of dpram_2w2r is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
shared variable RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk_a)
|
||||
begin
|
||||
if clk_a'event and clk_a = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) := din_a;
|
||||
end if;
|
||||
dout_a <= RAM(to_integer(addr_a));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk_b)
|
||||
begin
|
||||
if clk_b'event and clk_b = '1' then
|
||||
if en_b = '1' then
|
||||
if we_b = '1' then
|
||||
RAM(to_integer(addr_b)) := din_b;
|
||||
end if;
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,309 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
ENTITY gpio_wb IS
|
||||
Generic
|
||||
(
|
||||
f_sysclk : real := 100.0
|
||||
);
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
INT_TIM_O : out STD_LOGIC;
|
||||
|
||||
sys_gpi_0 : in unsigned(31 downto 0);
|
||||
sys_gpo_0 : out unsigned(31 downto 0)
|
||||
|
||||
);
|
||||
END gpio_wb;
|
||||
|
||||
ARCHITECTURE behavior OF gpio_wb IS
|
||||
|
||||
constant num_timers : natural := 2;
|
||||
constant ncycles_usec : natural := natural(f_sysclk);
|
||||
|
||||
signal gpio_0_dout_reg : unsigned(31 downto 0);
|
||||
signal gpio_0_dir_reg : unsigned(31 downto 0);
|
||||
signal gpio_0_din_reg : unsigned(31 downto 0);
|
||||
|
||||
-- Signals to form an timer generating an interrupt every microsecond
|
||||
subtype tick_usec_t is natural range 0 to ncycles_usec-1;
|
||||
signal tick_usec : tick_usec_t := 0;
|
||||
signal cnt_usec : unsigned(31 downto 0);
|
||||
signal cnt_sec : unsigned(31 downto 0);
|
||||
signal cnt_usec_preset : unsigned(31 downto 0);
|
||||
signal cnt_sec_preset : unsigned(31 downto 0);
|
||||
signal cnt_usec_en : std_logic;
|
||||
signal cnt_usec_we : std_logic;
|
||||
signal cnt_sec_en : std_logic;
|
||||
signal cnt_sec_we : std_logic;
|
||||
|
||||
type timer_array_t is array (0 to num_timers-1) of unsigned(31 downto 0);
|
||||
signal timer_cnt : timer_array_t;
|
||||
signal timer_cmp : timer_array_t;
|
||||
signal timer_en : unsigned(0 to num_timers-1);
|
||||
signal timer_inten : unsigned(0 to num_timers-1);
|
||||
signal timer_irq : unsigned(0 to num_timers-1);
|
||||
signal timer_ovl : unsigned(0 to num_timers-1);
|
||||
signal timer_irq_ack : unsigned(0 to num_timers-1);
|
||||
signal timer_cnt_we : unsigned(0 to num_timers-1);
|
||||
signal timer_cmp_we : unsigned(0 to num_timers-1);
|
||||
|
||||
signal reg_data_wr : unsigned(31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
SRDY_O <= CYC_I;
|
||||
|
||||
tim_irq:
|
||||
process(timer_irq)
|
||||
variable irq : std_logic;
|
||||
begin
|
||||
irq := '0';
|
||||
for i in 0 to num_timers-1 loop
|
||||
irq := irq or timer_irq(i);
|
||||
end loop;
|
||||
INT_TIM_O <= irq;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
gpio_0_out:
|
||||
process(gpio_0_dir_reg, gpio_0_dout_reg)
|
||||
begin
|
||||
for i in 0 to 31 loop
|
||||
sys_gpo_0(i) <= 'Z';
|
||||
if gpio_0_dir_reg(i) = '1' then
|
||||
sys_gpo_0(i) <= gpio_0_dout_reg(i);
|
||||
end if;
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
gpio_0_in:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
for i in 0 to 31 loop
|
||||
if gpio_0_dir_reg(i) = '1' then
|
||||
gpio_0_din_reg(i) <= gpio_0_dout_reg(i);
|
||||
else
|
||||
gpio_0_din_reg(i) <= sys_gpi_0(i);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
------------------------------------------------------------------
|
||||
registers_write:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
cnt_usec_we <= '0';
|
||||
cnt_sec_we <= '0';
|
||||
timer_cnt_we <= (others => '0');
|
||||
timer_cmp_we <= (others => '0');
|
||||
timer_irq_ack <= (others => '0');
|
||||
if RST_I = '1' then
|
||||
gpio_0_dout_reg <= (others => '0');
|
||||
gpio_0_dir_reg <= (others => '0');
|
||||
timer_en <= (others => '0');
|
||||
timer_inten <= (others => '0');
|
||||
elsif (STB_I and CYC_I and WE_I) = '1' then
|
||||
reg_data_wr <= DAT_I;
|
||||
case ADDR_I(6 downto 2) is
|
||||
|
||||
when "00000" =>
|
||||
gpio_0_dout_reg <= DAT_I;
|
||||
|
||||
when "00001" =>
|
||||
gpio_0_dir_reg <= DAT_I;
|
||||
|
||||
when "00010" =>
|
||||
cnt_usec_we <= '1';
|
||||
|
||||
when "00011" =>
|
||||
cnt_sec_we <= '1';
|
||||
|
||||
when "00110" => -- timer control
|
||||
for i in 0 to num_timers-1 loop
|
||||
timer_en(i) <= DAT_I(2*i+0);
|
||||
timer_inten(i) <= DAT_I(2*i+1);
|
||||
end loop;
|
||||
when "00111" => -- timer status
|
||||
for i in 0 to num_timers-1 loop
|
||||
timer_irq_ack(i) <= DAT_I(2*i); -- IRQ acknowledge
|
||||
end loop;
|
||||
|
||||
when "01000" => -- timer count 0
|
||||
timer_cnt_we(0) <= '1';
|
||||
|
||||
when "01001" => -- timer count 1
|
||||
timer_cnt_we(1) <= '1';
|
||||
|
||||
when "01100" => -- timer compare 0
|
||||
timer_cmp_we(0) <= '1';
|
||||
|
||||
when "01101" => -- timer compare 1
|
||||
timer_cmp_we(1) <= '1';
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
registers_read:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
ACK_O <= '0';
|
||||
if (STB_I and CYC_I) = '1' then
|
||||
ACK_O <= not WE_I;
|
||||
DAT_O <= (others => '0');
|
||||
case ADDR_I(6 downto 2) is
|
||||
|
||||
when "00000" =>
|
||||
DAT_O <= gpio_0_din_reg;
|
||||
|
||||
when "00001" =>
|
||||
DAT_O <= gpio_0_dir_reg;
|
||||
|
||||
when "00010" =>
|
||||
DAT_O <= cnt_usec;
|
||||
|
||||
when "00011" =>
|
||||
DAT_O <= cnt_sec;
|
||||
|
||||
when "00110" => -- timer control
|
||||
for i in 0 to num_timers-1 loop
|
||||
DAT_O(2*i+0) <= timer_en(i);
|
||||
DAT_O(2*i+1) <= timer_inten(i);
|
||||
end loop;
|
||||
|
||||
when "00111" => -- timer status
|
||||
for i in 0 to num_timers-1 loop
|
||||
DAT_O(2*i+0) <= timer_irq(i);
|
||||
DAT_O(2*i+1) <= timer_ovl(i);
|
||||
end loop;
|
||||
|
||||
when "01000" => -- timer count 0
|
||||
DAT_O <= timer_cnt(0);
|
||||
|
||||
when "01001" => -- timer count 1
|
||||
DAT_O <= timer_cnt(1);
|
||||
|
||||
when "01100" => -- timer compare 0
|
||||
DAT_O <= timer_cmp(0);
|
||||
|
||||
when "01101" => -- timer compare 1
|
||||
DAT_O <= timer_cmp(1);
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cnt_usec_tick:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
cnt_usec_en <= '0';
|
||||
if tick_usec >= tick_usec_t'high then
|
||||
tick_usec <= 0;
|
||||
cnt_usec_en <= '1';
|
||||
else
|
||||
tick_usec <= tick_usec + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- H/W Clock
|
||||
cnt_usec_clock:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
cnt_sec_en <= '0';
|
||||
if cnt_usec_we = '1' then
|
||||
cnt_usec <= reg_data_wr;
|
||||
elsif cnt_usec_en = '1' then
|
||||
if to_01(cnt_usec) >= to_unsigned(1E6 - 1, 32) then
|
||||
cnt_usec <= (others => '0');
|
||||
cnt_sec_en <= '1';
|
||||
else
|
||||
cnt_usec <= cnt_usec + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cnt_sec_clock:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if cnt_sec_we = '1' then
|
||||
cnt_sec <= reg_data_wr;
|
||||
elsif cnt_sec_en = '1' then
|
||||
cnt_sec <= cnt_sec + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Interrupt timer
|
||||
proc_int_timer:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
for i in 0 to num_timers-1 loop
|
||||
if RST_I = '1' then
|
||||
timer_ovl(i) <= '0';
|
||||
timer_irq(i) <= '0';
|
||||
elsif timer_irq_ack(i) = '1' then
|
||||
timer_ovl(i) <= '0';
|
||||
timer_irq(i) <= '0';
|
||||
elsif timer_cnt_we(i) = '1' then
|
||||
timer_cnt(i) <= reg_data_wr;
|
||||
elsif timer_en(i) = '1' then
|
||||
if to_01(timer_cnt(i)) >= timer_cmp(i) then
|
||||
timer_cnt(i) <= (others => '0');
|
||||
if timer_inten(i) = '1' then
|
||||
if timer_irq(i) = '1' then
|
||||
timer_ovl(i) <= '1';
|
||||
end if;
|
||||
timer_irq(i) <= '1';
|
||||
end if;
|
||||
else
|
||||
timer_cnt(i) <= timer_cnt(i) + 1;
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_int_timer_reload:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
for i in 0 to num_timers-1 loop
|
||||
if timer_cmp_we(i) = '1' then
|
||||
timer_cmp(i) <= reg_data_wr;
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -1,61 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
ENTITY rom_wb IS
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0)
|
||||
);
|
||||
END rom_wb;
|
||||
|
||||
ARCHITECTURE behavior OF rom_wb IS
|
||||
|
||||
COMPONENT rom
|
||||
PORT
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal data_en : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
data_en <= CYC_I and STB_I and MRDY_I;
|
||||
SRDY_O <= CYC_I;
|
||||
|
||||
data_valid_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
ACK_O <= '0';
|
||||
else
|
||||
ACK_O <= data_en; -- and not WE_I;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_rom : rom
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK_I,
|
||||
ce => data_en,
|
||||
addr => ADDR_I,
|
||||
dout => DAT_O
|
||||
);
|
||||
|
||||
|
||||
end behavior;
|
||||
@@ -1,281 +0,0 @@
|
||||
-- 'Bucket Brigade' FIFO
|
||||
-- 16 deep
|
||||
-- 8-bit data
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 14th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for BBFIFO_16x8
|
||||
--
|
||||
entity bbfifo_16x8 is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end bbfifo_16x8;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for BBFIFO_16x8
|
||||
--
|
||||
architecture low_level_definition of bbfifo_16x8 is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in BBFIFO_16x8
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal pointer : std_logic_vector(3 downto 0);
|
||||
signal next_count : std_logic_vector(3 downto 0);
|
||||
signal half_count : std_logic_vector(3 downto 0);
|
||||
signal count_carry : std_logic_vector(2 downto 0);
|
||||
|
||||
signal pointer_zero : std_logic;
|
||||
signal pointer_full : std_logic;
|
||||
signal decode_data_present : std_logic;
|
||||
signal data_present_int : std_logic;
|
||||
signal valid_write : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of zero_lut : label is "0001";
|
||||
attribute INIT of full_lut : label is "8000";
|
||||
attribute INIT of dp_lut : label is "BFA0";
|
||||
attribute INIT of valid_lut : label is "C4";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of BBFIFO_16x8 circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- SRL16E data storage
|
||||
|
||||
data_width_loop: for i in 0 to 7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of data_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
data_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_in(i),
|
||||
CE => valid_write,
|
||||
CLK => clk,
|
||||
A0 => pointer(0),
|
||||
A1 => pointer(1),
|
||||
A2 => pointer(2),
|
||||
A3 => pointer(3),
|
||||
Q => data_out(i) );
|
||||
|
||||
end generate data_width_loop;
|
||||
|
||||
-- 4-bit counter to act as data pointer
|
||||
-- Counter is clock enabled by 'data_present'
|
||||
-- Counter will be reset when 'reset' is active
|
||||
-- Counter will increment when 'valid_write' is active
|
||||
|
||||
count_width_loop: for i in 0 to 3 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of count_lut : label is "6606";
|
||||
--
|
||||
begin
|
||||
|
||||
register_bit: FDRE
|
||||
port map ( D => next_count(i),
|
||||
Q => pointer(i),
|
||||
CE => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
count_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"6606")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(i),
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => write,
|
||||
O => half_count(i));
|
||||
|
||||
lsb_count: if i=0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => valid_write,
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => valid_write,
|
||||
O => next_count(i));
|
||||
|
||||
end generate lsb_count;
|
||||
|
||||
mid_count: if i>0 and i<3 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => count_carry(i-1),
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate mid_count;
|
||||
|
||||
upper_count: if i=3 generate
|
||||
begin
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate upper_count;
|
||||
|
||||
end generate count_width_loop;
|
||||
|
||||
|
||||
-- Detect when pointer is zero and maximum
|
||||
|
||||
zero_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0001")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_zero );
|
||||
|
||||
|
||||
full_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8000")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_full );
|
||||
|
||||
|
||||
-- Data Present status
|
||||
|
||||
dp_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"BFA0")
|
||||
--synthesis translate_on
|
||||
port map( I0 => write,
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => data_present_int,
|
||||
O => decode_data_present );
|
||||
|
||||
dp_flop: FDR
|
||||
port map ( D => decode_data_present,
|
||||
Q => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
-- Valid write signal
|
||||
|
||||
valid_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"C4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer_full,
|
||||
I1 => write,
|
||||
I2 => read,
|
||||
O => valid_write );
|
||||
|
||||
|
||||
-- assign internal signals to outputs
|
||||
|
||||
full <= pointer_full;
|
||||
half_full <= pointer(3);
|
||||
data_present <= data_present_int;
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE BBFIFO_16x8.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -1,352 +0,0 @@
|
||||
-- Constant (K) Compact UART Receiver
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 16th October 2002
|
||||
--
|
||||
-- Start of design entry : 16th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART_RX
|
||||
--
|
||||
entity kcuart_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART_RX
|
||||
--
|
||||
architecture low_level_definition of kcuart_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal sync_serial : std_logic;
|
||||
signal stop_bit : std_logic;
|
||||
signal data_int : std_logic_vector(7 downto 0);
|
||||
signal data_delay : std_logic_vector(7 downto 0);
|
||||
signal start_delay : std_logic;
|
||||
signal start_bit : std_logic;
|
||||
signal edge_delay : std_logic;
|
||||
signal start_edge : std_logic;
|
||||
signal decode_valid_char : std_logic;
|
||||
signal valid_char : std_logic;
|
||||
signal decode_purge : std_logic;
|
||||
signal purge : std_logic;
|
||||
signal valid_srl_delay : std_logic_vector(8 downto 0);
|
||||
signal valid_reg_delay : std_logic_vector(8 downto 0);
|
||||
signal decode_data_strobe : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of start_srl : label is "0000";
|
||||
attribute INIT of edge_srl : label is "0000";
|
||||
attribute INIT of valid_lut : label is "0040";
|
||||
attribute INIT of purge_lut : label is "54";
|
||||
attribute INIT of strobe_lut : label is "8";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Synchronise input serial data to system clock
|
||||
|
||||
sync_reg: FD
|
||||
port map ( D => serial_in,
|
||||
Q => sync_serial,
|
||||
C => clk);
|
||||
|
||||
stop_reg: FD
|
||||
port map ( D => sync_serial,
|
||||
Q => stop_bit,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture data at 16 time baud rate
|
||||
-- Each SRL16E is followed by a flip-flop for best timing
|
||||
|
||||
data_loop: for i in 0 to 7 generate
|
||||
begin
|
||||
|
||||
lsbs: if i<7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(i+1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate lsbs;
|
||||
|
||||
msb: if i=7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => stop_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate msb;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => data_delay(i),
|
||||
Q => data_int(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate data_loop;
|
||||
|
||||
-- Assign internal signals to outputs
|
||||
|
||||
data_out <= data_int;
|
||||
|
||||
-- Data delays to capture start bit at 16 time baud rate
|
||||
|
||||
start_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(0),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => start_delay );
|
||||
|
||||
start_reg: FDE
|
||||
port map ( D => start_delay,
|
||||
Q => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture start bit leading edge at 16 time baud rate
|
||||
-- Delay ensures data is captured at mid-bit position
|
||||
|
||||
edge_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '0',
|
||||
Q => edge_delay );
|
||||
|
||||
edge_reg: FDE
|
||||
port map ( D => edge_delay,
|
||||
Q => start_edge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Detect a valid character
|
||||
|
||||
valid_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0040")
|
||||
--synthesis translate_on
|
||||
port map( I0 => purge,
|
||||
I1 => stop_bit,
|
||||
I2 => start_edge,
|
||||
I3 => edge_delay,
|
||||
O => decode_valid_char );
|
||||
|
||||
valid_reg: FDE
|
||||
port map ( D => decode_valid_char,
|
||||
Q => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Purge of data status
|
||||
|
||||
purge_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"54")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_reg_delay(8),
|
||||
I1 => valid_char,
|
||||
I2 => purge,
|
||||
O => decode_purge );
|
||||
|
||||
purge_reg: FDE
|
||||
port map ( D => decode_purge,
|
||||
Q => purge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Delay of valid_char pulse of length equivalent to the time taken
|
||||
-- to purge data shift register of all data which has been used.
|
||||
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
|
||||
-- up to 16 delays and utilising the dedicated flip flop in each stage.
|
||||
|
||||
valid_loop: for i in 0 to 8 generate
|
||||
begin
|
||||
|
||||
lsb: if i=0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate lsb;
|
||||
|
||||
msbs: if i>0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay16_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay16_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_reg_delay(i-1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate msbs;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => valid_srl_delay(i),
|
||||
Q => valid_reg_delay(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate valid_loop;
|
||||
|
||||
-- Form data strobe
|
||||
|
||||
strobe_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_char,
|
||||
I1 => en_16_x_baud,
|
||||
O => decode_data_strobe );
|
||||
|
||||
strobe_reg: FD
|
||||
port map ( D => decode_data_strobe,
|
||||
Q => data_strobe,
|
||||
C => clk);
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -1,394 +0,0 @@
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 2nd October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART_TX
|
||||
--
|
||||
entity kcuart_tx is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
Tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART_TX
|
||||
--
|
||||
architecture low_level_definition of kcuart_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal data_01 : std_logic;
|
||||
signal data_23 : std_logic;
|
||||
signal data_45 : std_logic;
|
||||
signal data_67 : std_logic;
|
||||
signal data_0123 : std_logic;
|
||||
signal data_4567 : std_logic;
|
||||
signal data_01234567 : std_logic;
|
||||
signal bit_select : std_logic_vector(2 downto 0);
|
||||
signal next_count : std_logic_vector(2 downto 0);
|
||||
signal mask_count : std_logic_vector(2 downto 0);
|
||||
signal mask_count_carry : std_logic_vector(2 downto 0);
|
||||
signal count_carry : std_logic_vector(2 downto 0);
|
||||
signal ready_to_start : std_logic;
|
||||
signal decode_Tx_start : std_logic;
|
||||
signal Tx_start : std_logic;
|
||||
signal decode_Tx_run : std_logic;
|
||||
signal Tx_run : std_logic;
|
||||
signal decode_hot_state : std_logic;
|
||||
signal hot_state : std_logic;
|
||||
signal hot_delay : std_logic;
|
||||
signal Tx_bit : std_logic;
|
||||
signal decode_Tx_stop : std_logic;
|
||||
signal Tx_stop : std_logic;
|
||||
signal decode_Tx_complete : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of mux1_lut : label is "E4FF";
|
||||
attribute INIT of mux2_lut : label is "E4FF";
|
||||
attribute INIT of mux3_lut : label is "E4FF";
|
||||
attribute INIT of mux4_lut : label is "E4FF";
|
||||
attribute INIT of ready_lut : label is "10";
|
||||
attribute INIT of start_lut : label is "0190";
|
||||
attribute INIT of run_lut : label is "1540";
|
||||
attribute INIT of hot_state_lut : label is "94";
|
||||
attribute INIT of delay14_srl : label is "0000";
|
||||
attribute INIT of stop_lut : label is "0180";
|
||||
attribute INIT of complete_lut : label is "8";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
mux1_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(0),
|
||||
I2 => data_in(1),
|
||||
I3 => Tx_run,
|
||||
O => data_01 );
|
||||
|
||||
mux2_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(2),
|
||||
I2 => data_in(3),
|
||||
I3 => Tx_run,
|
||||
O => data_23 );
|
||||
|
||||
mux3_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(4),
|
||||
I2 => data_in(5),
|
||||
I3 => Tx_run,
|
||||
O => data_45 );
|
||||
|
||||
mux4_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(6),
|
||||
I2 => data_in(7),
|
||||
I3 => Tx_run,
|
||||
O => data_67 );
|
||||
|
||||
mux5_muxf5: MUXF5
|
||||
port map( I1 => data_23,
|
||||
I0 => data_01,
|
||||
S => bit_select(1),
|
||||
O => data_0123 );
|
||||
|
||||
mux6_muxf5: MUXF5
|
||||
port map( I1 => data_67,
|
||||
I0 => data_45,
|
||||
S => bit_select(1),
|
||||
O => data_4567 );
|
||||
|
||||
mux7_muxf6: MUXF6
|
||||
port map( I1 => data_4567,
|
||||
I0 => data_0123,
|
||||
S => bit_select(2),
|
||||
O => data_01234567 );
|
||||
|
||||
-- Register serial output and force start and stop bits
|
||||
|
||||
pipeline_serial: FDRS
|
||||
port map ( D => data_01234567,
|
||||
Q => serial_out,
|
||||
R => Tx_start,
|
||||
S => Tx_stop,
|
||||
C => clk);
|
||||
|
||||
-- 3-bit counter
|
||||
-- Counter is clock enabled by en_16_x_baud
|
||||
-- Counter will be reset when 'Tx_start' is active
|
||||
-- Counter will increment when Tx_bit is active
|
||||
-- Tx_run must be active to count
|
||||
-- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
|
||||
|
||||
count_width_loop: for i in 0 to 2 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of count_lut : label is "8";
|
||||
--
|
||||
begin
|
||||
|
||||
register_bit: FDRE
|
||||
port map ( D => next_count(i),
|
||||
Q => bit_select(i),
|
||||
CE => en_16_x_baud,
|
||||
R => Tx_start,
|
||||
C => clk);
|
||||
|
||||
count_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(i),
|
||||
I1 => Tx_run,
|
||||
O => mask_count(i));
|
||||
|
||||
mask_and: MULT_AND
|
||||
port map( I0 => bit_select(i),
|
||||
I1 => Tx_run,
|
||||
LO => mask_count_carry(i));
|
||||
|
||||
lsb_count: if i=0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => mask_count_carry(i),
|
||||
CI => Tx_bit,
|
||||
S => mask_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => mask_count(i),
|
||||
CI => Tx_bit,
|
||||
O => next_count(i));
|
||||
|
||||
end generate lsb_count;
|
||||
|
||||
upper_count: if i>0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => mask_count_carry(i),
|
||||
CI => count_carry(i-1),
|
||||
S => mask_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => mask_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate upper_count;
|
||||
|
||||
end generate count_width_loop;
|
||||
|
||||
-- Ready to start decode
|
||||
|
||||
ready_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"10")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_run,
|
||||
I1 => Tx_start,
|
||||
I2 => send_character,
|
||||
O => ready_to_start );
|
||||
|
||||
-- Start bit enable
|
||||
|
||||
start_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0190")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_bit,
|
||||
I1 => Tx_stop,
|
||||
I2 => ready_to_start,
|
||||
I3 => Tx_start,
|
||||
O => decode_Tx_start );
|
||||
|
||||
Tx_start_reg: FDE
|
||||
port map ( D => decode_Tx_start,
|
||||
Q => Tx_start,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Run bit enable
|
||||
|
||||
run_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"1540")
|
||||
--synthesis translate_on
|
||||
port map( I0 => count_carry(2),
|
||||
I1 => Tx_bit,
|
||||
I2 => Tx_start,
|
||||
I3 => Tx_run,
|
||||
O => decode_Tx_run );
|
||||
|
||||
Tx_run_reg: FDE
|
||||
port map ( D => decode_Tx_run,
|
||||
Q => Tx_run,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Bit rate enable
|
||||
|
||||
hot_state_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"94")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_stop,
|
||||
I1 => ready_to_start,
|
||||
I2 => Tx_bit,
|
||||
O => decode_hot_state );
|
||||
|
||||
hot_state_reg: FDE
|
||||
port map ( D => decode_hot_state,
|
||||
Q => hot_state,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
delay14_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => hot_state,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => hot_delay );
|
||||
|
||||
Tx_bit_reg: FDE
|
||||
port map ( D => hot_delay,
|
||||
Q => Tx_bit,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Stop bit enable
|
||||
|
||||
stop_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0180")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_bit,
|
||||
I1 => Tx_run,
|
||||
I2 => count_carry(2),
|
||||
I3 => Tx_stop,
|
||||
O => decode_Tx_stop );
|
||||
|
||||
Tx_stop_reg: FDE
|
||||
port map ( D => decode_Tx_stop,
|
||||
Q => Tx_stop,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Tx_complete strobe
|
||||
|
||||
complete_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => count_carry(2),
|
||||
I1 => en_16_x_baud,
|
||||
O => decode_Tx_complete );
|
||||
|
||||
Tx_complete_reg: FD
|
||||
port map ( D => decode_Tx_complete,
|
||||
Q => Tx_complete,
|
||||
C => clk);
|
||||
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -1,146 +0,0 @@
|
||||
-- UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 8 bit, no parity, 1 stop bit
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 16th October 2002
|
||||
--
|
||||
-- Start of design entry : 16th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART_RX
|
||||
--
|
||||
entity uart_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_RX
|
||||
--
|
||||
architecture macro_level_definition of uart_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART_RX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Receiver
|
||||
--
|
||||
component kcuart_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x8
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal uart_data_out : std_logic_vector(7 downto 0);
|
||||
signal fifo_write : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
kcuart: kcuart_rx
|
||||
port map ( serial_in => serial_in,
|
||||
data_out => uart_data_out,
|
||||
data_strobe => fifo_write,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
clk => clk );
|
||||
|
||||
|
||||
buf: bbfifo_16x8
|
||||
port map ( data_in => uart_data_out,
|
||||
data_out => data_out,
|
||||
reset => reset_buffer,
|
||||
write => fifo_write,
|
||||
read => read_buffer,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => buffer_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -1,153 +0,0 @@
|
||||
-- UART Transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 8 bit, no parity, 1 stop bit
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 14th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART_TX
|
||||
--
|
||||
entity uart_tx is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
tx_complete : out std_logic;
|
||||
tx_empty : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_TX
|
||||
--
|
||||
architecture macro_level_definition of uart_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART_TX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
component kcuart_tx
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
Tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x8
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal fifo_data_out : std_logic_vector(7 downto 0);
|
||||
signal fifo_data_present : std_logic;
|
||||
signal fifo_read : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
tx_complete <= fifo_read;
|
||||
tx_empty <= not fifo_data_present;
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
kcuart: kcuart_tx
|
||||
port map ( data_in => fifo_data_out,
|
||||
send_character => fifo_data_present,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
Tx_complete => fifo_read,
|
||||
clk => clk);
|
||||
|
||||
|
||||
buf: bbfifo_16x8
|
||||
port map ( data_in => data_in,
|
||||
data_out => fifo_data_out,
|
||||
reset => reset_buffer,
|
||||
write => write_buffer,
|
||||
read => fifo_read,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => fifo_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -1,214 +0,0 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY uart_wb IS
|
||||
Generic
|
||||
(
|
||||
simulate_tx : boolean := false
|
||||
);
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
INT_O : out STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
ser_rx : in std_logic;
|
||||
ser_tx : out std_logic
|
||||
);
|
||||
END uart_wb;
|
||||
|
||||
ARCHITECTURE behavior OF uart_wb IS
|
||||
|
||||
COMPONENT uart_tx
|
||||
Port
|
||||
(
|
||||
data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
tx_complete : out std_logic;
|
||||
tx_empty : out std_logic;
|
||||
clk : in std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT uart_rx
|
||||
Port
|
||||
(
|
||||
serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Signals for UART connections
|
||||
signal baud_count : unsigned(15 downto 0);
|
||||
signal en_16_x_baud : std_logic;
|
||||
signal reg_we_uart_tx : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
signal reg_re_uart_rx : std_logic;
|
||||
signal reg_uart_tx : unsigned(7 downto 0);
|
||||
signal reg_uart_rx : std_logic_vector(7 downto 0);
|
||||
signal rx_data_present : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
signal uart_status_port : unsigned(15 downto 0);
|
||||
signal reg_uart_baud : unsigned(15 downto 0);
|
||||
signal rx_int_en : std_logic;
|
||||
signal tx_int_en : std_logic;
|
||||
signal irq_rx : std_logic;
|
||||
signal irq_tx : std_logic;
|
||||
signal tx_complete : std_logic;
|
||||
signal tx_empty : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
SRDY_O <= CYC_I;
|
||||
|
||||
------------------------------------------------------------------
|
||||
registers_write:
|
||||
process(CLK_I)
|
||||
file output: text open write_mode is "STD_OUTPUT";
|
||||
variable L : line;
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
reg_we_uart_tx <= '0';
|
||||
if RST_I = '1' then
|
||||
reg_uart_baud <= to_unsigned(53, 16);
|
||||
rx_int_en <= '0';
|
||||
tx_int_en <= '0';
|
||||
elsif (STB_I and CYC_I and WE_I) = '1' then
|
||||
case ADDR_I(5 downto 2) is
|
||||
|
||||
when "0000" =>
|
||||
if simulate_tx then
|
||||
if DAT_I(7 downto 0) /= X"0D" then
|
||||
write(L, character'val(to_integer(DAT_I(7 downto 0))));
|
||||
end if;
|
||||
if DAT_I(7 downto 0) = X"0A" then
|
||||
writeline(output, L);
|
||||
end if;
|
||||
else
|
||||
reg_we_uart_tx <= '1';
|
||||
reg_uart_tx <= DAT_I(7 downto 0);
|
||||
end if;
|
||||
|
||||
when "0001" =>
|
||||
rx_int_en <= DAT_I(6);
|
||||
tx_int_en <= DAT_I(5);
|
||||
|
||||
when "0010" =>
|
||||
reg_uart_baud <= DAT_I(15 downto 0);
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
registers_read:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
reg_re_uart_rx <= '0';
|
||||
ACK_O <= '0';
|
||||
if (STB_I and CYC_I) = '1' then
|
||||
ACK_O <= not WE_I;
|
||||
DAT_O <= (others => '0');
|
||||
case ADDR_I(5 downto 2) is
|
||||
|
||||
when "0000" =>
|
||||
reg_re_uart_rx <= not WE_I;
|
||||
DAT_O(7 downto 0) <= unsigned(reg_uart_rx);
|
||||
|
||||
when "0001" =>
|
||||
DAT_O(15 downto 0) <= uart_status_port;
|
||||
|
||||
when "0010" =>
|
||||
DAT_O(15 downto 0) <= reg_uart_baud;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
baud_timer:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
baud_count <= (others => '0');
|
||||
elsif baud_count = reg_uart_baud then
|
||||
baud_count <= (others => '0');
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
en_16_x_baud <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
irq_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
irq_tx <= tx_empty and tx_int_en;
|
||||
irq_rx <= rx_data_present and rx_int_en;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_uart_tx: uart_tx
|
||||
port map
|
||||
(
|
||||
data_in => std_logic_vector(reg_uart_tx),
|
||||
write_buffer => reg_we_uart_tx,
|
||||
reset_buffer => RST_I,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => ser_tx,
|
||||
buffer_full => tx_full,
|
||||
buffer_half_full => tx_half_full,
|
||||
tx_complete => tx_complete,
|
||||
tx_empty => tx_empty,
|
||||
clk => CLK_I
|
||||
);
|
||||
|
||||
inst_uart_rx: uart_rx
|
||||
port map
|
||||
(
|
||||
serial_in => ser_rx,
|
||||
data_out => reg_uart_rx,
|
||||
read_buffer => reg_re_uart_rx,
|
||||
reset_buffer => RST_I,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
buffer_data_present => rx_data_present,
|
||||
buffer_full => rx_full,
|
||||
buffer_half_full => rx_half_full,
|
||||
clk => CLK_I
|
||||
);
|
||||
|
||||
uart_status_port <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
|
||||
INT_O <= irq_rx or irq_tx;
|
||||
|
||||
end behavior;
|
||||
Reference in New Issue
Block a user