84 lines
2.2 KiB
VHDL
84 lines
2.2 KiB
VHDL
--------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: The arithmetic logic unit
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--
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-- Copyright (C) 2008 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.mips_types.all;
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entity muldiv is
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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din_vld_hi : in std_logic;
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din_vld_lo : in std_logic;
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din_hi : in word_t;
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din_lo : in word_t;
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hilo_sel : in std_logic;
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dout : out word_t
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);
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end muldiv;
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architecture Behavioral of muldiv is
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signal reg_hi, reg_lo : word_t;
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--------------------------------------------------------------------------
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begin
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--------------------------------------------------------------------------
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proc_reg_out:
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process(hilo_sel, reg_hi, reg_lo)
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begin
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if hilo_sel = '1' then
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dout <= reg_hi;
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else
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dout <= reg_lo;
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end if;
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end process;
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proc_reg_in:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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reg_hi <= (others => '0');
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reg_lo <= (others => '0');
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elsif din_vld_hi = '1' then
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if hilo_sel = '1' then
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reg_hi <= din_hi;
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else
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reg_lo <= din_hi;
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end if;
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end if;
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if din_vld_lo = '1' then
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reg_lo <= din_lo;
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end if;
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end if;
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end process;
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--------------------------------------------------------------------------
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end Behavioral;
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