jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: jens/vhdl:R4
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
...
compare: jens/vhdl:R8
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
195 Commits
R4 ... R8
Author SHA1 Message Date
jens f91e762e94 This commit was manufactured by cvs2svn to create tag 'R8'. 
git-svn-id: http://moon:8086/svn/vhdl/tags/R8@250 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:40:08 +00:00
jens 987f426a57 - update 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@249 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:40:07 +00:00
jens 6c03c853f6 - renamed bui, icache and dcache 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@248 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:34:55 +00:00
jens d63cdf3cb1 - renamed bui to biu 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@247 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:33:18 +00:00
jens 4c482f1cda - renamed 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@246 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 08:33:06 +00:00
jens 9f7547c68e - deleted 
git-svn-id: http://moon:8086/svn/vhdl/trunk@245 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-16 07:47:24 +00:00
jens dd6bd675f1 - changed to J-Bus interface 
git-svn-id: http://moon:8086/svn/vhdl/trunk@244 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-15 07:07:51 +00:00
jens c882f1d469 - changed read, write order (should have no effect) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@243 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 20:26:29 +00:00
jens 9163ced247 - uses common fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@242 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:43:36 +00:00
jens 0c8a1c2ec5 - removed reference to mix_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@241 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:41:01 +00:00
jens f053756416 - deleted 
git-svn-id: http://moon:8086/svn/vhdl/trunk@240 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:37:07 +00:00
jens 70645de004 - uses common fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@239 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:36:50 +00:00
jens e91134a95f - uses common fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@238 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-14 09:28:39 +00:00
jens d9030dc07c - removed decimation in m-script (which is done in CFIR) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@237 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-13 10:08:17 +00:00
jens 1417d6f5cd - bugfix 'x_out' register 
git-svn-id: http://moon:8086/svn/vhdl/trunk@236 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-13 09:55:05 +00:00
jens ef9b538769 - fir_stage_sys only uses pipe_latency as parameter 
git-svn-id: http://moon:8086/svn/vhdl/trunk@235 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-13 09:29:45 +00:00
jens 6a1d8f729f Initial version 
git-svn-id: http://moon:8086/svn/vhdl/trunk@234 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-12 10:11:09 +00:00
jens bcefe4639e - removed adding of one bit to cic_stages 
git-svn-id: http://moon:8086/svn/vhdl/trunk@233 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-12 09:56:08 +00:00
jens cf548fd893 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@232 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 19:08:23 +00:00
jens 89723cf6d0 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@231 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 18:47:33 +00:00
jens 308d0d8f4a - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@230 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 18:30:36 +00:00
jens 5483606f74 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@229 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 18:14:31 +00:00
jens 4e2cb68237 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@228 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 17:08:38 +00:00
jens 8d0bb58b5d - Coeff RAMs have no 'ce' for read 
git-svn-id: http://moon:8086/svn/vhdl/trunk@227 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 16:58:36 +00:00
jens bce7ba16b7 - Uses decimating CFIR (decimate by 2) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@226 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 15:44:07 +00:00
jens 7649b3fff0 deleted 
git-svn-id: http://moon:8086/svn/vhdl/trunk@225 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 15:31:42 +00:00
jens 16e7312df1 Initial version 
git-svn-id: http://moon:8086/svn/vhdl/trunk@224 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 15:31:32 +00:00
jens dd42e17b18 - decimating is now working 
git-svn-id: http://moon:8086/svn/vhdl/trunk@223 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 12:57:26 +00:00
jens 748bd9e52a - removed 'ce' 
git-svn-id: http://moon:8086/svn/vhdl/trunk@222 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-11 12:57:06 +00:00
jens c403b3b22d - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@221 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 21:16:38 +00:00
jens 9c45912627 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@220 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 19:22:25 +00:00
jens 170a65237b - Prepared with FIFO for decimating FIR 
git-svn-id: http://moon:8086/svn/vhdl/trunk@219 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 19:22:15 +00:00
jens 937e129a55 - reverted to 1.10 
- kept signal 'start' to trigger FIR process


git-svn-id: http://moon:8086/svn/vhdl/trunk@218 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 19:15:23 +00:00
jens d059cf8109 - new signal 'start' to trigger FIR process 
use din_vld for data load. This permits decimation FIR filtering


git-svn-id: http://moon:8086/svn/vhdl/trunk@217 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 17:40:32 +00:00
jens ffa4eb81ca - Lowpass prototype: omega is fraction of fs/2 
git-svn-id: http://moon:8086/svn/vhdl/trunk@216 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-10 08:56:38 +00:00
jens 04e1b6fcbf - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@215 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-09 11:50:57 +00:00
jens 8106295641 - added unfiltered output at ddc for eval 
git-svn-id: http://moon:8086/svn/vhdl/trunk@214 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-09 11:50:40 +00:00
jens 5f40d70789 - coef input registered 
git-svn-id: http://moon:8086/svn/vhdl/trunk@213 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-08 10:25:45 +00:00
jens 83a9b4c417 - changed iterative CFIR wirh semi-parallel version 
git-svn-id: http://moon:8086/svn/vhdl/trunk@212 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-06 21:20:29 +00:00
jens a98a8bb0ba - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@211 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-06 21:15:45 +00:00
jens 590734078c - added assertion check for min coef_latency 
git-svn-id: http://moon:8086/svn/vhdl/trunk@210 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-06 10:14:38 +00:00
jens 0ed5461442 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@209 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 10:54:55 +00:00
jens c46a1caaf5 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@208 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 10:15:53 +00:00
jens 9c12bc9640 - added RAM-based architecture 
git-svn-id: http://moon:8086/svn/vhdl/trunk@207 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 10:06:37 +00:00
jens 90a889a5f8 - use RAM-based delayline 
git-svn-id: http://moon:8086/svn/vhdl/trunk@206 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 10:06:14 +00:00
jens 245c01ad45 - fixed missing CE at yout 
git-svn-id: http://moon:8086/svn/vhdl/trunk@205 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 09:32:43 +00:00
jens 9832fbfac9 - added dedicated DPRAM for COEFFS 
git-svn-id: http://moon:8086/svn/vhdl/trunk@204 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-05 09:32:27 +00:00
jens 650e5db110 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@203 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 16:34:02 +00:00
jens 58257266ad - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@202 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 16:14:14 +00:00
jens c10463c961 - removed reset from fir_stage_sys 
git-svn-id: http://moon:8086/svn/vhdl/trunk@201 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 16:13:58 +00:00
jens e4dc3e69a1 - fixed rdy-signal 
git-svn-id: http://moon:8086/svn/vhdl/trunk@200 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 15:31:46 +00:00
jens 9a756d4ca8 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@199 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 15:31:20 +00:00
jens f05c6bb829 - input data rate can be lower than filter 
git-svn-id: http://moon:8086/svn/vhdl/trunk@198 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 15:16:06 +00:00
jens fe60d9d7a4 - added shift_en input 
git-svn-id: http://moon:8086/svn/vhdl/trunk@197 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 15:15:54 +00:00
jens 9675773b2a - added ce 
git-svn-id: http://moon:8086/svn/vhdl/trunk@196 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 14:00:06 +00:00
jens 1738a6c0b6 - minor mods to accu_ld_pipe 
git-svn-id: http://moon:8086/svn/vhdl/trunk@195 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-04 13:56:07 +00:00
jens bc4c015150 - minor mods to vld_pipe 
git-svn-id: http://moon:8086/svn/vhdl/trunk@194 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-03 20:33:42 +00:00
jens d28b2225a7 - uses only fir_pkg and filter_pkg for FIR 
git-svn-id: http://moon:8086/svn/vhdl/trunk@193 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-03 20:13:55 +00:00
jens fcdbc0e601 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@192 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-03 20:06:07 +00:00
jens 690c6c24f6 - bug fix coef-pipe 
git-svn-id: http://moon:8086/svn/vhdl/trunk@191 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-03 20:05:04 +00:00
jens ba703d81df - simplification for coef-array 
git-svn-id: http://moon:8086/svn/vhdl/trunk@190 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:48:36 +00:00
jens 0ed3e397f2 - using fir_stage_sys instead of fir_stage 
git-svn-id: http://moon:8086/svn/vhdl/trunk@189 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:23:04 +00:00
jens eb818a15bb - added coef_latency 
git-svn-id: http://moon:8086/svn/vhdl/trunk@188 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:22:28 +00:00
jens a165d37bb7 - added coef_latency 
- y_dout registered


git-svn-id: http://moon:8086/svn/vhdl/trunk@187 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:22:12 +00:00
jens c574f7f0fd - moved fixed_array_t to fixed_util_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@186 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:21:11 +00:00
jens a10614df0a - fix ntaps_bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@185 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:20:48 +00:00
jens 5f1b2738de - moved real_array_t to fixed_util_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@184 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:20:21 +00:00
jens d7ed0a9fb0 - added CFIR 
git-svn-id: http://moon:8086/svn/vhdl/trunk@183 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:19:08 +00:00
jens 655cfb7f0d - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@182 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:18:38 +00:00
jens 55a702d6bd - moved real_array_t to fixed_util_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@181 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 16:07:16 +00:00
jens e8ddaf8d98 - added real veriants of NextPower... 
git-svn-id: http://moon:8086/svn/vhdl/trunk@180 cc03376c-175c-47c8-b038-4cd826a8556b
 2009-01-02 15:28:01 +00:00
jens 377b8c0993 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@179 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-31 15:54:51 +00:00
jens 8c652af1a7 - removed sproto-calls due to crashes in synth tools 
git-svn-id: http://moon:8086/svn/vhdl/trunk@178 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-31 11:23:50 +00:00
jens 18641b8411 - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@177 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 19:37:56 +00:00
jens dc63b8df76 - Ratio and gain are set at synthesis time (simpler) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@176 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 18:56:12 +00:00
jens 7c7fc19162 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@175 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 18:54:21 +00:00
jens c11d040f68 - added register after scaler 
git-svn-id: http://moon:8086/svn/vhdl/trunk@174 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 06:24:39 +00:00
jens 4cd2e0fd19 - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@173 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 06:04:19 +00:00
jens 61d5c40cd2 - uses ieee_proposed.fixed_pkg 
- din scaled to more fraction precision at integrator input.
  Number of integer bits are the same as din
- min_gain intrduced (reduces complexity of barrel shifter).
 Din always constant scaled by min_gain.


git-svn-id: http://moon:8086/svn/vhdl/trunk@172 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 06:03:56 +00:00
jens 75f8ddd340 - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@171 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 05:35:51 +00:00
jens 8136d54172 - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@170 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 05:21:52 +00:00
jens 50e4d2d32a - combine in/out_width to max_width 
- uses ieee_proposed.fixed_pkg


git-svn-id: http://moon:8086/svn/vhdl/trunk@169 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 04:39:46 +00:00
jens c45b123bdb - uses ieee_proposed.fixed_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@168 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 04:32:32 +00:00
jens 4fe3a1c636 - combine in/out_width to max_width 
- uses ieee_proposed.fixed_pkg


git-svn-id: http://moon:8086/svn/vhdl/trunk@167 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-30 04:32:07 +00:00
jens d9ba866ed0 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@166 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-29 14:05:12 +00:00
jens f7e19d3d44 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@165 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 21:43:27 +00:00
jens fb625665d2 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@164 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 19:04:18 +00:00
jens ef5da14068 - uses now fixed_util_pkg for common functions 
git-svn-id: http://moon:8086/svn/vhdl/trunk@163 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:55:15 +00:00
jens f3c6c4c644 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@162 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:49:28 +00:00
jens 64cb0bb426 - uses now fixed_util_pkg for common functions 
git-svn-id: http://moon:8086/svn/vhdl/trunk@161 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:48:15 +00:00
jens 4735454c40 - moved common functions to fixed_util_pkg 
git-svn-id: http://moon:8086/svn/vhdl/trunk@160 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:47:54 +00:00
jens 0e4e1b0fba - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@159 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:41:04 +00:00
jens d9961e9efb - use now non-debug-versions (NCO) for TB 
git-svn-id: http://moon:8086/svn/vhdl/trunk@158 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:35:52 +00:00
jens be85922612 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@157 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:35:44 +00:00
jens 1e9bed13e5 - added CIC-decimator 
git-svn-id: http://moon:8086/svn/vhdl/trunk@156 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:30:56 +00:00
jens 28bd8e959d - use now non-debug-versions (NCO, MIX) for TB 
git-svn-id: http://moon:8086/svn/vhdl/trunk@155 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:30:28 +00:00
jens 860e2984fd - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@154 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:29:13 +00:00
jens 13df4bbf12 - added generic for fractional number of bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@153 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:29:03 +00:00
jens 9a7ffd09ac - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@152 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-28 16:28:38 +00:00
jens 21e3023bfb - added generic for fractional number of bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@151 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 10:44:31 +00:00
jens 2903f5b7f1 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@150 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 09:59:41 +00:00
jens 6e65134b53 - added generic for fractional number of bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@149 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 09:57:01 +00:00
jens 4bb7087b60 - added generic for fractional number of bits 
git-svn-id: http://moon:8086/svn/vhdl/trunk@148 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 09:39:16 +00:00
jens de9ad2d469 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@147 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-22 09:38:44 +00:00
jens 988b2ed138 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@146 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 19:54:37 +00:00
jens 50af9fe70d - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@145 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 19:53:00 +00:00
jens bf78b1beef - added debug_mix_t 
git-svn-id: http://moon:8086/svn/vhdl/trunk@144 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 19:52:20 +00:00
jens fbee2fe578 - changed z-range default to 1.0 
git-svn-id: http://moon:8086/svn/vhdl/trunk@143 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 19:51:42 +00:00
jens 080e286b1c - fixed valid_out signal for gain_corr=disabled 
git-svn-id: http://moon:8086/svn/vhdl/trunk@142 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:39:05 +00:00
jens 32e4a933b9 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@141 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:38:05 +00:00
jens 15645ec096 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@140 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:21:10 +00:00
jens 776094e4b2 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@139 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:18:22 +00:00
jens 8e6affa627 - renamed 
git-svn-id: http://moon:8086/svn/vhdl/trunk@138 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:16:09 +00:00
jens 27b1d6a426 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@137 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:15:49 +00:00
jens bb5f153651 - reduced lower spur boundary 
git-svn-id: http://moon:8086/svn/vhdl/trunk@136 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-12-21 16:15:31 +00:00
jens a2e01a7966 - added Tpd to 'dout' for sim 
git-svn-id: http://moon:8086/svn/vhdl/trunk@135 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-11-05 09:34:56 +00:00
jens b4392a5c7a - added AC-97 controller 
git-svn-id: http://moon:8086/svn/vhdl/trunk@134 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-11-01 21:52:59 +00:00
jens 5091040c1d - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@133 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-11-01 21:48:26 +00:00
jens 755b318e7a - added AC-97 controller 
git-svn-id: http://moon:8086/svn/vhdl/trunk@132 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-11-01 21:47:15 +00:00
jens a41b5f572a - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@131 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-27 00:00:12 +00:00
jens ba2d02d4e6 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@130 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 23:52:49 +00:00
jens a14c98c05f - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@129 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 23:36:00 +00:00
jens 529658b710 - fixed some bugs 
git-svn-id: http://moon:8086/svn/vhdl/trunk@128 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 23:17:57 +00:00
jens 11129059e7 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@127 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 21:30:42 +00:00
jens 1f03bb3d41 - fixed some bugs 
git-svn-id: http://moon:8086/svn/vhdl/trunk@126 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 10:04:44 +00:00
jens b0a0e4ae6c - fixed some bugs 
git-svn-id: http://moon:8086/svn/vhdl/trunk@125 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 09:57:32 +00:00
jens c10be79075 - fixed some bugs 
git-svn-id: http://moon:8086/svn/vhdl/trunk@124 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-26 09:46:49 +00:00
jens 6b38a0acba - removed delay at color output. Fixes image problems. 
git-svn-id: http://moon:8086/svn/vhdl/trunk@123 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 20:11:03 +00:00
jens 84255df928 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@122 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 18:09:39 +00:00
jens 9954268b22 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@120 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:40:42 +00:00
jens 6597bccd01 - using now dpram_1w1r 
git-svn-id: http://moon:8086/svn/vhdl/trunk@119 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:26:07 +00:00
jens a6c7859e22 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@118 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:23:04 +00:00
jens 1c7fd9022e - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@117 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:20:15 +00:00
jens 5120448104 - using bui-generics for cache sizes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@116 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:16:21 +00:00
jens 8e41790680 - added generics for cache sizes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@115 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:16:05 +00:00
jens 08317c7744 - Removed DEADBEEF-garbage 
git-svn-id: http://moon:8086/svn/vhdl/trunk@114 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:09:13 +00:00
jens 9918af8a12 - Removed dirty-bit which is not needed by Direct-Mapped Cache 
git-svn-id: http://moon:8086/svn/vhdl/trunk@113 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 17:08:37 +00:00
jens 8102a16c3c - Removed linefifo 
- Uses now lib/FIFO/fifo_async.vhd


git-svn-id: http://moon:8086/svn/vhdl/trunk@112 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 12:27:38 +00:00
jens ed47f478f8 - Switched to 64-Bit SDRAM- and VGA-controller 
git-svn-id: http://moon:8086/svn/vhdl/trunk@110 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:48:04 +00:00
jens 7cdfa6929d - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@109 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:26:06 +00:00
jens 16b4f2b138 - Bugfix: changed 'ptr_r' from 'bcnt_r' to 'bnxt_r' to prevent read delay when FIFO is read (re = 1) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@108 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:21:47 +00:00
jens 7ccefbab86 - Removed linefifo 
- Uses now lib/FIFO/fifo_async.vhd


git-svn-id: http://moon:8086/svn/vhdl/trunk@107 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:15:26 +00:00
jens 5abe0f9234 -Removed linefifo.vhd and dpram.vhd 
- Uses now lib/FIFO/fifo_async.vhd


git-svn-id: http://moon:8086/svn/vhdl/trunk@106 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:14:50 +00:00
jens 29eb6a05c3 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@105 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 11:11:52 +00:00
jens 2c95fae0ab - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@104 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 00:23:56 +00:00
jens 545379c99d - added conversion functions unsigned <=> color_t 
git-svn-id: http://moon:8086/svn/vhdl/trunk@103 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-25 00:15:29 +00:00
jens 533a0bd328 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@102 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-24 20:56:28 +00:00
jens b81ce94c39 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@101 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-24 20:56:13 +00:00
jens 48c7618752 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@100 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 22:06:41 +00:00
jens 5c63d629a7 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@99 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 22:06:34 +00:00
jens 36e8cd1e00 - Using MODELSIM_HOME environment variable 
git-svn-id: http://moon:8086/svn/vhdl/trunk@98 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 21:21:24 +00:00
jens c90b63d476 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@97 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 21:20:28 +00:00
jens 41593cbc54 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@96 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-23 09:49:42 +00:00
jens 0bba7d2e10 - added area constraint for "inst_mips_top" 
git-svn-id: http://moon:8086/svn/vhdl/trunk@95 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-22 09:47:34 +00:00
jens a5f0a35f80 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@94 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 19:32:11 +00:00
jens 5bd0c6ea4a - Update 
git-svn-id: http://moon:8086/svn/vhdl/trunk@93 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 19:29:57 +00:00
jens 1929d9374e - Removed User ROM stuff 
git-svn-id: http://moon:8086/svn/vhdl/trunk@92 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 18:52:14 +00:00
jens c9900e509a - Loading app from Flash instead User ROM 
- Removed User ROM


git-svn-id: http://moon:8086/svn/vhdl/trunk@91 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 18:24:56 +00:00
jens 029bf8eb22 - changed some directories 
git-svn-id: http://moon:8086/svn/vhdl/trunk@90 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 18:24:03 +00:00
jens 8060efb864 - Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@89 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 18:23:29 +00:00
jens 3f62f79d12 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@88 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-21 17:23:58 +00:00
jens fdc3664187 Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@87 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-20 19:26:51 +00:00
jens 69697d7222 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@86 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-20 19:26:01 +00:00
jens 419ccc4edf Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@85 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-20 19:11:30 +00:00
jens b67911c65d - added TM_NET for DDR-clock 
git-svn-id: http://moon:8086/svn/vhdl/trunk@84 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-20 09:55:32 +00:00
jens e9e132b3e6 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@83 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:53:51 +00:00
jens 32cbb4fc13 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@82 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:29:45 +00:00
jens 9e404bfb06 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@81 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:12:34 +00:00
jens 0ea7ced5e3 - Removed linefifo and clockgen (=> frontend and top) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@80 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:11:46 +00:00
jens de0a8c6e17 Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@79 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 21:10:51 +00:00
jens f59e4dd7d1 - Added Sync. SRAM 
git-svn-id: http://moon:8086/svn/vhdl/trunk@78 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 20:23:27 +00:00
jens 85bf744892 - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@77 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 20:13:28 +00:00
jens 891e764a23 - Added VGA 
git-svn-id: http://moon:8086/svn/vhdl/trunk@76 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 20:03:28 +00:00
jens 20b3bfb41b - Added Sync. SRAM 
git-svn-id: http://moon:8086/svn/vhdl/trunk@75 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-19 20:02:45 +00:00
jens 8a8adce98e - using now 64-bit SDR interface (2 SDRAMS) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@74 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 13:31:15 +00:00
jens 051b4182f1 - Cleaned up 
git-svn-id: http://moon:8086/svn/vhdl/trunk@73 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 12:49:30 +00:00
jens 3685973be8 - using now 64-bit SDR interface (2 SDRAMS) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@72 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 11:37:01 +00:00
jens b656e2890b Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@71 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 11:36:33 +00:00
jens f50a47246a - introduced per-bank activation (avoids multiple activations on same bank) 
- some other improvements


git-svn-id: http://moon:8086/svn/vhdl/trunk@70 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-18 11:36:07 +00:00
jens c104c6e67d - Intital revision 
git-svn-id: http://moon:8086/svn/vhdl/trunk@68 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 17:41:44 +00:00
jens c96015bbad - Removed distributed DPRAM reference 
git-svn-id: http://moon:8086/svn/vhdl/trunk@67 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 17:41:15 +00:00
jens fe372f0efa - Removed registered CYC_O (didn't work) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@66 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 17:35:07 +00:00
jens 61b2095bf8 - Shortened read cycles 
- Minor improvements


git-svn-id: http://moon:8086/svn/vhdl/trunk@65 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 14:26:02 +00:00
jens 329c639c1a - Shortened BUS-cycle by one clock 
git-svn-id: http://moon:8086/svn/vhdl/trunk@64 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 14:25:30 +00:00
jens f8962066f0 - Registered CYC_O 
git-svn-id: http://moon:8086/svn/vhdl/trunk@63 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-17 13:39:07 +00:00
jens 1c499c6b34 - Added VGA master/slave 
git-svn-id: http://moon:8086/svn/vhdl/trunk@62 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-16 23:12:14 +00:00
jens 225e0d5eeb - Added VGA component 
git-svn-id: http://moon:8086/svn/vhdl/trunk@61 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-15 21:55:34 +00:00
jens f960a13953 Simplified 
git-svn-id: http://moon:8086/svn/vhdl/trunk@60 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-15 11:16:47 +00:00
jens c8da959dbb - Moved to lib/FIFO 
git-svn-id: http://moon:8086/svn/vhdl/trunk@59 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 17:12:22 +00:00
jens 78db345b82 - Intital revision 
- Moved from SDRAM v1.5 to here


git-svn-id: http://moon:8086/svn/vhdl/trunk@58 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 17:11:50 +00:00
jens fda12e53c3 - Uses now full capacity of SDRAM (64-Bit interface on ML-402) 
- Removed read data mask


git-svn-id: http://moon:8086/svn/vhdl/trunk@57 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 17:09:30 +00:00
jens 40d96126e7 - Removed read data mask 
git-svn-id: http://moon:8086/svn/vhdl/trunk@56 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 17:07:48 +00:00
jens 959217a81c Minor changes 
git-svn-id: http://moon:8086/svn/vhdl/trunk@55 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-14 14:55:15 +00:00
jens 91347dd60e - Output pre_empty and pre_full for safer DPRAM control 
git-svn-id: http://moon:8086/svn/vhdl/trunk@54 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-12 18:04:36 +00:00
jens 3be3800dc7 Registered rdy (better timing) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@53 cc03376c-175c-47c8-b038-4cd826a8556b
 2008-10-12 14:12:14 +00:00
229 changed files with 18151 additions and 18583 deletions
Expand all files Collapse all files
lib/CPUs/JCpu/sim/ModelSim SE .lnk
BIN
View File
Binary file not shown.
lib/CPUs/MIPS/sim/ModelSim SE .lnk
BIN
View File
Binary file not shown.
lib/CPUs/MIPS/sim/compile_simprim.do
-6
View File
@@ -1,6 +0,0 @@
vlib simprim
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
lib/CPUs/MIPS/sim/compile_unisim.do
-6
View File
@@ -1,6 +0,0 @@
vlib unisim
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo
-13
View File
@@ -1,13 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/tb_eval_muldiv.vhd"
vsim -t 1ps -lib work tb_eval_muldiv
do {tb_eval_muldiv.wdo}
view wave
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo
-27
View File
@@ -1,27 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_eval_muldiv/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result
add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0}
configure wave -namecolwidth 149
configure wave -valuecolwidth 171
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {2520 ns}
lib/CPUs/MIPS/sim/tb_mips_embedded.fdo
-22
View File
@@ -1,22 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
vcom -explicit -93 "../src/core/mips_reg.vhd"
vcom -explicit -93 "../src/core/mips_shifter.vhd"
vcom -explicit -93 "../src/core/mips_alu.vhd"
vcom -explicit -93 "../src/core/mips_bcu.vhd"
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
vcom -explicit -93 "../src/core/mips_top.vhd"
vcom -explicit -93 "../src/ram.vhd"
vcom -explicit -93 "../asm/fibonacci.vhd"
vcom -explicit -93 "../src/mips_embedded.vhd"
vcom -explicit -93 "../src/tb_mips_embedded.vhd"
vsim -t 1ps -lib work tb_mips_embedded
do {tb_mips_embedded.wdo}
view wave
view structure
view signals
run 20us
lib/CPUs/MIPS/sim/tb_mips_embedded.wdo
-41
View File
@@ -1,41 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_embedded/rst
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Logic /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/exception
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_ram/sram
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_dout
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_re
add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_din
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/wb_stage
add wave -noupdate -format Logic /tb_mips_embedded/clk
add wave -noupdate -format Literal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/hdu
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {624000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {2520 ns}
lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo
-31
View File
@@ -1,31 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
vcom -explicit -93 "../src/core/mips_reg.vhd"
vcom -explicit -93 "../src/core/mips_shifter.vhd"
vcom -explicit -93 "../src/core/mips_alu.vhd"
vcom -explicit -93 "../src/core/mips_bcu.vhd"
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
vcom -explicit -93 "../src/core/mips_muldiv.vhd"
vcom -explicit -93 "../src/core/mips_cop.vhd"
vcom -explicit -93 "../src/core/mips_bui.vhd"
vcom -explicit -93 "../src/core/mips_top.vhd"
vcom -explicit -93 "../src/core/dcache.vhd"
vcom -explicit -93 "../asm/testbench.ROM.vhd"
vcom -explicit -93 "../src/mips_embedded.vhd"
vcom -explicit -93 "../src/mips_embedded_syn.vhd"
vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../uart/uart_rx.vhd"
vcom -explicit -93 "../../../uart/uart_tx.vhd"
vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd"
vsim -t 1ps -lib work tb_mips_embedded_syn
do {tb_mips_embedded_syn.wdo}
view wave
view structure
view signals
run 100us
lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo
-13
View File
@@ -1,13 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../syn/ise9/netgen/par/mips_embedded_syn_timesim.vhd"
vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd"
vsim -t 1ps -sdfmax "/uut=../syn/ise9/netgen/par/mips_embedded_syn_timesim.sdf" -lib work tb_mips_embedded_syn
do {tb_mips_embedded_syn.wdo}
view wave
#add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo
-112
View File
@@ -1,112 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_rx
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_tx
add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_rst_n_in
add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_clk_in
add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_led
add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_dip
add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_btn
add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_error
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_rst
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_run
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_tx
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_ctrl
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_baud
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/uart_status_port
add wave -noupdate -format Literal -radix decimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_sec
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_rdy
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_en
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_re
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_dout
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_bui/s
add wave -noupdate -divider DMEM
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_dout
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_en
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_we
add wave -noupdate -divider IMEM
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/imem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_din
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_en
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc_run
add wave -noupdate -divider PC
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/hdu
add wave -noupdate -divider Stages
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/halt
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_reg_dual_a/reg_mem
add wave -noupdate -divider Cop
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ir_valid
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_id
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_ex
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_ex_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_entered
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/epc
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cause
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/events
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/eflags
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/badvaddr
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/rst
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exception
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_save
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_rest
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_strobe
add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ip
add wave -noupdate -divider Stages
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_dout
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/wb_stage
add wave -noupdate -divider Muldiv
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/result
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/start
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/busy
add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/hilo_sel
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_hi
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_lo
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1121030000 ps} 0} {{Cursor 2} {1436367 ps} 0} {{Cursor 3} {1122030000 ps} 0}
configure wave -namecolwidth 179
configure wave -valuecolwidth 89
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {1351336 ps} {1583596 ps}
lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo
+1 -1
View File
@@ -12,4 +12,4 @@ view wave
view structure
view signals
run 5000us
run 8ms
lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo
-19
View File
@@ -1,19 +0,0 @@
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit -93 "../syn/eval_muldiv/netgen/translate/muldiv_translate.vhd"
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/tb_mips_muldiv.vhd"
vsim -t 1ps -lib work tb_mips_muldiv
#do {tb_mips_muldiv.udo}
view wave
add wave *
view structure
view signals
run 1000ns
## End
lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo
-19
View File
@@ -1,19 +0,0 @@
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit -93 "../syn/eval_muldiv/netgen/synthesis/muldiv_synthesis.vhd"
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/tb_mips_muldiv.vhd"
vsim -t 1ps -lib work tb_mips_muldiv
do {tb_mips_muldiv.wdo}
view wave
#add wave *
view structure
view signals
run 1000ns
## End
lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo
+5 -6
View File
@@ -6,16 +6,15 @@ add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn
add wave -noupdate -format Logic /tb_mips_muldiv/start
add wave -noupdate -format Logic /tb_mips_muldiv/busy
add wave -noupdate -format Logic /tb_mips_muldiv/s_un
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/result
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/md_result
add wave -noupdate -format Logic /tb_mips_muldiv/check
add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
@@ -62,7 +61,7 @@ add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {1278050000 ps} 0}
WaveRestoreCursors {{Cursor 1} {7735999838 ps} 0} {{Cursor 2} {512321 ps} 0}
configure wave -namecolwidth 149
configure wave -valuecolwidth 171
configure wave -justifyvalue left
@@ -76,4 +75,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {5250 us}
WaveRestoreZoom {0 ps} {8400 us}
lib/CPUs/MIPS/sim/tb_mips_top.fdo
+19 -2
View File
@@ -1,18 +1,35 @@
## NOTE: Do not edit this file.
##
vlib work
# Misc
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
# RAMS
vcom -explicit -93 "../../../misc/dpram_2w2r.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
# FIFOS
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd"
# MIPS
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
vcom -explicit -93 "../src/core/mips_reg.vhd"
vcom -explicit -93 "../src/core/mips_shifter.vhd"
vcom -explicit -93 "../src/core/mips_alu.vhd"
vcom -explicit -93 "../src/core/mips_muldiv.vhd"
vcom -explicit -93 "../src/core/mips_cop.vhd"
vcom -explicit -93 "../src/core/mips_icache.vhd"
vcom -explicit -93 "../src/core/mips_dcache.vhd"
vcom -explicit -93 "../src/core/mips_biu.vhd"
vcom -explicit -93 "../src/core/mips_bcu.vhd"
vcom -explicit -93 "../src/core/mips_pipeline.vhd"
vcom -explicit -93 "../src/core/mips_top.vhd"
vcom -explicit -93 "../asm/fibonacci.vhd"
vcom -explicit -93 "../src/ram.vhd"
vcom -explicit -93 "../src/tb_mips_top.vhd"
vsim -t 1ps -lib work tb_mips_top
do {tb_mips_top.wdo}
lib/CPUs/MIPS/sim/tb_mips_top.mdo
-18
View File
@@ -1,18 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
## Compile Post-Map Model
vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_map.vhd"
vsim -t 1ps -sdfmax "/mips_top=../syn/ise9/netgen/map/mips_top_map.sdf" -lib work mips_top
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/irom_hello.vhd"
vcom -explicit -93 "../src/tb_mips_top.vhd"
vsim -t 1ps -lib work tb_mips_top
do {tb_mips_top.mwdo}
view wave
#add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_mips_top.mwdo
-31
View File
@@ -1,31 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_top/rst
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Logic /tb_mips_top/ce
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
add wave -noupdate -format Logic /tb_mips_top/dmem_we
add wave -noupdate -format Logic /tb_mips_top/dmem_re
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_op2
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_result
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {77481 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {729730 ps}
lib/CPUs/MIPS/sim/tb_mips_top.sdo
-16
View File
@@ -1,16 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../syn/ise9/netgen/synthesis/mips_top_synthesis.vhd"
vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/irom_hello.vhd"
vcom -explicit -93 "../src/tb_mips_top.vhd"
vsim -t 1ps -lib work tb_mips_top
#do {tb_mips_top.wdo}
view wave
add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/sim/tb_mips_top.wdo
+16 -25
View File
@@ -1,40 +1,31 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mips_top/rst
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Logic /tb_mips_top/cpu_halt
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
add wave -noupdate -format Logic /tb_mips_top/dmem_re
add wave -noupdate -format Logic /tb_mips_top/dmem_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram
add wave -noupdate -divider {TOP interface}
add wave -noupdate -format Literal /tb_mips_top/debug
add wave -noupdate -format Logic /tb_mips_top/rst_i
add wave -noupdate -format Logic /tb_mips_top/clk_i
add wave -noupdate -format Logic /tb_mips_top/ack_i
add wave -noupdate -format Logic /tb_mips_top/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
add wave -noupdate -format Logic /tb_mips_top/we_o
add wave -noupdate -format Literal /tb_mips_top/sel_o
add wave -noupdate -format Logic /tb_mips_top/cyc_o
add wave -noupdate -format Logic /tb_mips_top/stb_o
add wave -noupdate -format Logic /tb_mips_top/mrdy_o
add wave -noupdate -format Literal /tb_mips_top/int
add wave -noupdate -divider ALU
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -divider PC
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall
add wave -noupdate -divider PC
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
add wave -noupdate -format Logic /tb_mips_top/clk
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
WaveRestoreCursors {{Cursor 1} {21313433 ps} 0}
configure wave -namecolwidth 188
configure wave -valuecolwidth 100
configure wave -justifyvalue left
lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo
-17
View File
@@ -1,17 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
## Compile Post-Map Model
vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_syn_map.vhd"
vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/map/mips_top_syn_map.sdf" -lib work mips_top_syn
vcom -explicit -93 "../src/core/mips_types.vhd"
vcom -explicit -93 "../src/core/mips_instr.vhd"
vcom -explicit -93 "../src/irom_hello.vhd"
vcom -explicit -93 "../src/tb_mips_top_syn.vhd"
vsim -t 1ps -lib work tb_mips_top_syn
do {tb_mips_top_syn.wdo}
view wave
#add wave *
view structure
view signals
run 2400ns
lib/CPUs/MIPS/src/core/dcache.vhd
+5 -10
View File
@@ -92,14 +92,13 @@ END COMPONENT;
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
constant tag_parity_width : natural := 3;
constant tram_data_width : natural := 2 + tag_parity_width + tag_width;
constant tram_data_width : natural := 1 + tag_parity_width + tag_width;
constant tram_addr_width : natural := cache_index_width;
subtype tram_data_t is unsigned (tram_data_width-1 downto 0);
type dcache_entry_t is record
valid : std_logic;
dirty : std_logic;
tv_p : unsigned(tag_parity_width-1 downto 0);
tag : unsigned(tag_width-1 downto 0);
end record;
@@ -112,9 +111,8 @@ END COMPONENT;
variable result : dcache_entry_t;
begin
result.valid := x(0);
result.dirty := x(1);
result.tv_p := x(4 downto 2);
result.tag := x(tag_width+4 downto 5);
result.tv_p := x(3 downto 1);
result.tag := x(tag_width+3 downto 4);
return result;
end to_dcache_entry;
@@ -123,9 +121,8 @@ END COMPONENT;
variable result : tram_data_t;
begin
result(0) := x.valid;
result(1) := x.dirty;
result(4 downto 2) := x.tv_p;
result(tag_width+4 downto 5) := x.tag;
result(3 downto 1) := x.tv_p;
result(tag_width+3 downto 4) := x.tag;
return result;
end to_tram_data;
@@ -321,7 +318,6 @@ cache_state:
cache_entry_in.tv_p <= (others => '0');
cache_entry_in.tag <= tag_index_reg;
cache_entry_in.valid <= '0';
cache_entry_in.dirty <= '0';
sn <= s;
case s is
@@ -378,7 +374,6 @@ cache_state:
end if;
end if;
when upd_cache =>
CYC_O <= '1';
tram_addr_wr <= cache_index_reg;
tram_we <= '1';
cache_entry_in.valid <= '1';
lib/CPUs/MIPS/src/core/icache.vhd
-2
View File
@@ -296,14 +296,12 @@ cache_state:
end if;
end if;
when upd_cache =>
CYC_O <= '1';
tag_ram_addr_wr <= cache_index_reg;
tag_ram_we <= '1';
cache_entry_in.valid <= '1';
sn <= rd_cache;
when rd_cache =>
-- CYC_O <= '1';
tag_ram_re <= '1';
data_ram_re <= '1';
was_miss <= '1';
lib/CPUs/MIPS/src/core/mips_bui.vhd
+36 -20
View File
@@ -28,7 +28,12 @@ use IEEE.numeric_std.ALL;
library work;
use work.mips_types.all;
entity bui is
entity biu is
Generic
(
icache_size : natural := 2048; -- words
dcache_size : natural := 2048 -- words
);
Port
(
RST_I : in STD_LOGIC;
@@ -57,15 +62,15 @@ entity bui is
cpu_dmem_din : out word_t;
cpu_dmem_addr : in word_t
);
end bui;
end biu;
architecture behavior of bui is
architecture behavior of biu is
COMPONENT icache
GENERIC
(
cache_size : natural := 2048; -- words
line_size : natural := 8 -- words
cache_size : natural; -- words
line_size : natural -- words
);
PORT
(
@@ -88,8 +93,8 @@ architecture behavior of bui is
COMPONENT dcache
GENERIC
(
cache_size : natural := 2048; -- words
line_size : natural := 8 -- words
cache_size : natural; -- words
line_size : natural -- words
);
PORT
(
@@ -182,11 +187,28 @@ architecture behavior of bui is
alias write_fifo_data_out is write_fifo_dout(63 downto 32);
alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
signal read_cycle : std_logic;
begin
MRDY_O <= '1';
CYC_O <= not bout_fifo_empty or dmem_mem_rd_gnt or dcache_mem_gnt or icache_mem_gnt;
read_cyc_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
read_cycle <= '0';
else
read_cycle <= (dmem_mem_rd_gnt and CYC_O_dmem_rd)
or (dcache_mem_gnt and CYC_O_dcache)
or (icache_mem_gnt and CYC_O_icache);
end if;
end if;
end process;
CYC_O <= not bout_fifo_empty or read_cycle;
STB_O <= not bout_fifo_empty;
ADDR_O <= bout_fifo_addr_out;
DAT_O <= bout_fifo_data_out;
@@ -200,7 +222,7 @@ begin
inst_icache : icache
GENERIC MAP
(
cache_size => 2048, -- words
cache_size => icache_size, -- words
line_size => 8
)
PORT MAP
@@ -225,7 +247,7 @@ inst_icache : icache
inst_dcache : dcache
GENERIC MAP
(
cache_size => 2048, -- words
cache_size => dcache_size, -- words
line_size => 8
)
PORT MAP
@@ -255,7 +277,7 @@ inst_dcache : dcache
dcache_en <= cpu_dmem_en and not busy;
-- Instantiate synchronous FIFO
inst_bout_fifo: entity work.fifo_sync
inst_bout_fifo: entity work.fifo_sync_dist
GENERIC MAP
(
addr_width => 4,
@@ -277,11 +299,7 @@ inst_bout_fifo: entity work.fifo_sync
bout_rdy <= not bout_fifo_full;
bout_fifo_re <= not bout_fifo_empty and SRDY_I;
bout_fifo_we <= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
STB_O_dcache when dcache_mem_gnt = '1' else
STB_O_icache when icache_mem_gnt = '1' else '0';
bout_fifo_we <= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
bout_fifo_data_in <= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
@@ -294,13 +312,11 @@ inst_bout_fifo: entity work.fifo_sync
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
-- Instantiate synchronous FIFO
inst_write_fifo: entity work.fifo_sync
inst_write_fifo: entity work.fifo_sync_dist
GENERIC MAP
(
addr_width => 4,
data_width => 68,
almost_full_thresh => 12,
almost_empty_thresh => 4
data_width => 68
)
PORT MAP
(
lib/CPUs/MIPS/src/core/mips_cop.vhd
+2 -2
View File
@@ -338,10 +338,10 @@ cop_register_read:
reg := test_reg;
when others =>
reg := X"DEADBEEF";
reg := (others => '-');
end case;
dout <= reg;
dout <= reg after 1 ns;
end if;
end process;
lib/CPUs/MIPS/src/core/mips_top.vhd
+12 -2
View File
@@ -88,7 +88,12 @@ architecture rtl of mips_top is
signal dmem_be : unsigned(3 downto 0);
COMPONENT bui
COMPONENT biu
GENERIC
(
icache_size : natural;
dcache_size : natural
);
PORT
(
RST_I : in STD_LOGIC;
@@ -147,7 +152,12 @@ inst_pipeline: pipeline
dmem_dout => dmem_dout
);
inst_bui: bui
inst_biu: biu
GENERIC MAP
(
icache_size => 4096, -- words
dcache_size => 4096 -- words
)
PORT MAP
(
RST_I => RST_I,
lib/CPUs/MIPS/src/mips_muldiv.vhd
-83
View File
@@ -1,83 +0,0 @@
--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: The arithmetic logic unit
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.mips_types.all;
entity muldiv is
Port
(
rst : in std_logic;
clk : in std_logic;
din_vld_hi : in std_logic;
din_vld_lo : in std_logic;
din_hi : in word_t;
din_lo : in word_t;
hilo_sel : in std_logic;
dout : out word_t
);
end muldiv;
architecture Behavioral of muldiv is
signal reg_hi, reg_lo : word_t;
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
proc_reg_out:
process(hilo_sel, reg_hi, reg_lo)
begin
if hilo_sel = '1' then
dout <= reg_hi;
else
dout <= reg_lo;
end if;
end process;
proc_reg_in:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_hi <= (others => '0');
reg_lo <= (others => '0');
elsif din_vld_hi = '1' then
if hilo_sel = '1' then
reg_hi <= din_hi;
else
reg_lo <= din_hi;
end if;
end if;
if din_vld_lo = '1' then
reg_lo <= din_lo;
end if;
end if;
end process;
--------------------------------------------------------------------------
end Behavioral;
lib/CPUs/MIPS/src/tb_eval_muldiv.vhd
-156
View File
@@ -1,156 +0,0 @@
-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: Testbench for JCPU
-- also writes 'opc.lst' for JASM-assembler
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.mips_types.all;
use work.mips_instr.all;
ENTITY tb_eval_muldiv IS
END tb_eval_muldiv;
ARCHITECTURE behavior OF tb_eval_muldiv IS
constant CLK_PERIOD : time := 10 ns;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal ce : std_logic := '0';
signal mul_divn : std_logic := '1';
signal op_valid : std_logic := '0';
signal op1_in : word_t := (others => '-');
signal op2_in : word_t := (others => '-');
signal result : unsigned (2*word_t'length-1 downto 0);
signal res_valid : std_logic;
signal busy : std_logic;
signal result_reg : unsigned (2*word_t'length-1 downto 0);
subtype pp_t is unsigned (39 downto 0);
signal pp0, pp1, pp2, pp3 : pp_t;
signal signed_mul : std_logic := '1';
signal sign1 : std_logic;
signal sign2 : std_logic;
signal cy : std_logic;
BEGIN
sign1 <= signed_mul and op1_in(op1_in'left);
sign2 <= signed_mul and op2_in(op1_in'left);
cy <= sign1;
pp0 <= op1_in * op2_in(7 downto 0);
pp1 <= op1_in * op2_in(15 downto 8);
pp2 <= op1_in * op2_in(23 downto 16);
pp3 <= op1_in * op2_in(31 downto 24);
result <= ((63 downto 40 => '0') & pp0)
+ ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0'))
+ ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0'))
+ (pp3 & (23 downto 0 => '0'));
result_reg <= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000"));
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
rst <= '0';
wait for 10*CLK_PERIOD;
wait until rising_edge(clk);
ce <= '1';
wait for 10*CLK_PERIOD;
op1_in <= X"FFFF_FFFA"; -- (-6)
op2_in <= X"0000_0005"; -- (+5)
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"0000_0006"; -- (+6)
op2_in <= X"FFFF_FFFB"; -- (-5)
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"1234_5678";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"1234_5678";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"1234_5678";
op2_in <= X"1234_5678";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"789A_BCDE";
op2_in <= X"8765_4321";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait for 10*CLK_PERIOD;
op1_in <= X"8765_4321";
op2_in <= X"789A_BCDE";
op_valid <= '1';
wait until rising_edge(clk);
op_valid <= '0';
wait;
end process;
END;
lib/CPUs/MIPS/src/tb_mips_muldiv.vhd
+56 -32
View File
@@ -63,12 +63,14 @@ ARCHITECTURE behavior OF tb_mips_muldiv IS
signal start : std_logic := '0';
signal din_hi : word_t := (others => '-');
signal din_lo : word_t := (others => '-');
signal ref_hi : word_t := (others => '-');
signal ref_lo : word_t := (others => '-');
signal dout : word_t;
signal hilo_sel : std_logic := '0';
signal result : unsigned (2*word_t'length-1 downto 0);
signal md_result : unsigned (2*word_t'length-1 downto 0) := (others => '0');
signal ref_result : unsigned (2*word_t'length-1 downto 0);
signal ref_hi : unsigned (word_t'length-1 downto 0);
signal rtmp : unsigned (2*word_t'length-1 downto 0);
signal tmp2 : unsigned (word_t'length-1 downto 0);
signal check : std_logic;
type word_array_t is array (natural range <>) of word_t;
@@ -164,35 +166,31 @@ CLK_GEN: process
end process;
REF_GEN: process
variable tmp : unsigned (2*word_t'length-1 downto 0);
variable tmp2 : unsigned (word_t'length-1 downto 0);
begin
if mul_divn = '0' then
wait until rising_edge(clk) and start = '1';
ref_lo <= din_lo;
ref_hi <= din_hi;
wait until rising_edge(clk) and busy = '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk) and check = '1';
if s_un = '1' then
tmp := unsigned(signed(result(31 downto 0)) * signed(ref_lo));
tmp2 := unsigned(signed(tmp(31 downto 0)) + signed(result(63 downto 32)));
ref_result <= X"00000000" & tmp2(31 downto 0);
rtmp <= unsigned(signed(md_result(31 downto 0)) * signed(din_lo));
wait until rising_edge(clk);
tmp2 <= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32)));
wait until rising_edge(clk);
ref_hi <= tmp2(31 downto 0);
else
tmp := result(31 downto 0) * ref_lo;
tmp2 := tmp(31 downto 0) + result(63 downto 32);
ref_result <= X"00000000" & tmp2(31 downto 0);
rtmp <= md_result(31 downto 0) * din_lo;
wait until rising_edge(clk);
tmp2 <= rtmp(31 downto 0) + md_result(63 downto 32);
wait until rising_edge(clk);
ref_hi <= tmp2(31 downto 0);
end if;
wait until rising_edge(clk);
if ref_lo /= X"00000000" then
if din_lo /= X"00000000" then
if ENABLE_FAIL_REPORT then
assert ref_hi = ref_result(31 downto 0) report "Error on divison" severity failure;
assert din_hi = ref_hi report "Error on divison" severity failure;
end if;
end if;
else
wait until rising_edge(clk) and start = '1';
wait until rising_edge(clk) and busy = '0';
wait until rising_edge(clk) and check = '1';
if s_un = '1' then
ref_result <= unsigned(signed(din_hi) * signed(din_lo));
else
@@ -202,7 +200,7 @@ REF_GEN: process
wait until rising_edge(clk);
wait until rising_edge(clk);
if ENABLE_FAIL_REPORT then
assert ref_result = result report "Error on multiplication" severity failure;
assert ref_result = md_result report "Error on multiplication" severity failure;
end if;
end if;
@@ -221,6 +219,7 @@ STIMULUS: process
s_un <= '0';
for i in 0 to operands'length-1 loop
for j in 0 to operands'length-1 loop
check <= '0';
wait until rising_edge(clk) and busy = '0';
din_hi <= operands(i);
din_lo <= operands(j);
@@ -231,17 +230,23 @@ STIMULUS: process
-- Read result
wait until rising_edge(clk) and busy = '0';
result(31 downto 0) <= dout;
wait until rising_edge(clk);
md_result(31 downto 0) <= dout;
wait until rising_edge(clk);
hilo_sel <= '1';
wait until rising_edge(clk);
result(63 downto 32) <= dout;
wait for 2*CLK_PERIOD;
md_result(63 downto 32) <= dout;
check <= '1';
wait until rising_edge(clk);
check <= '0';
wait for 8*CLK_PERIOD;
end loop;
end loop;
s_un <= '1';
for i in 0 to operands'length-1 loop
for j in 0 to operands'length-1 loop
check <= '0';
wait until rising_edge(clk) and busy = '0';
din_hi <= operands(i);
din_lo <= operands(j);
@@ -252,11 +257,16 @@ STIMULUS: process
-- Read result
wait until rising_edge(clk) and busy = '0';
result(31 downto 0) <= dout;
wait until rising_edge(clk);
md_result(31 downto 0) <= dout;
wait until rising_edge(clk);
hilo_sel <= '1';
wait until rising_edge(clk);
result(63 downto 32) <= dout;
wait for 2*CLK_PERIOD;
md_result(63 downto 32) <= dout;
check <= '1';
wait until rising_edge(clk);
check <= '0';
wait for 8*CLK_PERIOD;
end loop;
end loop;
@@ -264,6 +274,7 @@ STIMULUS: process
s_un <= '0';
for i in 0 to operands'length-1 loop
for j in 0 to operands'length-1 loop
check <= '0';
wait until rising_edge(clk) and busy = '0';
din_hi <= operands(i);
din_lo <= operands(j);
@@ -274,16 +285,23 @@ STIMULUS: process
-- Read result
wait until rising_edge(clk) and busy = '0';
result(31 downto 0) <= dout;
wait until rising_edge(clk);
md_result(31 downto 0) <= dout;
wait until rising_edge(clk);
hilo_sel <= '1';
wait until rising_edge(clk);
result(63 downto 32) <= dout;
md_result(63 downto 32) <= dout;
check <= '1';
wait until rising_edge(clk);
check <= '0';
wait for 8*CLK_PERIOD;
end loop;
end loop;
s_un <= '1';
for i in 0 to operands'length-1 loop
for j in 0 to operands'length-1 loop
check <= '0';
wait until rising_edge(clk) and busy = '0';
din_hi <= operands(i);
din_lo <= operands(j);
@@ -294,10 +312,16 @@ STIMULUS: process
-- Read result
wait until rising_edge(clk) and busy = '0';
result(31 downto 0) <= dout;
wait until rising_edge(clk);
md_result(31 downto 0) <= dout;
wait until rising_edge(clk);
hilo_sel <= '1';
wait until rising_edge(clk);
result(63 downto 32) <= dout;
md_result(63 downto 32) <= dout;
check <= '1';
wait until rising_edge(clk);
check <= '0';
wait for 8*CLK_PERIOD;
end loop;
end loop;
lib/CPUs/MIPS/src/tb_mips_top.vhd
+47 -105
View File
@@ -37,136 +37,78 @@ END tb_mips_top;
ARCHITECTURE behavior OF tb_mips_top IS
COMPONENT mips_top
Port
PORT
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
halt : in STD_LOGIC;
imem_din : in unsigned (WORD_WIDTH-1 downto 0);
imem_addr : out unsigned (WORD_WIDTH-1 downto 0);
dmem_we : out STD_LOGIC;
dmem_re : out STD_LOGIC;
dmem_din : in unsigned (WORD_WIDTH-1 downto 0);
dmem_dout : out unsigned (WORD_WIDTH-1 downto 0);
dmem_addr : out unsigned (WORD_WIDTH-1 downto 0)
);
END COMPONENT;
COMPONENT rom
Port
(
clk : in STD_LOGIC;
addr : in word_t;
dout : out word_t
);
END COMPONENT;
COMPONENT ram
Generic
(
word_addr_width : integer
);
Port
(
clk : in STD_LOGIC;
we : in STD_LOGIC;
addr : in word_t;
din : in word_t;
dout : out word_t
debug : out unsigned(1 downto 0);
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
DAT_O : out word_t;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC;
INT : in unsigned (5 downto 0)
);
END COMPONENT;
constant CLK_PERIOD : time := 10 ns;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal cpu_halt : std_logic;
signal irom_data : word_t := (others => '-');
signal irom_addr : word_t;
signal dmem_din : word_t := (others => '-');
signal dmem_dout : word_t;
signal dmem_addr : word_t;
signal dmem_we : std_logic;
signal dmem_re : std_logic;
signal debug : unsigned(1 downto 0);
signal RST_I : STD_LOGIC := '1';
signal CLK_I : STD_LOGIC := '0';
signal ACK_I : STD_LOGIC := '0';
signal SRDY_I : STD_LOGIC := '0';
signal ADDR_O : word_t;
signal DAT_I : word_t := (others => '0');
signal DAT_O : word_t;
signal WE_O : STD_LOGIC;
signal SEL_O : unsigned(3 downto 0);
signal CYC_O : STD_LOGIC;
signal STB_O : STD_LOGIC;
signal MRDY_O : STD_LOGIC;
signal INT : unsigned (5 downto 0) := (others => '0');
BEGIN
uut: mips_top
PORT MAP(
rst => rst,
clk => clk,
halt => cpu_halt,
imem_din => irom_data,
imem_addr => irom_addr,
dmem_we => dmem_we,
dmem_re => dmem_re,
dmem_din => dmem_din,
dmem_dout => dmem_dout,
dmem_addr => dmem_addr
);
inst_rom: rom
PORT MAP
(
clk => clk,
addr => irom_addr,
dout => irom_data
);
inst_ram: ram
GENERIC MAP
(
word_addr_width => 6
)
PORT MAP
(
clk => clk,
we => dmem_we,
addr => dmem_addr,
din => dmem_dout,
dout => dmem_din
debug => debug,
RST_I => RST_I,
CLK_I => CLK_I,
ACK_I => ACK_I,
SRDY_I => SRDY_I,
ADDR_O => ADDR_O,
DAT_I => DAT_I,
DAT_O => DAT_O,
WE_O => WE_O,
SEL_O => SEL_O,
CYC_O => CYC_O,
STB_O => STB_O,
MRDY_O => MRDY_O,
INT => INT
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
HLT_GEN:
process(rst, clk)
subtype cnt_t is natural range 0 to 2;
variable cnt : cnt_t;
begin
if rst = '1' then
cnt := cnt_t'high;
cpu_halt <= '0';
elsif rising_edge(clk) then
cpu_halt <= '0';
if cnt /= 0 then
cnt := cnt - 1;
else
cnt := cnt_t'high;
cpu_halt <= '1';
end if;
end if;
CLK_I <= not CLK_I;
end process;
STIMULUS: process
begin
-- for i in 0 to instr_name_array'length-1 loop
-- fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
-- end loop;
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
rst <= '0';
wait for 2*CLK_PERIOD;
-- assert false report "Test finished" severity error;
wait until rising_edge(CLK_I);
RST_I <= '0';
wait;
end process;
lib/CPUs/MIPS/syn/ise101/mips_top.prj
+20
View File
@@ -0,0 +1,20 @@
vhdl work "../../src/core/mips_types.vhd"
vhdl work "../../../../misc/dpram_2w2r.vhd"
vhdl work "../../../../misc/dpram_1w1r_dist.vhd"
vhdl work "../../../../misc/dpram_1w1r.vhd"
vhdl work "../../../../FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../src/core/mips_instr.vhd"
vhdl work "../../../../FIFO/src/fifo_sync_dist.vhd"
vhdl work "../../src/core/mips_shifter.vhd"
vhdl work "../../src/core/mips_reg.vhd"
vhdl work "../../src/core/mips_muldiv.vhd"
vhdl work "../../src/core/mips_idecode_rom.vhd"
vhdl work "../../src/core/mips_icache.vhd"
vhdl work "../../src/core/mips_dcache.vhd"
vhdl work "../../src/core/mips_cop.vhd"
vhdl work "../../src/core/mips_bcu.vhd"
vhdl work "../../src/core/mips_alu.vhd"
vhdl work "../../src/core/mips_pipeline.vhd"
vhdl work "../../src/core/mips_biu.vhd"
vhdl work "../../src/core/mips_top.vhd"
lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
+20
View File
@@ -0,0 +1,20 @@
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
lib/CPUs/MIPS/todo.txt
+5
View File
@@ -0,0 +1,5 @@
2008-10-26
- Optimierung: MUL32x32 primitive für Virtex-4
- External COP 1..3 interface
- FPU (COP1)
- MMU
lib/FIFO/src/async_fifo_ctrl.vhd
+2 -2
View File
@@ -21,7 +21,7 @@
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.2 2008-10-25 11:21:47 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
@@ -80,7 +80,7 @@ architecture Behavioral of async_fifo_ctrl is
begin
ptr_w <= bcnt_w(addr_width-1 downto 0);
ptr_r <= bcnt_r(addr_width-1 downto 0);
ptr_r <= bnxt_r(addr_width-1 downto 0);
winc <= we and (not write_inhibit);
rinc <= re and (not read_inhibit);
fifo_full <= write_inhibit;
lib/VGA_ctrl/src/linefifo.vhd → lib/FIFO/src/fifo_async.vhd
+30 -38
View File
@@ -26,14 +26,13 @@ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use work.vga_types.all;
entity linefifo is
entity fifo_async is
Generic
(
depth : natural := 64;
almost_full_thresh : natural := 60;
almost_empty_thresh : natural := 4
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4
);
Port
(
@@ -46,19 +45,16 @@ entity linefifo is
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC;
color_w : in color_t;
color_r : out color_t
data_w : in unsigned (data_width-1 downto 0);
data_r : out unsigned (data_width-1 downto 0)
);
end linefifo;
end fifo_async;
architecture Behavioral of linefifo is
constant data_width : integer := 8;
constant addr_width : integer := NextExpBaseTwo(depth);
architecture Behavioral of fifo_async is
signal buf_we_w : STD_LOGIC;
signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0);
signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0);
signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_full : STD_LOGIC;
@@ -72,29 +68,7 @@ begin
fifo_afull <= almost_full;
fifo_aempty <= almost_empty;
gen_line:
for c in color_range_t generate
begin
inst_dpram: entity work.dpram
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP(
clka => clk_w,
clkb => clk_r,
en_a => '1',
en_b => '1',
we_a => buf_we_w,
addr_a => ptr_w,
addr_b => ptr_r,
din_a => color_w(c),
dout_b => color_r(c)
);
end generate;
inst_fifo_ctrl: entity work.async_fifo_ctrl
inst_fifo_ctrl: entity work.async_fifo_ctrl
GENERIC MAP
(
addr_width => ADDR_WIDTH,
@@ -117,5 +91,23 @@ gen_line:
);
inst_dpram_1w1r: entity work.dpram_1w1r
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
PORT MAP(
clka => clk_w,
clkb => clk_r,
en_a => '1',
en_b => '1',
we_a => buf_we_w,
addr_a => ptr_w,
addr_b => ptr_r,
din_a => data_w,
dout_b => data_r
);
end Behavioral;
lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd → lib/FIFO/src/fifo_sync.vhd
+6 -4
View File
@@ -29,7 +29,8 @@ USE IEEE.NUMERIC_STD.ALL;
use work.fifo_ctrl_pkg.all;
entity fifo_sync is
Generic (
Generic
(
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
@@ -72,7 +73,7 @@ begin
fifo_afull <= almost_full;
fifo_aempty <= almost_empty;
inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
GENERIC MAP
(
addr_width => addr_width,
@@ -96,8 +97,9 @@ begin
);
inst_dpram_1w1r: entity work.dpram_1w1r_dist
GENERIC MAP (
inst_dpram_1w1r: entity work.dpram_1w1r
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
lib/FIFO/src/fifo_sync_dist.vhd
+117
View File
@@ -0,0 +1,117 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use work.fifo_ctrl_pkg.all;
entity fifo_sync_dist is
Generic (
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
almost_empty_thresh : integer := 4
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC;
data_w : in unsigned (data_width-1 downto 0);
data_r : out unsigned (data_width-1 downto 0)
);
end fifo_sync_dist;
architecture Behavioral of fifo_sync_dist is
signal mem_wr_en : STD_LOGIC;
signal mem_rd_en : STD_LOGIC;
signal ptr_w : unsigned (addr_width-1 downto 0);
signal ptr_r : unsigned (addr_width-1 downto 0);
signal full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal pre_full : STD_LOGIC;
signal pre_empty : STD_LOGIC;
begin
mem_wr_en <= not full;
mem_rd_en <= not pre_empty;
fifo_full <= full;
fifo_empty <= empty;
fifo_afull <= almost_full;
fifo_aempty <= almost_empty;
inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
GENERIC MAP
(
addr_width => addr_width,
almost_full_thresh => almost_full_thresh,
almost_empty_thresh => almost_empty_thresh
)
PORT MAP
(
rst => rst,
clk => clk,
we => we,
re => re,
ptr_w => ptr_w,
ptr_r => ptr_r,
fifo_full => full,
fifo_empty => empty,
fifo_pre_full => pre_full,
fifo_pre_empty => pre_empty,
fifo_afull => almost_full,
fifo_aempty => almost_empty
);
inst_dpram_1w1r: entity work.dpram_1w1r_dist
GENERIC MAP (
addr_width => addr_width,
data_width => data_width
)
PORT MAP(
clka => clk,
clkb => clk,
en_a => mem_wr_en,
en_b => mem_rd_en,
we_a => we,
addr_a => ptr_w,
addr_b => ptr_r,
din_a => data_w,
dout_b => data_r
);
end Behavioral;
lib/FIFO/src/sync_fifo_ctrl.vhd
+18 -14
View File
@@ -21,7 +21,7 @@
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.2 2008-10-12 18:04:36 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
@@ -42,6 +42,8 @@ entity sync_fifo_ctrl is
re : in STD_LOGIC;
ptr_w : out unsigned (addr_width-1 downto 0);
ptr_r : out unsigned (addr_width-1 downto 0);
fifo_pre_full : out STD_LOGIC;
fifo_pre_empty : out STD_LOGIC;
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
@@ -61,11 +63,13 @@ architecture Behavioral of sync_fifo_ctrl is
begin
read <= '1' when re = '1' and empty = '0' else '0';
write <= '1' when we = '1' and full = '0' else '0';
read <= re and not empty;
write <= we and not full;
fifo_full <= full;
fifo_empty <= empty;
fifo_full <= full;
fifo_empty <= empty;
fifo_pre_full <= pre_full;
fifo_pre_empty <= pre_empty;
proc_diff_gen:
@@ -131,14 +135,14 @@ proc_empty_reg:
end process;
proc_status_w:
process(was_write, pW_next, pR_next, pW, pR, we, re)
process(was_write, pW_next, pR_next, pW, pR, write, read)
begin
if (pW_next = pR) and (we = '1' or was_write = '1') then
if (pW_next = pR) and (write = '1' or was_write = '1') then
pre_full <= '1';
else
pre_full <= '0';
end if;
if (pR_next = pW) and (re = '1' or was_write = '0') then
if (pR_next = pW) and (read = '1' or was_write = '0') then
pre_empty <= '1';
else
pre_empty <= '0';
@@ -160,36 +164,36 @@ proc_flag_write:
end process;
proc_ptr_w:
process(rst, clk, pW, we, full)
process(rst, clk, pW, write, full)
begin
if rst = '1' then
pW <= to_unsigned(0, addr_width);
pW_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if we = '1' then
if write = '1' then
pW <= pW_next;
end if;
end if;
pW_next <= pW;
if we = '1' and full = '0' then
if write = '1' then
pW_next <= pW + 1;
end if;
ptr_w <= pW;
end process;
proc_ptr_r:
process(rst, clk, pR_next, pR, re, empty)
process(rst, clk, pR_next, pR, read, empty)
begin
if rst = '1' then
pR <= to_unsigned(0, addr_width);
pR_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if re = '1' then
if read = '1' then
pR <= pR_next;
end if;
end if;
pR_next <= pR;
if re = '1' and empty = '0' then
if read = '1' then
pR_next <= pR + 1;
end if;
ptr_r <= pR_next;
lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do
-6
View File
@@ -1,6 +0,0 @@
vlib simprim
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do
-6
View File
@@ -1,6 +0,0 @@
vlib unisim
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk
BIN
View File
Binary file not shown.
lib/SDRAM/ddr_sdr_v1_5/sim/compile_simprim.do
-6
View File
@@ -1,6 +0,0 @@
vlib simprim
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
lib/SDRAM/ddr_sdr_v1_5/sim/compile_unisim.do
-6
View File
@@ -1,6 +0,0 @@
vlib unisim
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
+28
View File
@@ -0,0 +1,28 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
vcom -explicit -93 "../src/reset_virtex4.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
vcom -explicit -93 "../src/sdram_ctrl.vhd"
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd"
vcom -explicit -93 "../src/mt46v16m16.vhd"
vcom -explicit -93 "../src/tb_sdram_ctrl_frontend64_wb.vhd"
#restart -force
vsim -t 1ps -lib work tb_sdram_ctrl_frontend64_wb
do {tb_sdram_ctrl_frontend64_wb.wdo}
view wave
view structure
view signals
run 200us
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
+50
View File
@@ -0,0 +1,50 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/rst_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/cyc_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/stb_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/we_o
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sel_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/ack_i
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/mrdy_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt
add wave -noupdate -divider Part
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cs_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_we_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_ras_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cas_n
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_ba
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dm
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dqs
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_data
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {34438503 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {210 us}
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo
+2 -2
View File
@@ -4,10 +4,10 @@
vlib work
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../src/fifo_sync.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
vcom -explicit -93 "../src/reset_virtex4.vhd"
@@ -25,4 +25,4 @@ do {tb_sdram_ctrl_frontend_wb.wdo}
view wave
view structure
view signals
run 10us
run 200us
lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo
+10 -2
View File
@@ -24,8 +24,16 @@ add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8165533 ps} 0}
WaveRestoreCursors {{Cursor 1} {34438503 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -39,4 +47,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {7279048 ps} {8233593 ps}
WaveRestoreZoom {0 ps} {210 us}
lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+3 -22
View File
@@ -43,9 +43,7 @@ entity ddr_phy is
phy_ctrl : in phy_ctrl_t;
part_ctrl : in part_ctrl_t;
sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0);
sdr_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0);
sdr_data_vld : out STD_LOGIC;
sdr_data_req_w : out STD_LOGIC;
@@ -83,9 +81,6 @@ architecture tech of ddr_phy is
type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
signal u_tag_pipe : u_tag_array_t;
type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0);
signal dm_out_pipe : dm_out_array_t;
begin
------------------------------------------------------------------------------------------------------------------------------------------------
@@ -102,19 +97,6 @@ utag_pipe:
end if;
end process;
dmout_pipe:
process(sys_rst, sys_clk0)
begin
if rising_edge(sys_clk0) then
for i in dm_out_pipe'length-1 downto 1 loop
dm_out_pipe(i) <= dm_out_pipe(i-1);
end loop;
if phy_ctrl.utag_we = '1' then
dm_out_pipe(0) <= sdr_dm_rd_in;
end if;
end if;
end process;
WE_REGISTER:
process(sys_rst, sys_clk0)
begin
@@ -239,8 +221,8 @@ gen_ddr_dm_out:
Q => part_dm(n), -- 1-bit DDR output
C => sys_clk270, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => sdr_dm_wr_in(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge)
D2 => sdr_dm_wr_in(n), -- 1-bit data input (negative edge)
D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge)
D2 => sdr_dm(n), -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
@@ -368,7 +350,6 @@ misc_flags_and_data_out:
sdr_data_r <= data_reg_r;
if p(3) = '1' then
u_tag_rd <= u_tag_pipe(4);
sdr_dm_rd_out <= dm_out_pipe(4);
end if;
if phy_ctrl.we = '1' then
u_tag_wr <= u_tag_pipe(0);
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
-1
View File
@@ -110,7 +110,6 @@ fsm_sdr_state:
case cmd is
when SD_PRE =>
st_sdr_next <= PRECHARGE;
sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL);
when SD_LMR =>
st_sdr_next <= MODE;
when SD_ACT =>
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
+1 -1
View File
@@ -27,7 +27,7 @@ USE IEEE.NUMERIC_STD.ALL;
package sdram_config is
constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width
constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+88 -84
View File
@@ -57,7 +57,7 @@ architecture behaviour of sdram_ctrl is
constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL);
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH);
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
@@ -85,14 +85,18 @@ architecture behaviour of sdram_ctrl is
signal bank_addr_reg : bank_addr_t;
signal row_addr_reg : row_addr_t;
signal col_addr_reg : col_addr_t;
signal bank_addr_last : bank_addr_t;
signal row_addr_last : row_addr_t;
signal col_addr_last : col_addr_t;
signal u_bank_addr : bank_addr_t;
signal u_row_addr : row_addr_t;
signal u_col_addr : col_addr_t;
signal act_request : std_logic;
signal act_request_set : std_logic;
signal act_request_clr : std_logic;
signal bank_active_reg : unsigned(0 to 3);
signal bank_is_active : std_logic;
signal bank_activate : std_logic;
signal bank_clr : std_logic;
type init_seq_rom_t is array (0 to 14) of init_seq_t;
@@ -181,10 +185,11 @@ begin
u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
bank_is_active <= bank_active_reg(to_integer(u_bank_addr));
------------------------------------------------------------------------------------------
fsm_ctrl_state:
process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request)
process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, bank_addr_last, row_addr_last, refresh_request, bank_is_active)
begin
u_busy <= '1';
@@ -200,8 +205,8 @@ fsm_ctrl_state:
seq_rst_en <= '0';
addr_reg_load_en <= '0';
refresh_cnt_rst <= '0';
act_request_set <= '0';
act_request_clr <= '0';
bank_activate <= '0';
bank_clr <= '0';
u_tag_out <= u_tag_reg;
st_ctrl_next <= st_ctrl;
@@ -223,7 +228,7 @@ fsm_ctrl_state:
sdr_cmd <= init_seq_rom(seq_cnt).cmd;
cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
if seq_cnt = init_seq_rom_t'high then
act_request_set <= '1';
bank_clr <= '1';
refresh_cnt_rst <= '1';
st_ctrl_next <= USER_READY;
elsif sdr_cmd_busy = '0' then
@@ -239,119 +244,116 @@ fsm_ctrl_state:
end if;
when USER_READY =>
if sdr_cmd_busy = '0' then
if refresh_request = '1' then
sdr_mode(BIT_PRE_ALL) <= '1';
sdr_cmd_we <= '1';
sdr_cmd <= SD_PRE;
st_ctrl_next <= REFRESH;
else
u_busy <= '0';
if u_cmd_we = '1' then
case u_cmd is
when UCMD_NOP =>
sdr_cmd <= SD_NOP;
when UCMD_LMR =>
sdr_cmd <= SD_NOP;
when UCMD_WRITE =>
col_addr <= u_col_addr;
u_tag_out <= u_tag_in;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
addr_reg_load_en <= '1';
act_request_clr <= '1';
sdr_cmd <= SD_WRITE;
if (u_row_addr /= row_addr_reg) or act_request = '1' then
st_ctrl_next <= USER_WRITE_PRE;
elsif (u_bank_addr /= bank_addr_reg) then
if ENABLE_PRE_ALL = '1' then
st_ctrl_next <= USER_WRITE_ACT;
else
st_ctrl_next <= USER_WRITE_PRE;
end if;
elsif sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
else
st_ctrl_next <= USER_WRITE;
end if;
when UCMD_READ =>
col_addr <= u_col_addr;
u_tag_out <= u_tag_in;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
addr_reg_load_en <= '1';
act_request_clr <= '1';
sdr_cmd <= SD_READ;
if (u_row_addr /= row_addr_reg) or act_request = '1' then
st_ctrl_next <= USER_READ_PRE;
elsif (u_bank_addr /= bank_addr_reg) then
if ENABLE_PRE_ALL = '1' then
st_ctrl_next <= USER_READ_ACT;
else
st_ctrl_next <= USER_READ_PRE;
end if;
elsif sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
else
st_ctrl_next <= USER_READ;
end if;
when others => null;
end case;
end if;
if refresh_request = '1' then
st_ctrl_next <= REFRESH_PRE;
else
u_busy <= '0';
col_addr <= u_col_addr;
u_tag_out <= u_tag_in;
sdr_mode <= u_bank_addr & u_row_addr;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
if u_cmd_we = '1' then
addr_reg_load_en <= '1';
case u_cmd is
when UCMD_NOP =>
sdr_cmd <= SD_NOP;
when UCMD_LMR =>
sdr_cmd <= SD_NOP;
when UCMD_WRITE =>
sdr_cmd <= SD_WRITE;
if (u_row_addr /= row_addr_reg) then
st_ctrl_next <= USER_WRITE_PRE;
elsif bank_is_active = '0' then
st_ctrl_next <= USER_WRITE_ACT;
elsif sdr_cmd_busy = '1' then
st_ctrl_next <= USER_WRITE;
else
sdr_cmd_we <= '1';
end if;
when UCMD_READ =>
sdr_cmd <= SD_READ;
if (u_row_addr /= row_addr_reg) then
st_ctrl_next <= USER_READ_PRE;
elsif bank_is_active = '0' then
st_ctrl_next <= USER_READ_ACT;
elsif sdr_cmd_busy = '1' then
st_ctrl_next <= USER_READ;
else
sdr_cmd_we <= '1';
end if;
when others => null;
end case;
end if;
end if;
when USER_WRITE_PRE =>
sdr_cmd <= SD_PRE;
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
bank_clr <= '1';
sdr_cmd <= SD_PRE;
sdr_mode <= bank_addr_last & row_addr_last;
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_WRITE_ACT;
end if;
when USER_WRITE_ACT =>
sdr_cmd <= SD_ACT;
bank_activate <= '1';
sdr_cmd <= SD_ACT;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_WRITE;
end if;
when USER_WRITE =>
sdr_cmd <= SD_WRITE;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
sdr_cmd <= SD_WRITE;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READY;
end if;
when USER_READ_PRE =>
bank_clr <= '1';
sdr_cmd <= SD_PRE;
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
sdr_mode <= bank_addr_last & row_addr_last;
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READ_ACT;
end if;
when USER_READ_ACT =>
sdr_cmd <= SD_ACT;
bank_activate <= '1';
sdr_cmd <= SD_ACT;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READ;
end if;
when USER_READ =>
sdr_cmd <= SD_READ;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
sdr_cmd <= SD_READ;
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READY;
end if;
when REFRESH_PRE =>
bank_clr <= '1';
sdr_cmd <= SD_PRE;
-- sdr_mode <= bank_addr_last & row_addr_last;
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= REFRESH;
end if;
when REFRESH =>
sdr_cmd <= SD_AR;
if sdr_cmd_busy = '0' then
sdr_cmd_we <= '1';
st_ctrl_next <= USER_READY;
refresh_cnt_rst <= '1';
act_request_set <= '1';
end if;
when others =>
@@ -371,20 +373,19 @@ fsm_ctrl_state_next:
end process;
------------------------------------------------------------------------------------------
act_request_register:
process (rst, clk)
bank_active_register:
process (clk)
begin
if rst = '1' then
act_request <= '1';
elsif rising_edge(clk) then
if act_request_set = '1' then
act_request <= '1';
elsif act_request_clr = '1' then
act_request <= '0';
if rising_edge(clk) then
if bank_clr = '1' then
bank_active_reg <= (others => '0'); -- assumes PRE_ALL !!!!!!!!!!!!!
elsif bank_activate = '1' then
bank_active_reg(to_integer(bank_addr_reg)) <= '1';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
user_addr_register:
process (rst, clk)
@@ -396,6 +397,9 @@ user_addr_register:
u_tag_reg <= (others => '0');
elsif rising_edge(clk) then
if addr_reg_load_en = '1' then
bank_addr_last <= bank_addr_reg;
row_addr_last <= row_addr_reg;
col_addr_last <= col_addr_reg;
bank_addr_reg <= u_bank_addr;
row_addr_reg <= u_row_addr;
col_addr_reg <= u_col_addr;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+272
View File
@@ -0,0 +1,272 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
entity sdram_ctrl_frontend64_wb is
Generic
(
BL : natural := 2;
f_sysclk : natural := 100E6;
fifo_depth : integer := 4
);
Port
(
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
CLK270_I : in STD_LOGIC;
CLK270VAR_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(SDR_DM_WIDTH-1 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0);
DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0);
-- SDRAM signals
sd_clk_p : out STD_LOGIC;
sd_clk_n : out STD_LOGIC;
sd_cke : out STD_LOGIC;
sd_cs_n : out STD_LOGIC;
sd_cas_n : out STD_LOGIC;
sd_ras_n : out STD_LOGIC;
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
);
end sdram_ctrl_frontend64_wb;
architecture struct of sdram_ctrl_frontend64_wb is
-- Number of user data words for simulation
signal u_addr : user_addr_t;
signal u_tag_in : user_tag_t;
signal u_tag_rd : user_tag_t;
signal u_tag_wr : user_tag_t;
signal u_cmd : user_cmd_t;
signal u_cmd_we : std_logic;
signal u_busy : std_logic;
signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0);
signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal u_data_vld : std_logic;
signal u_req_wr : std_logic;
signal rdy : std_logic;
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_re : std_logic;
signal cat_fifo_we : std_logic;
signal cat_fifo_full : std_logic;
signal cat_fifo_empty : std_logic;
-- signal cat_fifo_almost_full : std_logic;
-- signal cat_fifo_almost_empty : std_logic;
signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
signal write_fifo_re : std_logic;
signal write_fifo_we : std_logic;
signal write_fifo_full : std_logic;
signal write_fifo_empty : std_logic;
-- signal write_fifo_almost_full : std_logic;
-- signal write_fifo_almost_empty : std_logic;
signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal read_fifo_re : std_logic;
signal read_fifo_we : std_logic;
signal read_fifo_full : std_logic;
signal read_fifo_empty : std_logic;
-- signal read_fifo_almost_full : std_logic;
-- signal read_fifo_almost_empty : std_logic;
alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
alias write_fifo_dm_in is write_fifo_din(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
alias write_fifo_data_in is write_fifo_din(SDR_DATA_WIDTH-1 downto 0);
alias write_fifo_dm_out is write_fifo_dout(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
alias write_fifo_data_out is write_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
alias read_fifo_data_in is read_fifo_din(SDR_DATA_WIDTH-1 downto 0);
alias read_fifo_data_out is read_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
begin
-- Instantiate synchronous FIFO
inst_cat_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => fifo_depth,
data_width => CAT_FIFO_WIDTH
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => cat_fifo_we,
re => cat_fifo_re,
fifo_full => cat_fifo_full,
fifo_empty => cat_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => cat_fifo_din,
data_r => cat_fifo_dout
);
-- Instantiate synchronous FIFO
inst_write_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => fifo_depth,
data_width => write_fifo_din'length
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => write_fifo_we,
re => write_fifo_re,
fifo_full => write_fifo_full,
fifo_empty => write_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => write_fifo_din,
data_r => write_fifo_dout
);
-- Instantiate synchronous FIFO
inst_read_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => fifo_depth,
data_width => read_fifo_din'length
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => read_fifo_we,
re => read_fifo_re,
fifo_full => read_fifo_full,
fifo_empty => read_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => read_fifo_din,
data_r => read_fifo_dout
);
-- DDR SDRAM Controller Core
inst_sdram_ctrl : entity work.sdram_ctrl_top
Generic map
(
BL => BL,
f_sysclk => f_sysclk
)
Port map
(
sys_rst_in => RST_I,
sys_clk0_in => CLK_I,
sys_clk270_in => CLK270_I,
capture_clk270_in => CLK270VAR_I,
-- User interface
u_data_vld => u_data_vld,
u_data_req_w => u_req_wr,
u_data_req_r => open,
u_tag_in => u_tag_in,
u_tag_rd => u_tag_rd,
u_tag_wr => u_tag_wr,
u_busy => u_busy,
u_addr => u_addr,
u_cmd => u_cmd,
u_cmd_we => u_cmd_we,
u_data_wr => u_data_w,
u_data_rd => u_data_r,
u_dm => u_dm_wr_in,
-- SDRAM signals
sd_clk_p => sd_clk_p,
sd_clk_n => sd_clk_n,
sd_cke => sd_cke,
sd_cs_n => sd_cs_n,
sd_cas_n => sd_cas_n,
sd_ras_n => sd_ras_n,
sd_we_n => sd_we_n,
sd_addr => sd_addr,
sd_ba => sd_ba,
sd_dm => sd_dm,
sd_dqs => sd_dqs,
sd_data => sd_data
);
------------------------------------------------------------------------------------------
SRDY_O <= rdy;
ACK_O <= not (read_fifo_empty);
DAT_O <= read_fifo_data_out;
rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
write_fifo_we <= STB_I and WE_I and rdy;
write_fifo_data_in <= DAT_I;
write_fifo_dm_in <= not SEL_I;
cat_fifo_we <= STB_I and rdy;
cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ;
addr_fifo_in <= ADDR_I(25 downto 3) & "0";
tag_fifo_in <= "000" & ADDR_I(2);
u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
u_cmd <= cmd_fifo_out;
u_addr <= addr_fifo_out;
u_dm_wr_in <= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when u_tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
u_tag_in <= tag_fifo_out;
u_data_w <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0);
write_fifo_re <= u_req_wr and (not write_fifo_empty);
cat_fifo_re <= u_cmd_we;
read_fifo_re <= (not read_fifo_empty) and MRDY_I;
read_fifo_we <= u_data_vld;
read_fifo_data_in <= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0);
end architecture struct;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+19 -30
View File
@@ -83,14 +83,12 @@ architecture struct of sdram_ctrl_frontend_wb is
signal u_busy : std_logic;
signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0);
signal u_dm_rd_in : unsigned(SDR_DM_WIDTH-1 downto 0);
signal u_dm_rd_out : unsigned(SDR_DM_WIDTH-1 downto 0);
signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal u_data_vld : std_logic;
signal u_req_wr : std_logic;
signal rdy : std_logic;
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + 4;
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_re : std_logic;
@@ -109,8 +107,8 @@ architecture struct of sdram_ctrl_frontend_wb is
-- signal write_fifo_almost_full : std_logic;
-- signal write_fifo_almost_empty : std_logic;
signal read_fifo_din : unsigned(35 downto 0);
signal read_fifo_dout : unsigned(35 downto 0);
signal read_fifo_din : unsigned(31 downto 0);
signal read_fifo_dout : unsigned(31 downto 0);
signal read_fifo_re : std_logic;
signal read_fifo_we : std_logic;
signal read_fifo_full : std_logic;
@@ -120,22 +118,18 @@ architecture struct of sdram_ctrl_frontend_wb is
alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 4);
alias dm_rd_fifo_in is cat_fifo_din(4-1 downto 0);
alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 4);
alias dm_rd_fifo_out is cat_fifo_dout(4-1 downto 0);
alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-4);
alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-4-1 downto 0);
alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-4);
alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-4-1 downto 0);
alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4);
alias write_fifo_dm_in is write_fifo_din(3 downto 0);
alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4);
alias write_fifo_dm_out is write_fifo_dout(3 downto 0);
alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-4);
alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-4-1 downto 0);
alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-4);
alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-4-1 downto 0);
alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0);
alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0);
begin
@@ -165,7 +159,7 @@ begin
GENERIC MAP
(
addr_width => fifo_depth,
data_width => 36
data_width => write_fifo_din'length
)
PORT MAP
(
@@ -186,7 +180,7 @@ begin
GENERIC MAP
(
addr_width => fifo_depth,
data_width => 36
data_width => read_fifo_din'length
)
PORT MAP
(
@@ -231,9 +225,7 @@ begin
u_cmd_we => u_cmd_we,
u_data_wr => u_data_w,
u_data_rd => u_data_r,
u_dm_wr_in => u_dm_wr_in,
u_dm_rd_in => u_dm_rd_in,
u_dm_rd_out => u_dm_rd_out,
u_dm => u_dm_wr_in,
-- SDRAM signals
sd_clk_p => sd_clk_p,
@@ -250,7 +242,7 @@ begin
sd_data => sd_data
);
------------------------------------------------------------------------------------------
SRDY_O <= rdy;
ACK_O <= not (read_fifo_empty);
@@ -262,22 +254,19 @@ begin
cat_fifo_we <= STB_I and rdy;
cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ;
addr_fifo_in <= ADDR_I(24 downto 2) & "0";
dm_rd_fifo_in <= not SEL_I;
tag_fifo_in <= (others=>'0');
tag_fifo_in <= "000" & ADDR_I(25);
u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
u_cmd <= cmd_fifo_out;
u_addr <= addr_fifo_out;
u_dm_rd_in <= dm_rd_fifo_out & dm_rd_fifo_out;
u_dm_wr_in <= write_fifo_dm_out & write_fifo_dm_out;
u_dm_wr_in <= ("1111" & write_fifo_dm_out) when u_tag_wr(0) = '0' else (write_fifo_dm_out & "1111");
u_tag_in <= tag_fifo_out;
u_data_w <= write_fifo_data_out & write_fifo_data_out;
write_fifo_re <= u_req_wr and (not write_fifo_empty);
cat_fifo_re <= u_cmd_we;
u_data_w <= write_fifo_data_out & write_fifo_data_out;
read_fifo_re <= (not read_fifo_empty) and MRDY_I;
read_fifo_we <= u_data_vld;
read_fifo_data_in <= u_data_r(31 downto 0);
read_fifo_dm_in <= u_dm_rd_out(3 downto 0);
read_fifo_data_in <= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32);
end architecture struct;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+2 -6
View File
@@ -53,9 +53,7 @@ entity sdram_ctrl_top is
u_cmd : in user_cmd_t;
u_cmd_we : in STD_LOGIC;
u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0);
u_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
u_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
u_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0);
u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0);
u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0);
-- SDRAM signals
@@ -225,9 +223,7 @@ begin
sdr_data_req_w => u_data_req_w,
sdr_data_req_r => u_data_req_r,
sdr_data_w => u_data_wr,
sdr_dm_wr_in => u_dm_wr_in,
sdr_dm_rd_in => u_dm_rd_in,
sdr_dm_rd_out => u_dm_rd_out,
sdr_dm => u_dm,
sdr_data_r => u_data_rd,
sdr_data_vld => u_data_vld,
part_clk_p => sd_clk_p,
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+860
View File
@@ -0,0 +1,860 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
entity tb_sdram_ctrl_frontend64_wb is
end;
architecture struct of tb_sdram_ctrl_frontend64_wb is
-- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns;
constant BURST_LEN : natural := 2;
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal locked : std_logic;
signal error : std_logic;
signal clk_out : std_logic;
signal clk_fb : std_logic;
signal part_clk_p : std_logic;
signal part_clk_n : std_logic;
signal part_cke : std_logic;
signal part_cs_n : std_logic;
signal part_we_n : std_logic;
signal part_ras_n : std_logic;
signal part_cas_n : std_logic;
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal CLK_O : std_logic;
signal CLK270_O : std_logic;
signal CLK270VAR_O : std_logic;
signal RST_O : std_logic;
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal WE_O : std_logic := '0';
signal SEL_O : unsigned(SDR_DM_WIDTH-1 downto 0);
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal DAT_O : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
signal sddat : unsigned(31 downto 0) := (others => '-');
signal sdsel : unsigned(3 downto 0) := (others => '1');
type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
signal sd_cmd : sd_cmd_t;
begin
process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
variable cmd : unsigned (2 downto 0);
begin
cmd := part_ras_n & part_cas_n & part_we_n;
sd_cmd <= nop;
if part_cs_n = '0' then
case cmd is
when "000" =>
sd_cmd <= lmr;
when "001" =>
sd_cmd <= ar;
when "010" =>
sd_cmd <= pre;
when "011" =>
sd_cmd <= act;
when "100" =>
sd_cmd <= write;
when "101" =>
sd_cmd <= read;
when "110" =>
sd_cmd <= bst;
when "111" =>
sd_cmd <= nop;
when others =>
sd_cmd <= nop;
end case;
end if;
end process;
inst_clockgen : entity work.clockgen
GENERIC MAP
(
sys1_phaseshift => 0,
frequency_hz => 100E6
)
PORT MAP
(
-- Clocks and Reset
rst => rst, -- external async reset, low active
clk_in => clk, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_fb, -- feedback clock
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sys1_clk270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys0_clk0_out => CLK_O, -- System clock #0, dcm#0 output 0°
sys0_clk270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
locked_out => locked, -- DCM locked status
error_out => error
);
clk_fb <= part_clk_p after 1 ns;
RST_O <= not locked;
DAT_O <= X"DEADBEEF" & sddat;
SEL_O <= "0000" & sdsel;
-- DDR SDRAM Controller Core
sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => 100E6,
fifo_depth => 3
)
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
CLK270_I => CLK270_O,
CLK270VAR_I => CLK270VAR_O,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I,
-- SDRAM signals
sd_clk_p => part_clk_p,
sd_clk_n => part_clk_n,
sd_cke => part_cke,
sd_cs_n => part_cs_n,
sd_cas_n => part_cas_n,
sd_ras_n => part_ras_n,
sd_we_n => part_we_n,
sd_addr => part_addr,
sd_ba => part_ba,
sd_dm => part_dm,
sd_dqs => part_dqs,
sd_data => part_data
);
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_0 : entity work.mt46v16m16
port map
(
dq => std_logic_vector(part_data(15 downto 0)),
dqs => std_logic_vector(part_dqs(1 downto 0)),
addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba),
clk => part_clk_p,
clk_n => part_clk_n,
cke => part_cke,
cs_n => part_cs_n,
ras_n => part_ras_n,
cas_n => part_cas_n,
we_n => part_we_n,
dm => std_logic_vector(part_dm(1 downto 0))
);
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_1 : entity work.mt46v16m16
port map
(
dq => std_logic_vector(part_data(31 downto 16)),
dqs => std_logic_vector(part_dqs(3 downto 2)),
addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba),
clk => part_clk_p,
clk_n => part_clk_n,
cke => part_cke,
cs_n => part_cs_n,
ras_n => part_ras_n,
cas_n => part_cas_n,
we_n => part_we_n,
dm => std_logic_vector(part_dm(3 downto 2))
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
clk <= not clk;
end process;
read_register:
process(CLK_O)
begin
if rising_edge(CLK_O) then
if dout_rst = '1' then
dout_cnt <= 0;
elsif ACK_I = '1' and WE_O = '0' then
dout_reg <= DAT_I(31 downto 0);
dout_cnt <= dout_cnt + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
rst <= '0';
wait until RST_O = '0';
-- 8 single cycles
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sddat <= X"1234_0000";
ADDR_O <= X"0000_0000";
for i in 0 to 8192 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 31 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 31;
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "0011";
ADDR_O <= X"0000_0080";
sddat <= X"DEADBEEF";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0080";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 31 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 31;
CYC_O <= '0';
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
end loop;
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
end loop;
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "1111";
sddat <= X"1111_0000";
ADDR_O <= X"0000_0000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "1111";
sddat <= X"2222_0000";
ADDR_O <= X"0000_0400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "1111";
sddat <= X"3333_0000";
ADDR_O <= X"0000_0800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "1111";
sddat <= X"4444_0000";
ADDR_O <= X"0000_0C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
end loop;
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "1111";
sddat <= X"1111_0000";
ADDR_O <= X"0000_1000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "1111";
sddat <= X"2222_0000";
ADDR_O <= X"0000_1400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "1111";
sddat <= X"3333_0000";
ADDR_O <= X"0000_1800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
sdsel <= "1111";
sddat <= X"4444_0000";
ADDR_O <= X"0000_1C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
sddat <= sddat + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
end loop;
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
end loop;
wait;
end process;
end architecture struct;
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+604 -254
View File
@@ -76,8 +76,43 @@ architecture struct of tb_sdram_ctrl_frontend_wb is
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
signal sd_cmd : sd_cmd_t;
begin
process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
variable cmd : unsigned (2 downto 0);
begin
cmd := part_ras_n & part_cas_n & part_we_n;
sd_cmd <= nop;
if part_cs_n = '0' then
case cmd is
when "000" =>
sd_cmd <= lmr;
when "001" =>
sd_cmd <= ar;
when "010" =>
sd_cmd <= pre;
when "011" =>
sd_cmd <= act;
when "100" =>
sd_cmd <= write;
when "101" =>
sd_cmd <= read;
when "110" =>
sd_cmd <= bst;
when "111" =>
sd_cmd <= nop;
when others =>
sd_cmd <= nop;
end case;
end if;
end process;
inst_clockgen : entity work.clockgen
GENERIC MAP
(
@@ -144,13 +179,12 @@ inst_clockgen : entity work.clockgen
);
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_0 : entity work.mt46v16m16
port map
(
dq => std_logic_vector(part_data),
dqs => std_logic_vector(part_dqs),
dq => std_logic_vector(part_data(15 downto 0)),
dqs => std_logic_vector(part_dqs(1 downto 0)),
addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba),
clk => part_clk_p,
@@ -160,7 +194,25 @@ i_mt46v16m16_0 : entity work.mt46v16m16
ras_n => part_ras_n,
cas_n => part_cas_n,
we_n => part_we_n,
dm => std_logic_vector(part_dm)
dm => std_logic_vector(part_dm(1 downto 0))
);
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_1 : entity work.mt46v16m16
port map
(
dq => std_logic_vector(part_data(31 downto 16)),
dqs => std_logic_vector(part_dqs(3 downto 2)),
addr => std_logic_vector(part_addr),
ba => std_logic_vector(part_ba),
clk => part_clk_p,
clk_n => part_clk_n,
cke => part_cke,
cs_n => part_cs_n,
ras_n => part_ras_n,
cas_n => part_cas_n,
we_n => part_we_n,
dm => std_logic_vector(part_dm(3 downto 2))
);
CLK_GEN: process
@@ -198,125 +250,22 @@ STIMULUS: process
WE_O <= '1';
DAT_O <= X"1234_0000";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
for i in 0 to 8192 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
CYC_O <= '0';
-- 8-word burst cycle
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
@@ -324,27 +273,20 @@ STIMULUS: process
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
for i in 0 to 31 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
wait until rising_edge(CLK_O) and dout_cnt = 7;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 31;
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
@@ -355,10 +297,13 @@ STIMULUS: process
DAT_O <= X"DEADBEEF";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
@@ -370,134 +315,539 @@ STIMULUS: process
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
-- 8-word burst cycle
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
MRDY_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
MRDY_O <= '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
for i in 0 to 31 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
wait until rising_edge(CLK_O) and dout_cnt = 54;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 31;
CYC_O <= '0';
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
end loop;
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
end loop;
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"1111_0000";
ADDR_O <= X"0000_0000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"2222_0000";
ADDR_O <= X"0000_0400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"3333_0000";
ADDR_O <= X"0000_0800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"4444_0000";
ADDR_O <= X"0000_0C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
end loop;
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"1111_0000";
ADDR_O <= X"0000_1000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"2222_0000";
ADDR_O <= X"0000_1400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"3333_0000";
ADDR_O <= X"0000_1800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"4444_0000";
ADDR_O <= X"0000_1C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
end loop;
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
for k in 0 to 3 loop
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
-- wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_1C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
end loop;
wait;
end process;
lib/SSRAM/sim/ModelSim SE .lnk
BIN
View File
Binary file not shown.
lib/SSRAM/sim/tb_ssram_frontend_wb.fdo
+17
View File
@@ -0,0 +1,17 @@
## NOTE: Do not edit this file.
##
vlib work
# Top and TB
vcom -explicit -93 "../src/package_utility.vhd"
vcom -explicit -93 "../src/CY7C1354B.vhd"
vcom -explicit -93 "../src/ssram_frontend_wb.vhd"
vcom -explicit -93 "../src/tb_ssram_frontend_wb.vhd"
vsim -t 1ps -lib work tb_ssram_frontend_wb
do {tb_ssram_frontend_wb.wdo}
view wave
view structure
view signals
run 6us
lib/SSRAM/sim/tb_ssram_frontend_wb.wdo
+47
View File
@@ -0,0 +1,47 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ssram_frontend_wb/clk_o
add wave -noupdate -format Logic /tb_ssram_frontend_wb/rst_o
add wave -noupdate -format Logic /tb_ssram_frontend_wb/cyc_o
add wave -noupdate -format Logic /tb_ssram_frontend_wb/stb_o
add wave -noupdate -format Logic /tb_ssram_frontend_wb/we_o
add wave -noupdate -format Literal /tb_ssram_frontend_wb/sel_o
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ack_i
add wave -noupdate -format Logic /tb_ssram_frontend_wb/mrdy_o
add wave -noupdate -format Logic /tb_ssram_frontend_wb/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_d
add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_dp
add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_a
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_cke_n
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_adv
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_mode
add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_bw_n
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_we_n
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_oe_n
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_ce_n
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_zz
add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dout_reg
add wave -noupdate -format Literal -radix unsigned /tb_ssram_frontend_wb/dout_cnt
add wave -noupdate -format Literal /tb_ssram_frontend_wb/inst_ssram_frontend_wb/vld_pipe
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk_fb
add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1343191 ps} 0} {{Cursor 2} {178651436 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {6300 ns}
lib/SSRAM/src/CY7C1354B.vhd
+388
View File
@@ -0,0 +1,388 @@
-----------------------------------------------------------------------------------------
--
-- File Name: CY7C1354B.VHD
-- Version: 2.0
-- Date: Nov 22nd, 2004
-- Model: BUS Functional
--
--
-- Author: RKF
-- Company: Cypress Semiconductor
-- Model: CY7C1354B (256k x 36)
-- Mode: Pipelined
--
-- Description: NoBL SRAM VHDL Model
--
-- Limitation: None
--
-- Note: - BSDL Model available separately
-- - Set simulator resolution to "ps" timescale
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 2004 Cypress Semiconductor
-- All rights reserved
--
-- Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor
--
-- Rev Author Date Changes
-- --- -------- ------- ----------
-- 2.0 RKF 11/22/2004 - Second Release
-- - Fully Tested with New Test Bench and Test Vectors
-----------------------------------------------------------------------------------------
LIBRARY ieee,work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
Use IEEE.Std_Logic_Arith.all;
-- Use work.all;
USE work.package_utility.all;
ENTITY cy7c1354 IS
GENERIC (
-- Constant parameters
addr_bits : INTEGER := 18;
data_bits : INTEGER := 32;
par_bits : INTEGER := 4;
-- Timing parameters for -5 (225 Mhz)
-- tCYC : TIME := 4.4 ns;
-- tCH : TIME := 1.8 ns;
-- tCL : TIME := 1.8 ns;
-- tCO : TIME := 2.8 ns;
-- tAS : TIME := 1.4 ns;
-- tCENS : TIME := 1.4 ns;
-- tWES : TIME := 1.4 ns;
-- tDS : TIME := 1.4 ns;
-- tAH : TIME := 0.4 ns;
-- tCENH : TIME := 0.4 ns;
-- tWEH : TIME := 0.4 ns;
-- tDH : TIME := 0.4 ns
-- Timing parameters for -6 (200 Mhz)
--tCYC : TIME := 5.0 ns;
--tCH : TIME := 2.0 ns;
--tCL : TIME := 2.0 ns;
--tCO : TIME := 3.2 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
-- Timing parameters for -7 (166 Mhz)
tCYC : TIME := 6.0 ns;
tCH : TIME := 2.4 ns;
tCL : TIME := 2.4 ns;
tCO : TIME := 3.5 ns;
tAS : TIME := 1.5 ns;
tCENS : TIME := 1.5 ns;
tWES : TIME := 1.5 ns;
tDS : TIME := 1.5 ns;
tAH : TIME := 0.5 ns;
tCENH : TIME := 0.5 ns;
tWEH : TIME := 0.5 ns;
tDH : TIME := 0.5 ns
);
-- Port Declarations
PORT (
Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O
Dpq : INOUT STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0); -- Data parity I/O
Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address
Mode : IN STD_LOGIC := '1'; -- Burst Mode
Clk : IN STD_LOGIC; -- Clk
CEN_n : IN STD_LOGIC; -- CEN#
AdvLd_n : IN STD_LOGIC; -- Adv/Ld#
Bwa_n : IN STD_LOGIC; -- Bwa#
Bwb_n : IN STD_LOGIC; -- BWb#
Bwc_n : IN STD_LOGIC; -- Bwc#
Bwd_n : IN STD_LOGIC; -- BWd#
Rw_n : IN STD_LOGIC; -- RW#
Oe_n : IN STD_LOGIC; -- OE#
Ce1_n : IN STD_LOGIC; -- CE1#
Ce2 : IN STD_LOGIC; -- CE2
Ce3_n : IN STD_LOGIC; -- CE3#
Zz : IN STD_LOGIC -- Snooze Mode
);
END cy7c1354;
ARCHITECTURE behave OF cy7c1354 IS
SIGNAL ce : STD_LOGIC := '0';
SIGNAL doe : STD_LOGIC := '0';
SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
SIGNAL dout_p : STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
BEGIN
ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2;
doe <= NOT(Oe_n) AND NOT(Zz);
-- Output Buffers
WITH doe SELECT
Dq <= TRANSPORT dout AFTER (tCO) WHEN '1',
(OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
WITH doe SELECT
Dpq <= TRANSPORT dout_p AFTER (tCO) WHEN '1',
(OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
-- Check for Clock Timing Violation
clk_check : PROCESS
VARIABLE clk_high, clk_low : TIME := 0 ns;
BEGIN
WAIT ON Clk;
IF Clk = '1' AND NOW >= tCYC THEN
ASSERT (NOW - clk_low >= tCH)
REPORT "Clk width low - tCH violation"
SEVERITY ERROR;
ASSERT (NOW - clk_high >= tCYC)
REPORT "Clk period high - tCYC violation"
SEVERITY ERROR;
clk_high := NOW;
ELSIF Clk = '0' AND NOW /= 0 ns THEN
ASSERT (NOW - clk_high >= tCL)
REPORT "Clk width high - tCL violation"
SEVERITY ERROR;
ASSERT (NOW - clk_low >= tCYC)
REPORT "Clk period low - tCYC violation"
SEVERITY ERROR;
clk_low := NOW;
END IF;
END PROCESS;
-- Check for Setup Timing Violation
setup_check : PROCESS
BEGIN
WAIT ON Clk;
IF Clk = '1' and (Ce1_n = '0' and Ce2 = '1' and Ce3_n = '0') THEN
ASSERT (Addr'LAST_EVENT >= tAS)
REPORT "Addr - tAS violation"
SEVERITY ERROR;
ASSERT (CEN_n'LAST_EVENT >= tCENS)
REPORT "CKE# - tCENS violation"
SEVERITY ERROR;
ASSERT (Ce1_n'LAST_EVENT >= tWES)
REPORT "CE1# - tWES violation"
SEVERITY ERROR;
ASSERT (Ce2'LAST_EVENT >= tWES)
REPORT "CE2 - tWES violation"
SEVERITY ERROR;
ASSERT (Ce3_n'LAST_EVENT >= tWES)
REPORT "CE3# - tWES violation"
SEVERITY ERROR;
ASSERT (AdvLd_n'LAST_EVENT >= tWES)
REPORT "ADV/LD# - tWES violation"
SEVERITY ERROR;
ASSERT (Rw_n'LAST_EVENT >= tWES)
REPORT "RW# - tWES violation"
SEVERITY ERROR;
ASSERT (Bwa_n'LAST_EVENT >= tWES)
REPORT "BWa# - tWES violation"
SEVERITY ERROR;
ASSERT (Bwb_n'LAST_EVENT >= tWES)
REPORT "BWb# - tWES violation"
SEVERITY ERROR;
ASSERT (Bwc_n'LAST_EVENT >= tWES)
REPORT "BWc# - tWES violation"
SEVERITY ERROR;
ASSERT (Bwd_n'LAST_EVENT >= tWES)
REPORT "BWd# - tWES violation"
SEVERITY ERROR;
ASSERT (Dq'LAST_EVENT >= tDS)
REPORT "Dq - tDS violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Check for Hold Timing Violation
hold_check : PROCESS
BEGIN
WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH);
IF Clk'DELAYED(tAH) = '1' THEN
ASSERT (Addr'LAST_EVENT > tAH)
REPORT "Addr - tAH violation"
SEVERITY ERROR;
END IF;
IF Clk'DELAYED(tCENH) = '1' THEN
ASSERT (CEN_n'LAST_EVENT > tCENH)
REPORT "CKE# - tCENH violation"
SEVERITY ERROR;
END IF;
IF Clk'DELAYED(tDH) = '1' THEN
ASSERT (Dq'LAST_EVENT > tDH)
REPORT "Dq - tDH violation"
SEVERITY ERROR;
END IF;
IF Clk'DELAYED(tWEH) = '1' THEN
ASSERT (Ce1_n'LAST_EVENT > tWEH)
REPORT "CE1# - tWEH violation"
SEVERITY ERROR;
ASSERT (Ce2'LAST_EVENT > tWEH)
REPORT "CE2 - tWEH violation"
SEVERITY ERROR;
ASSERT (Ce3_n'LAST_EVENT > tWEH)
REPORT "CE3 - tWEH violation"
SEVERITY ERROR;
ASSERT (AdvLd_n'LAST_EVENT > tWEH)
REPORT "ADV/LD# - tWEH violation"
SEVERITY ERROR;
ASSERT (Rw_n'LAST_EVENT > tWEH)
REPORT "RW# - tWEH violation"
SEVERITY ERROR;
ASSERT (Bwa_n'LAST_EVENT > tWEH)
REPORT "BWa# - tWEH violation"
SEVERITY ERROR;
ASSERT (Bwb_n'LAST_EVENT > tWEH)
REPORT "BWb# - tWEH violation"
SEVERITY ERROR;
ASSERT (Bwc_n'LAST_EVENT > tWEH)
REPORT "BWc# - tWEH violation"
SEVERITY ERROR;
ASSERT (Bwd_n'LAST_EVENT > tWEH)
REPORT "BWd# - tWEH violation"
SEVERITY ERROR;
END IF;
END PROCESS;
-- Main Program
main : PROCESS
TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (((data_bits+par_bits) / 4) - 1 DOWNTO 0);
VARIABLE Addr_in : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
VARIABLE first_Addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Addr_read : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
VARIABLE Addr_write : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0';
VARIABLE bank0 : memory_array;
VARIABLE bank1 : memory_array;
VARIABLE bank2 : memory_array;
VARIABLE bank3 : memory_array;
VARIABLE ce_in : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE rw_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "111";
VARIABLE bwa_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
VARIABLE bwb_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
VARIABLE bwc_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
VARIABLE bwd_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
VARIABLE bcnt : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
BEGIN
WAIT ON Clk;
IF Clk'EVENT AND Clk = '1' THEN
IF CEN_n = '0' AND Zz = '0' THEN
-- Write Address Register
Addr_write := Addr_read;
-- Read Address Register
Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0;
-- Address Register
IF AdvLd_n = '0' and ce = '1' THEN
Addr_in := Addr;
first_Addr := Addr(1 DOWNTO 0);
bcnt := Addr(1 DOWNTO 0);
END IF;
-- Burst Logic
IF Mode = '0' AND AdvLd_n = '1' THEN
bcnt := bcnt + 1;
ELSIF Mode = '1' AND AdvLd_n = '1' THEN
IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN
bcnt := bcnt + 1;
ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN
bcnt := bcnt - 1;
END IF;
END IF;
bAddr1 := bcnt (1);
bAddr0 := bcnt (0);
-- Read Logic
ce_in (0) := ce_in (1);
IF AdvLd_n = '0' THEN
ce_in (1) := ce;
END IF;
rw_in (0) := rw_in (1);
rw_in (1) := rw_in (2);
IF AdvLd_n = '0' THEN
rw_in (2) := NOT(ce AND NOT(Rw_n));
END IF;
-- Write Registry and Data Coherency Control Logic
bwa_in (0) := bwa_in (1);
bwb_in (0) := bwb_in (1);
bwc_in (0) := bwc_in (1);
bwd_in (0) := bwd_in (1);
bwa_in (1) := bwa_in (2);
bwb_in (1) := bwb_in (2);
bwc_in (1) := bwc_in (2);
bwd_in (1) := bwd_in (2);
bwa_in (2) := Bwa_n;
bwb_in (2) := Bwb_n;
bwc_in (2) := Bwc_n;
bwd_in (2) := Bwd_n;
-- Write Data to Memory
IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN
bank0 (CONV_INTEGER1 (Addr_write)) := Dpq(0) & Dq ( (data_bits / 4) - 1 DOWNTO 0);
END IF;
IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN
bank1 (CONV_INTEGER1 (Addr_write)) := Dpq(1) & Dq ((data_bits / 2 - 1) DOWNTO (data_bits / 4));
END IF;
IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN
bank2 (CONV_INTEGER1 (Addr_write)) := Dpq(2) & Dq ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2));
END IF;
IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN
bank3 (CONV_INTEGER1 (Addr_write)) := Dpq(3) & Dq (data_bits - 1 DOWNTO (3 * (data_bits / 4)));
END IF;
END IF;
Addr_read_sig <= Addr_read;
-- Read Data from Memory Array
IF ce_in (0) = '1' AND rw_in (1) = '1' THEN
dout ((data_bits / 4) - 1 DOWNTO 0) <= bank0 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0);
dout ((data_bits / 2 - 1) DOWNTO (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0);
dout ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0);
dout (data_bits - 1 DOWNTO (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0);
dout_p(0) <= bank0 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
dout_p(1) <= bank1 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
dout_p(2) <= bank2 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
dout_p(3) <= bank3 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
ELSE
dout <= (OTHERS => 'Z');
dout_p <= (OTHERS => 'Z');
END IF;
END IF;
END PROCESS;
END behave;
lib/SSRAM/src/package_utility.vhd
+73
View File
@@ -0,0 +1,73 @@
--****************************************************************
--** MODEL : package_utility **
--** COMPANY : Cypress Semiconductor **
--** REVISION: 1.0 Created new package utility model **
--** **
--****************************************************************
Library ieee,work;
Use ieee.std_logic_1164.all;
Use IEEE.Std_Logic_Arith.all;
Use IEEE.std_logic_TextIO.all;
--- Use work.package_timing.all;
Library Std;
Use STD.TextIO.all;
Package package_utility is
FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR;
FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER;
End; -- package package_utility
Package body package_utility is
------------------------------------------------------------------------------------------------
--Converts string into std_logic_vector
------------------------------------------------------------------------------------------------
FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(S'RANGE);
BEGIN
FOR i IN S'RANGE LOOP
IF S(i) = '0' THEN
result(i) := '0';
ELSIF S(i) = '1' THEN
result(i) := '1';
ELSIF S(i) = 'X' THEN
result(i) := 'X';
ELSE
result(i) := 'Z';
END IF;
END LOOP;
RETURN result;
END convert_string;
------------------------------------------------------------------------------------------------
--Converts std_logic_vector into integer
------------------------------------------------------------------------------------------------
FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
BEGIN
FOR i IN S'RANGE LOOP
IF S(i) = '1' THEN
result := result + (2**i);
ELSIF S(i) = '0' THEN
result := result;
ELSE
result := 0;
END IF;
END LOOP;
RETURN result;
END CONV_INTEGER1;
end package_utility;
lib/SSRAM/src/ssram_frontend_wb.vhd
+181
View File
@@ -0,0 +1,181 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
ENTITY ssram_frontend_wb IS
Generic
(
latency : natural := 2; -- clock cycles
addr_width : natural := 20;
data_width : natural := 32;
parity_width : natural := 4
);
Port
(
-- J-Bus domain
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
-- Sync SRAM domain
ssram_clk_o : out std_logic;
ssram_clk_fb : in std_logic;
ssram_cke_n : out std_logic;
ssram_ce_n : out std_logic;
ssram_oe_n : out std_logic;
ssram_we_n : out std_logic;
ssram_adv : out std_logic;
ssram_mode : out std_logic;
ssram_zz : out std_logic;
ssram_a : out unsigned(addr_width-1 downto 0);
ssram_d : inout unsigned(data_width-1 downto 0);
ssram_dp : inout unsigned(parity_width-1 downto 0);
ssram_bw_n : out unsigned(3 downto 0)
);
END ssram_frontend_wb;
ARCHITECTURE behavior OF ssram_frontend_wb IS
constant topad : time := 3 ns;
subtype ssram_d_t is unsigned(data_width+parity_width-1 downto 0);
type data_pipe_t is array (latency downto 0) of ssram_d_t;
signal ssram_clk : std_logic;
signal dcm_locked : std_logic;
signal dcm_clk0 : std_logic;
signal dcm_clk1 : std_logic;
signal data_en : std_logic;
signal drive : std_logic;
signal vld_pipe : unsigned(latency downto 0);
signal drive_pipe : unsigned(latency downto 0);
signal data_pipe : data_pipe_t;
signal ssram_dout : ssram_d_t;
begin
SRDY_O <= CYC_I and dcm_locked;
ACK_O <= vld_pipe(vld_pipe'left);
DAT_O(data_width-1 downto 0) <= ssram_d;
data_en <= CYC_I and STB_I;
ssram_dout <= "0000" & DAT_I(data_width-1 downto 0);
drive <= drive_pipe(drive_pipe'left);
ssram_clk_o <= ssram_clk after topad;
ssram_cke_n <= not dcm_locked after topad;
ssram_oe_n <= not vld_pipe(vld_pipe'left-1) after topad;
inst_clock_out : ODDR
generic map
(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => ssram_clk, -- 1-bit DDR output
C => dcm_clk1, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ssram_bufg: bufg
port map
(
o => dcm_clk1,
i => dcm_clk0
);
inst_DCM_BASE_0 : DCM_BASE
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcm_locked, -- DCM LOCK status output
CLKFB => ssram_clk_fb, -- DCM clock feedback
CLKIN => CLK_I, -- Clock input (from IBUFG, BUFG or DCM)
RST => RST_I -- DCM asynchronous reset input
);
data_valid_pipeline:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
vld_pipe <= (others => '0');
else
vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & (data_en and MRDY_I and not WE_I);
end if;
end if;
end process;
data_out_pipeline:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ssram_ce_n <= '1' after topad;
ssram_we_n <= '1' after topad;
ssram_adv <= '0' after topad;
ssram_mode <= '0' after topad;
ssram_zz <= '1' after topad;
drive_pipe <= (others => '0');
elsif dcm_locked = '1' then
ssram_ce_n <= not data_en after topad;
ssram_we_n <= not (WE_I and data_en) after topad;
ssram_adv <= '0' after topad;
ssram_mode <= '0' after topad;
ssram_zz <= '0' after topad;
ssram_a <= ADDR_I(addr_width-1 downto 0) after topad;
ssram_bw_n <= not SEL_I after topad;
drive_pipe <= drive_pipe(drive_pipe'left-1 downto 0) & (data_en and WE_I);
data_pipe <= data_pipe(data_pipe'left-1 downto 0) & ssram_dout;
end if;
end if;
end process;
ssram_d <= data_pipe(data_pipe'left)(data_width-1 downto 0) after topad when drive = '1' else (others => 'Z') after topad;
ssram_dp <= data_pipe(data_pipe'left)(data_width+parity_width-1 downto data_width) after topad when drive = '1' else (others => 'Z') after topad;
end behavior;
lib/SSRAM/src/tb_ssram_frontend_wb.vhd
+457
View File
@@ -0,0 +1,457 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.package_utility.all;
Library UNISIM;
use UNISIM.vcomponents.all;
ENTITY tb_ssram_frontend_wb IS
END tb_ssram_frontend_wb;
ARCHITECTURE behavior OF tb_ssram_frontend_wb IS
constant CLK_PERIOD : time := 10 ns;
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal WE_O : std_logic := '0';
signal SEL_O : unsigned(3 downto 0) := (others => '1');
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0);
signal DAT_O : unsigned(31 downto 0) := (others => '-');
SIGNAL ssram_d : unsigned (32 - 1 DOWNTO 0) := (OTHERS => 'Z');
SIGNAL ssram_dp : unsigned (4 - 1 DOWNTO 0) := (OTHERS => 'Z');
SIGNAL ssram_a : unsigned (20 - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ssram_clk : STD_LOGIC := '0';
SIGNAL ssram_cke_n : STD_LOGIC;
SIGNAL ssram_adv : STD_LOGIC;
SIGNAL ssram_mode : STD_LOGIC;
SIGNAL ssram_bw_n : unsigned(3 downto 0);
SIGNAL ssram_we_n : STD_LOGIC;
SIGNAL ssram_oe_n : STD_LOGIC;
SIGNAL ssram_ce_n : STD_LOGIC;
SIGNAL ssram_zz : STD_LOGIC;
SIGNAL ssram_clk_fb : STD_LOGIC;
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
BEGIN
ssram_clk_fb <= ssram_clk after 0.5 ns;
inst_ssram_frontend_wb : entity work.ssram_frontend_wb
GENERIC MAP
(
addr_width => 20,
data_width => 32,
parity_width => 4
)
PORT MAP
(
-- J-Bus domain
RST_I => RST_O,
CLK_I => CLK_O,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I,
-- Sync SRAM domain
ssram_clk_o => ssram_clk,
ssram_clk_fb => ssram_clk_fb,
ssram_cke_n => ssram_cke_n,
ssram_ce_n => ssram_ce_n,
ssram_oe_n => ssram_oe_n,
ssram_we_n => ssram_we_n,
ssram_adv => ssram_adv,
ssram_mode => ssram_mode,
ssram_zz => ssram_zz,
ssram_a => ssram_a,
ssram_d => ssram_d,
ssram_dp => ssram_dp,
ssram_bw_n => ssram_bw_n
);
inst_ssram : entity work.cy7c1354
-- PORT MAP Declarations
PORT MAP
(
Dq => STD_LOGIC_VECTOR(ssram_d), -- Data I/O
Dpq => STD_LOGIC_VECTOR(ssram_dp), -- Data I/O
Addr => STD_LOGIC_VECTOR(ssram_a(19 downto 2)), -- Address
Mode => ssram_mode, -- Burst Mode
Clk => ssram_clk, -- Clk
CEN_n => ssram_cke_n, -- CEN#
AdvLd_n => ssram_adv, -- Adv/Ld#
Bwa_n => ssram_bw_n(0), -- Bwa#
Bwb_n => ssram_bw_n(1), -- BWb#
Bwc_n => ssram_bw_n(2), -- Bwc#
Bwd_n => ssram_bw_n(3), -- BWd#
Rw_n => ssram_we_n, -- RW#
Oe_n => ssram_oe_n, -- OE#
Ce1_n => ssram_ce_n, -- CE1#
Ce2 => '1', -- CE2
Ce3_n => '0', -- CE3#
Zz => ssram_zz
);
read_register:
process(CLK_O)
begin
if rising_edge(CLK_O) then
if dout_rst = '1' then
dout_cnt <= 0;
elsif ACK_I = '1' and WE_O = '0' then
dout_reg <= DAT_I;
dout_cnt <= dout_cnt + 1;
end if;
end if;
end process;
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK_O <= not CLK_O;
end process;
STIMULUS: process
begin
wait for 5*CLK_PERIOD;
RST_O <= '0';
wait until rising_edge(CLK_O);
-- 8 single cycles
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"1234_0000";
ADDR_O <= X"0000_0000";
for i in 0 to 31 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 31 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 31;
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "0011";
ADDR_O <= X"0000_0010";
DAT_O <= X"DEADBEEF";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0010";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
------------------------------------------------------------
wait for 3*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 31 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 31;
CYC_O <= '0';
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"1111_0000";
ADDR_O <= X"0000_0000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"2222_0000";
ADDR_O <= X"0000_0400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
WE_O <= '0';
ADDR_O <= X"0000_0400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"3333_0000";
ADDR_O <= X"0000_0800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
WE_O <= '0';
ADDR_O <= X"0000_0800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "1111";
DAT_O <= X"4444_0000";
ADDR_O <= X"0000_0C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
end loop;
WE_O <= '0';
ADDR_O <= X"0000_0C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
------------------------------------------------------------
wait for 10*CLK_PERIOD;
------------------------------------------------------------
-- 8-word burst cycle
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
ADDR_O <= X"0000_0400";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
ADDR_O <= X"0000_0800";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
ADDR_O <= X"0000_0C00";
for i in 0 to 7 loop
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 31;
CYC_O <= '0';
wait;
end process;
END;
lib/VGA_ctrl/sim/ModelSim SE .lnk
BIN
View File
Binary file not shown.
lib/VGA_ctrl/sim/tb_vga_frontend.fdo
+25
View File
@@ -0,0 +1,25 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/async_fifo_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/fonts/char_rom_c64.vhd"
vcom -explicit -93 "../src/vga_types.vhd"
vcom -explicit -93 "../src/clkgen_virtex4.vhd"
vcom -explicit -93 "../src/char_gen.vhd"
vcom -explicit -93 "../src/vga_sync.vhd"
vcom -explicit -93 "../src/vga_timing.vhd"
vcom -explicit -93 "../src/vga_backend.vhd"
vcom -explicit -93 "../src/vga_frontend.vhd"
vcom -explicit -93 "../src/tb_vga_frontend.vhd"
vsim -t 1ps -lib work tb_vga_frontend
view wave
do {tb_vga_frontend.wdo}
view structure
view signals
run 20ms
lib/VGA_ctrl/sim/tb_vga_frontend.wdo
+65
View File
@@ -0,0 +1,65 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_vga_frontend/clk_o
add wave -noupdate -format Logic /tb_vga_frontend/rst_o
add wave -noupdate -divider Master
add wave -noupdate -format Logic /tb_vga_frontend/cyc_o
add wave -noupdate -format Logic /tb_vga_frontend/stb_o
add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_o
add wave -noupdate -format Literal /tb_vga_frontend/sel_o
add wave -noupdate -format Logic /tb_vga_frontend/we_o
add wave -noupdate -format Logic /tb_vga_frontend/ack_i
add wave -noupdate -format Logic /tb_vga_frontend/mrdy_o
add wave -noupdate -format Logic /tb_vga_frontend/srdy_i
add wave -noupdate -divider Slave
add wave -noupdate -format Logic /tb_vga_frontend/cyc_i
add wave -noupdate -format Logic /tb_vga_frontend/stb_i
add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_i
add wave -noupdate -format Literal /tb_vga_frontend/sel_i
add wave -noupdate -format Logic /tb_vga_frontend/we_i
add wave -noupdate -format Logic /tb_vga_frontend/ack_o
add wave -noupdate -format Logic /tb_vga_frontend/mrdy_i
add wave -noupdate -format Logic /tb_vga_frontend/srdy_o
add wave -noupdate -divider VGA
add wave -noupdate -format Logic /tb_vga_frontend/vga_clk_out
add wave -noupdate -format Logic /tb_vga_frontend/vga_blank_n
add wave -noupdate -format Logic /tb_vga_frontend/vga_sync_n
add wave -noupdate -format Logic /tb_vga_frontend/vga_hsync
add wave -noupdate -format Logic /tb_vga_frontend/vga_vsync
add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_red
add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_green
add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_blue
add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/s
add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/request_cnt
add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/read_cnt
add wave -noupdate -divider Backend
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/ctrl_scan_en
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/sys_rst
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_vga_rdy
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_scan
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/scan_enable
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/is_scan
add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_hpos
add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_vpos
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/rst
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/dcm_locked
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_draw
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_en
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/hready
add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/vready
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1420398899 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {1382189057 ps} {1476673938 ps}
lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
+25
View File
@@ -0,0 +1,25 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/async_fifo_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/fonts/char_rom_c64.vhd"
vcom -explicit -93 "../src/vga_types.vhd"
vcom -explicit -93 "../src/clkgen_virtex4.vhd"
vcom -explicit -93 "../src/char_gen.vhd"
vcom -explicit -93 "../src/vga_sync.vhd"
vcom -explicit -93 "../src/vga_timing.vhd"
vcom -explicit -93 "../src/vga_backend.vhd"
vcom -explicit -93 "../src/vga_frontend64.vhd"
vcom -explicit -93 "../src/tb_vga_frontend64.vhd"
vsim -t 1ps -lib work tb_vga_frontend64
view wave
do {tb_vga_frontend64.wdo}
view structure
view signals
run 20ms
lib/VGA_ctrl/sim/tb_vga_frontend64.wdo
+65
View File
@@ -0,0 +1,65 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
add wave -noupdate -format Logic /tb_vga_frontend64/rst_o
add wave -noupdate -divider Master
add wave -noupdate -format Logic /tb_vga_frontend64/cyc_o
add wave -noupdate -format Logic /tb_vga_frontend64/stb_o
add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/addr_o
add wave -noupdate -format Literal /tb_vga_frontend64/sel_o
add wave -noupdate -format Logic /tb_vga_frontend64/we_o
add wave -noupdate -format Logic /tb_vga_frontend64/ack_i
add wave -noupdate -format Logic /tb_vga_frontend64/mrdy_o
add wave -noupdate -format Logic /tb_vga_frontend64/srdy_i
add wave -noupdate -divider Slave
add wave -noupdate -format Logic /tb_vga_frontend64/cyc_i
add wave -noupdate -format Logic /tb_vga_frontend64/stb_i
add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/addr_i
add wave -noupdate -format Literal /tb_vga_frontend64/sel_i
add wave -noupdate -format Logic /tb_vga_frontend64/we_i
add wave -noupdate -format Logic /tb_vga_frontend64/ack_o
add wave -noupdate -format Logic /tb_vga_frontend64/mrdy_i
add wave -noupdate -format Logic /tb_vga_frontend64/srdy_o
add wave -noupdate -divider VGA
add wave -noupdate -format Logic /tb_vga_frontend64/vga_clk_out
add wave -noupdate -format Logic /tb_vga_frontend64/vga_blank_n
add wave -noupdate -format Logic /tb_vga_frontend64/vga_sync_n
add wave -noupdate -format Logic /tb_vga_frontend64/vga_hsync
add wave -noupdate -format Logic /tb_vga_frontend64/vga_vsync
add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_red
add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_green
add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_blue
add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/request_cnt
add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/read_cnt
add wave -noupdate -divider Backend
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/ctrl_scan_en
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/sys_rst
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_vga_rdy
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_scan
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/scan_enable
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/is_scan
add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_hpos
add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_vpos
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/rst
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/dcm_locked
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_draw
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_en
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/hready
add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/vready
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1420398899 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {1382189057 ps} {1476673938 ps}
lib/VGA_ctrl/src/char_gen.vhd
+1 -1
View File
@@ -206,7 +206,7 @@ begin
DATA => char_rom_data
);
inst_ascii_ram: entity work.dpram
inst_ascii_ram: entity work.dpram_1w1r
GENERIC MAP (
addr_width => A_RAM_ADDR_WIDTH,
data_width => A_RAM_DATA_WIDTH
lib/VGA_ctrl/src/dpram.vhd
-79
View File
@@ -1,79 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram;
architecture Behavioral of dpram is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/VGA_ctrl/src/tb_vga_frontend.vhd
+201
View File
@@ -0,0 +1,201 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use work.vga_types.all;
ENTITY tb_vga_frontend IS
END tb_vga_frontend;
ARCHITECTURE behavior OF tb_vga_frontend IS
constant CLK_PERIOD : time := 10 ns;
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
-- Master
signal CYC_O : std_logic;
signal STB_O : std_logic;
signal WE_O : std_logic;
signal SEL_O : unsigned(3 downto 0) := (others => '1');
signal ACK_I : std_logic := '0';
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic := '0';
signal ADDR_O : unsigned(31 downto 0);
signal MDAT_I : unsigned(31 downto 0);
signal MDAT_O : unsigned(31 downto 0);
-- Slave
signal CYC_I : std_logic := '0';
signal STB_I : std_logic := '0';
signal WE_I : std_logic := '0';
signal SEL_I : unsigned(3 downto 0);
signal ACK_O : std_logic;
signal MRDY_I : std_logic;
signal SRDY_O : std_logic;
signal ADDR_I : unsigned(31 downto 0) := (others => '-');
signal SDAT_I : unsigned(31 downto 0) := (others => '-');
signal SDAT_O : unsigned(31 downto 0);
-- VGA signals
signal vga_clk_out : std_logic;
signal vga_red : unsigned(7 downto 0);
signal vga_green : unsigned(7 downto 0);
signal vga_blue : unsigned(7 downto 0);
signal vga_blank_n : std_logic;
signal vga_sync_n : std_logic;
signal vga_hsync : std_logic;
signal vga_vsync : std_logic;
BEGIN
inst_vga_frontend : entity work.vga_frontend
GENERIC MAP
(
sys_freq => 100E6,
fifo_depth => 2048,
fifo_almost_full_thresh => 2000,
fifo_almost_empty_thresh => 48,
tsvga => ts_vga_800_600_72
)
PORT MAP
(
-- System signals
RST_I => RST_O,
CLK_I => CLK_O,
-- JBUS Master signals
CYC_O => CYC_I,
STB_O => STB_I,
WE_O => WE_I,
SEL_O => SEL_I,
ACK_I => ACK_O,
SRDY_I => SRDY_O,
MRDY_O => MRDY_I,
ADDR_O => ADDR_I,
MDAT_I => MDAT_O,
MDAT_O => MDAT_I,
-- JBUS Slave signals
CYC_I => CYC_O,
STB_I => STB_O,
WE_I => WE_O,
SEL_I => SEL_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
SDAT_I => SDAT_O,
SDAT_O => SDAT_I,
-- VGA signals
vga_clk_out => vga_clk_out,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_blank_n => vga_blank_n,
vga_sync_n => vga_sync_n,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK_O <= not CLK_O;
end process;
-- Slave
SRDY_O <= CYC_I;
process(CLK_O)
begin
if rising_edge(CLK_O) then
if RST_O = '1' then
MDAT_O <= X"00000000";
elsif (CYC_I and STB_I) = '1' then
MDAT_O <= MDAT_O + 1;
ACK_O <= '1';
else
ACK_O <= '0';
end if;
end if;
end process;
-- Master
STIMULUS: process
begin
wait for 6*CLK_PERIOD;
RST_O <= '0';
-- 8 single cycles
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_I <= X"0000_0000";
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_I <= X"0000_0000";
ADDR_O <= X"0000_0010";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_I <= X"0000_0035";
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_I <= X"0000_0035";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
wait;
end process;
END;
lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+201
View File
@@ -0,0 +1,201 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use work.vga_types.all;
ENTITY tb_vga_frontend64 IS
END tb_vga_frontend64;
ARCHITECTURE behavior OF tb_vga_frontend64 IS
constant CLK_PERIOD : time := 10 ns;
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
-- Master
signal CYC_O : std_logic;
signal STB_O : std_logic;
signal WE_O : std_logic;
signal SEL_O : unsigned(3 downto 0) := (others => '1');
signal ACK_I : std_logic := '0';
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic := '0';
signal ADDR_O : unsigned(31 downto 0);
signal MDAT_I : unsigned(63 downto 0);
signal MDAT_O : unsigned(63 downto 0);
-- Slave
signal CYC_I : std_logic := '0';
signal STB_I : std_logic := '0';
signal WE_I : std_logic := '0';
signal SEL_I : unsigned(7 downto 0);
signal ACK_O : std_logic;
signal MRDY_I : std_logic;
signal SRDY_O : std_logic;
signal ADDR_I : unsigned(31 downto 0) := (others => '-');
signal SDAT_I : unsigned(31 downto 0) := (others => '-');
signal SDAT_O : unsigned(31 downto 0);
-- VGA signals
signal vga_clk_out : std_logic;
signal vga_red : unsigned(7 downto 0);
signal vga_green : unsigned(7 downto 0);
signal vga_blue : unsigned(7 downto 0);
signal vga_blank_n : std_logic;
signal vga_sync_n : std_logic;
signal vga_hsync : std_logic;
signal vga_vsync : std_logic;
BEGIN
inst_vga_frontend64 : entity work.vga_frontend64
GENERIC MAP
(
sys_freq => 100E6,
fifo_depth => 2048,
fifo_almost_full_thresh => 2000,
fifo_almost_empty_thresh => 48,
tsvga => ts_vga_800_600_72
)
PORT MAP
(
-- System signals
RST_I => RST_O,
CLK_I => CLK_O,
-- JBUS Master signals
CYC_O => CYC_I,
STB_O => STB_I,
WE_O => WE_I,
SEL_O => SEL_I,
ACK_I => ACK_O,
SRDY_I => SRDY_O,
MRDY_O => MRDY_I,
ADDR_O => ADDR_I,
MDAT_I => MDAT_O,
MDAT_O => MDAT_I,
-- JBUS Slave signals
CYC_I => CYC_O,
STB_I => STB_O,
WE_I => WE_O,
SEL_I => SEL_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
SDAT_I => SDAT_O,
SDAT_O => SDAT_I,
-- VGA signals
vga_clk_out => vga_clk_out,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_blank_n => vga_blank_n,
vga_sync_n => vga_sync_n,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK_O <= not CLK_O;
end process;
-- Slave
SRDY_O <= CYC_I;
process(CLK_O)
begin
if rising_edge(CLK_O) then
if RST_O = '1' then
MDAT_O <= X"00000000_00000000";
elsif (CYC_I and STB_I) = '1' then
MDAT_O <= MDAT_O + 1;
ACK_O <= '1';
else
ACK_O <= '0';
end if;
end if;
end process;
-- Master
STIMULUS: process
begin
wait for 6*CLK_PERIOD;
RST_O <= '0';
-- 8 single cycles
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_I <= X"0000_0000";
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_I <= X"0000_0000";
ADDR_O <= X"0000_0010";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_I <= X"0000_0035";
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_I <= X"0000_0035";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
wait;
end process;
END;
lib/VGA_ctrl/src/vga_backend.vhd
+32 -60
View File
@@ -27,9 +27,6 @@ entity vga_backend is
Generic
(
sys_freq : integer := 100E6;
fifo_depth : integer := 2048;
fifo_almost_full_thresh : natural := 2000;
fifo_almost_empty_thresh : natural := 48;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
Port
@@ -37,19 +34,18 @@ entity vga_backend is
-- System signals
sys_rst : in std_logic;
sys_clk : in std_logic;
vga_ready : out std_logic;
-- Buffered channel (Graphics plane)
color_in : in color_t;
color_fifo_we : in std_logic;
color_fifo_full : out std_logic;
color_fifo_afull : out std_logic;
-- Color channels
color_in : in color_array_t;
color_op : in color_op_t;
color_en : unsigned (VGA_NUM_CH-1 downto 0);
-- Control signals
ctrl_scan_en : in std_logic;
-- Direct channel (Character plane)
direct_color_in : in color_t;
direct_draw_en : in std_logic;
-- Status signals
stat_vga_rdy : out std_logic;
stat_scan : out std_logic;
stat_hsync : out std_logic;
stat_vsync : out std_logic;
stat_hready : out std_logic;
@@ -61,7 +57,9 @@ entity vga_backend is
-- VGA domain signals
vga_clk_out : out std_logic;
vga_color_out : out color_t;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
vga_blank_n : out std_logic;
vga_sync_n : out std_logic;
vga_hsync : out std_logic;
@@ -72,10 +70,6 @@ end vga_backend;
architecture Behavioral of vga_backend is
signal scan_enable : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almost_empty : std_logic;
signal fifo_almost_full : std_logic;
signal is_scan : std_logic;
signal is_hscan : std_logic;
signal is_vscan : std_logic;
@@ -83,7 +77,6 @@ architecture Behavioral of vga_backend is
signal vsync : std_logic;
signal hready : std_logic;
signal vready : std_logic;
signal color : color_t;
signal vga_clk : std_logic;
signal dcm_locked : std_logic;
signal rst : std_logic;
@@ -91,9 +84,8 @@ architecture Behavioral of vga_backend is
begin
vga_clk_out <= vga_clk;
vga_ready <= dcm_locked;
inst_clkgen: entity work.clkgen
inst_clkgen: entity work.clkgen
GENERIC MAP
(
sys_freq => sys_freq,
@@ -107,7 +99,7 @@ begin
dcm_locked => dcm_locked
);
inst_vga_timing: entity work.vga_timing
inst_vga_timing: entity work.vga_timing
GENERIC MAP
(
tsvga => tsvga
@@ -127,44 +119,21 @@ begin
scan_rdy_v => vready
);
inst_linefifo: entity work.linefifo
GENERIC MAP
(
depth => fifo_depth,
almost_full_thresh => fifo_almost_full_thresh,
almost_empty_thresh => fifo_almost_empty_thresh
)
PORT MAP(
rst => sys_rst,
clk_w => sys_clk,
clk_r => vga_clk,
we_w => color_fifo_we,
re_r => is_scan,
color_w => color_in,
color_r => color,
fifo_full => fifo_full,
fifo_empty => fifo_empty,
fifo_afull => fifo_almost_full,
fifo_aempty => fifo_almost_empty
);
---------------------------------------------------------------------------------------------
rst <= not dcm_locked;
stat_vga_rdy <= dcm_locked;
stat_hsync <= hsync;
stat_vsync <= vsync;
stat_hscan <= is_hscan;
stat_vscan <= is_vscan;
stat_hready <= hready;
stat_vready <= vready;
stat_scan <= is_scan;
vga_blank_n <= '1';
vga_sync_n <= '0';
is_scan <= is_hscan and is_vscan and scan_enable;
color_fifo_full <= fifo_full;
color_fifo_afull <= fifo_almost_full;
---------------------------------------------------------------------------------------------
proc_vga_start:
process (rst, vga_clk)
@@ -173,7 +142,7 @@ begin
scan_enable <= '0';
elsif rising_edge(vga_clk) then
if vsync = '1' then
if fifo_empty = '0' then
if ctrl_scan_en = '1' then
scan_enable <= '1';
else
scan_enable <= '0';
@@ -183,21 +152,24 @@ begin
end process;
proc_vga_color_out:
process (rst, vga_clk)
process (vga_clk)
variable do_scan : std_logic;
variable color : color_t;
begin
if rst = '1' then
do_scan := '0';
elsif rising_edge(vga_clk) then
vga_color_out <= (X"00", X"00", X"00");
if do_scan = '1' then
if direct_draw_en = '1' then
vga_color_out <= direct_color_in;
else
vga_color_out <= color;
end if;
if rising_edge(vga_clk) then
vga_red <= X"00";
vga_green <= X"00";
vga_blue <= X"00";
if is_scan = '1' then
for i in 0 to VGA_NUM_CH-1 loop
color := color_in(i);
if color_en(i) = '1' then
vga_red <= color(r); -- ToDo: color_op over channels
vga_green <= color(g); -- ToDo: color_op over channels
vga_blue <= color(b); -- ToDo: color_op over channels
end if;
end loop;
end if;
do_scan := is_scan;
end if;
end process;
lib/VGA_ctrl/src/vga_frontend.vhd
+422
View File
@@ -0,0 +1,422 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:45 10/15/05
-- Design Name:
-- Module Name: vga_backend - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vga_types.all;
entity vga_frontend is
Generic
(
sys_freq : integer := 100E6;
fifo_depth : integer := 2048;
fifo_almost_full_thresh : natural := 2000;
fifo_almost_empty_thresh : natural := 48;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
Port
(
-- System signals
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
-- JBUS Master signals
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
MRDY_O : out STD_LOGIC;
ADDR_O : out unsigned(31 downto 0);
MDAT_I : in unsigned(31 downto 0);
MDAT_O : out unsigned(31 downto 0);
-- JBUS Slave signals
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
SDAT_I : in unsigned(31 downto 0);
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_out : out std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
vga_blank_n : out std_logic;
vga_sync_n : out std_logic;
vga_hsync : out std_logic;
vga_vsync : out std_logic
);
end vga_frontend;
architecture Behavioral of vga_frontend is
signal vga_clk : std_logic;
-- Color FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almost_empty : std_logic;
signal fifo_almost_full : std_logic;
signal fifo_color_re : std_logic;
signal fifo_color_we : std_logic;
signal fifo_color_out : unsigned(31 downto 0);
signal fifo_color_in : unsigned(31 downto 0);
-- Backend signals
signal scan_rdy : std_logic;
signal ctrl_scan_en : std_logic;
signal color_in : color_array_t;
signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic;
signal stat_vready : std_logic;
signal stat_scan : std_logic;
signal stat_hscan : std_logic;
signal stat_vscan : std_logic;
signal stat_hsync : std_logic;
signal stat_vsync : std_logic;
signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1;
-- CG signals
signal cg_en : std_logic;
signal cg_rdy : std_logic;
signal cg_draw : std_logic;
signal cg_clr_screen : std_logic;
signal cg_clr_line : std_logic;
signal cg_ascii_data : unsigned(7 downto 0);
signal cg_ascii_data_we : std_logic;
signal cg_ascii_posy_we : std_logic;
signal cg_ascii_posx_we : std_logic;
-- Bus master signals
constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
signal vga_mem_offset : unsigned(31 downto 0);
signal vga_scan_rdy : std_logic;
signal vga_master_en : std_logic;
signal request_cnt_rst : std_logic;
signal request_cnt_en : std_logic;
signal pixel_cnt_rst : std_logic;
signal read_bus_en : std_logic;
signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1;
type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
signal s, sn : vm_state_t;
begin
vga_clk_out <= vga_clk;
inst_vga_backend : entity work.vga_backend
GENERIC MAP
(
sys_freq => sys_freq,
tsvga => tsvga
)
PORT MAP
(
-- System signals
sys_rst => RST_I,
sys_clk => CLK_I,
-- Color channels
color_in => color_in,
color_op => color_op,
color_en => color_en,
-- Control signals
ctrl_scan_en => ctrl_scan_en,
-- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan,
stat_hsync => stat_hsync,
stat_vsync => stat_vsync,
stat_hready => stat_hready,
stat_vready => stat_vready,
stat_hscan => stat_hscan,
stat_vscan => stat_vscan,
stat_hpos => stat_hpos,
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_out => vga_clk,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_blank_n => vga_blank_n,
vga_sync_n => vga_sync_n,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
ctrl_scan_en <= '1';
color_en(0) <= not fifo_empty;
color_en(1) <= cg_draw;
color_in(0) <= to_color_t(fifo_color_out);
color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque
color_op <= op_over;
vga_scan_rdy <= stat_hready and stat_vready;
inst_linefifo: entity work.fifo_async
GENERIC MAP
(
addr_width => NextExpBaseTwo(fifo_depth),
data_width => 32,
almost_full_thresh => fifo_almost_full_thresh,
almost_empty_thresh => fifo_almost_empty_thresh
)
PORT MAP
(
rst => RST_I,
clk_w => CLK_I,
clk_r => vga_clk,
we_w => fifo_color_we,
re_r => fifo_color_re,
data_w => fifo_color_in,
data_r => fifo_color_out,
fifo_full => fifo_full,
fifo_empty => fifo_empty,
fifo_afull => fifo_almost_full,
fifo_aempty => fifo_almost_empty
);
fifo_color_in <= MDAT_I;
fifo_color_re <= stat_scan;
fifo_color_we <= ACK_I and read_bus_en; -- TODO:
MRDY_O <= not fifo_full;
SEL_O <= (others => '0');
WE_O <= '0';
vga_master_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= init;
else
s <= sn;
end if;
end if;
end process;
vga_master:
process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
begin
CYC_O <= '0';
STB_O <= '0';
pixel_cnt_rst <= '0';
request_cnt_rst <= '0';
request_cnt_en <= '0';
read_bus_en <= '0';
sn <= s;
case s is
when init =>
if stat_vga_rdy = '1' then
sn <= idle;
end if;
when idle =>
pixel_cnt_rst <= '1';
if vga_master_en = '1' and vga_scan_rdy = '1' then
sn <= rdy;
end if;
when rdy =>
-- pixel_cnt_rst <= '1';
if fifo_almost_empty = '1' then
sn <= bus_request;
end if;
when bus_request =>
CYC_O <= '1';
request_cnt_rst <= '1';
if SRDY_I = '1' then
sn <= bus_access;
end if;
when bus_access =>
CYC_O <= '1';
STB_O <= '1';
request_cnt_en <= '1';
read_bus_en <= '1';
if fifo_almost_full = '1' then
sn <= bus_data;
end if;
when bus_data =>
CYC_O <= '1';
read_bus_en <= '1';
if read_cnt = request_cnt then
sn <= rdy;
if vga_master_en = '0' then
sn <= idle;
end if;
end if;
when others =>
sn <= idle;
end case;
end process;
request_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= 0;
elsif request_cnt_en = '1' and SRDY_I = '1' then
if request_cnt /= MAX_REQUEST_CNT-1 then
request_cnt <= request_cnt + 1;
end if;
end if;
end if;
end process;
read_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
read_cnt <= 0;
elsif read_bus_en = '1' and ACK_I = '1' then
if read_cnt /= MAX_REQUEST_CNT-1 then
read_cnt <= read_cnt + 1;
end if;
end if;
end if;
end process;
pixel_counter:
process(CLK_I)
variable pixel_cntx : natural range 0 to tsvga.ts_h.ncyc_scan-1;
variable pixel_cnty : natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
begin
if rising_edge(CLK_I) then
if pixel_cnt_rst = '1' then
pixel_cntx := 0;
pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
elsif request_cnt_en = '1' and SRDY_I = '1' then
if pixel_cntx /= tsvga.ts_h.ncyc_scan-1 then
pixel_cntx := pixel_cntx + 1;
else
pixel_cntx := 0;
if pixel_cnty /= 0 then
pixel_cnty := pixel_cnty - tsvga.ts_h.ncyc_scan;
else
pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
end if;
end if;
end if;
ADDR_O <= vga_mem_offset + (to_unsigned(pixel_cntx, 30) & "00") + (to_unsigned(pixel_cnty, 30) & "00");
end if;
end process;
inst_char_gen : entity work.char_gen
GENERIC MAP
(
tsvga => tsvga,
CHARACTER_SCALE => 1,
CHAR_ROM_SIZE_X => 8, -- Pixels
CHAR_ROM_SIZE_Y => 16, -- Pixels
CHAR_ROM_DEPTH => 256, -- Chars
MAX_CHAR_PER_LINE => 80, -- Chars
MAX_LINE_PER_FRAME => 32, -- Chars
CHAR_SPACING_X => 0, -- Pixels
CHAR_SPACING_Y => 0, -- Pixels
SCREEN_OFFSET_X => 16, -- Pixels
SCREEN_OFFSET_Y => 16 -- Pixels
)
PORT MAP
(
rst => RST_I,
sys_clk => CLK_I,
vga_clk => vga_clk,
ce => cg_en,
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,
clr_line => cg_clr_line,
ascii_data => cg_ascii_data,
ascii_data_we => cg_ascii_data_we,
ascii_posy_we => cg_ascii_posy_we,
ascii_posx_we => cg_ascii_posx_we,
ready => cg_rdy,
pos_x => stat_hpos,
pos_y => stat_vpos,
char_draw_en => cg_draw
);
SRDY_O <= CYC_I; -- and cg_rdy;
cg_ascii_data <= SDAT_I(7 downto 0);
cg_ascii_data_we <= ADDR_I(2) and CYC_I and STB_I and WE_I;
cg_ascii_posy_we <= ADDR_I(3) and CYC_I and STB_I and WE_I;
cg_ascii_posx_we <= ADDR_I(4) and CYC_I and STB_I and WE_I;
cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I;
cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I;
SDAT_O <= X"0000000" & "000" & cg_rdy;
scan_rdy <= stat_hready and stat_vready;
cg_en <= stat_scan;
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= CYC_I and STB_I and not WE_I;
end if;
end if;
end process;
data_valid_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
vga_master_en <= '0';
vga_mem_offset <= X"40000000";
elsif (CYC_I and STB_I and WE_I) = '1' then
if ADDR_I(8) = '1' then
vga_master_en <= SDAT_I(0);
elsif ADDR_I(9) = '1' then
vga_mem_offset <= SDAT_I(31 downto 2) & "00";
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------
end Behavioral;
lib/VGA_ctrl/src/vga_frontend64.vhd
+426
View File
@@ -0,0 +1,426 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:45 10/15/05
-- Design Name:
-- Module Name: vga_backend - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vga_types.all;
entity vga_frontend64 is
Generic
(
sys_freq : integer := 100E6;
fifo_depth : integer := 2048;
fifo_almost_full_thresh : natural := 2000;
fifo_almost_empty_thresh : natural := 48;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
Port
(
-- System signals
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
-- JBUS Master signals
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(7 downto 0);
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
MRDY_O : out STD_LOGIC;
ADDR_O : out unsigned(31 downto 0);
MDAT_I : in unsigned(63 downto 0);
MDAT_O : out unsigned(63 downto 0);
-- JBUS Slave signals
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
SDAT_I : in unsigned(31 downto 0);
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_out : out std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
vga_blank_n : out std_logic;
vga_sync_n : out std_logic;
vga_hsync : out std_logic;
vga_vsync : out std_logic
);
end vga_frontend64;
architecture Behavioral of vga_frontend64 is
signal vga_clk : std_logic;
-- Color FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almost_empty : std_logic;
signal fifo_almost_full : std_logic;
signal fifo_color_re : std_logic;
signal fifo_color_we : std_logic;
signal fifo_color_out : unsigned(63 downto 0);
signal fifo_color_in : unsigned(63 downto 0);
-- Backend signals
signal scan_rdy : std_logic;
signal ctrl_scan_en : std_logic;
signal color_in : color_array_t;
signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic;
signal stat_vready : std_logic;
signal stat_scan : std_logic;
signal stat_hscan : std_logic;
signal stat_vscan : std_logic;
signal stat_hsync : std_logic;
signal stat_vsync : std_logic;
signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1;
-- CG signals
signal cg_en : std_logic;
signal cg_rdy : std_logic;
signal cg_draw : std_logic;
signal cg_clr_screen : std_logic;
signal cg_clr_line : std_logic;
signal cg_ascii_data : unsigned(7 downto 0);
signal cg_ascii_data_we : std_logic;
signal cg_ascii_posy_we : std_logic;
signal cg_ascii_posx_we : std_logic;
-- Bus master signals
constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
signal vga_mem_offset : unsigned(31 downto 0);
signal vga_scan_rdy : std_logic;
signal vga_master_en : std_logic;
signal request_cnt_rst : std_logic;
signal request_cnt_en : std_logic;
signal pixel_cnt_rst : std_logic;
signal read_bus_en : std_logic;
signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
signal s, sn : vm_state_t;
begin
vga_clk_out <= vga_clk;
inst_vga_backend : entity work.vga_backend
GENERIC MAP
(
sys_freq => sys_freq,
tsvga => tsvga
)
PORT MAP
(
-- System signals
sys_rst => RST_I,
sys_clk => CLK_I,
-- Color channels
color_in => color_in,
color_op => color_op,
color_en => color_en,
-- Control signals
ctrl_scan_en => ctrl_scan_en,
-- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan,
stat_hsync => stat_hsync,
stat_vsync => stat_vsync,
stat_hready => stat_hready,
stat_vready => stat_vready,
stat_hscan => stat_hscan,
stat_vscan => stat_vscan,
stat_hpos => stat_hpos,
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_out => vga_clk,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_blank_n => vga_blank_n,
vga_sync_n => vga_sync_n,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length);
ctrl_scan_en <= '1';
color_en(0) <= not fifo_empty;
color_en(1) <= cg_draw;
color_in(0) <= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32));
color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque
color_op <= op_over;
vga_scan_rdy <= stat_hready and stat_vready;
inst_linefifo: entity work.fifo_async
GENERIC MAP
(
addr_width => NextExpBaseTwo(fifo_depth),
data_width => 64,
almost_full_thresh => fifo_almost_full_thresh,
almost_empty_thresh => fifo_almost_empty_thresh
)
PORT MAP
(
rst => RST_I,
clk_w => CLK_I,
clk_r => vga_clk,
we_w => fifo_color_we,
re_r => fifo_color_re,
data_w => fifo_color_in,
data_r => fifo_color_out,
fifo_full => fifo_full,
fifo_empty => fifo_empty,
fifo_afull => fifo_almost_full,
fifo_aempty => fifo_almost_empty
);
fifo_color_in <= MDAT_I;
fifo_color_re <= stat_scan and odd_pixel(0);
fifo_color_we <= ACK_I and read_bus_en; -- TODO:
MRDY_O <= not fifo_full;
SEL_O <= (others => '0');
WE_O <= '0';
vga_master_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= init;
else
s <= sn;
end if;
end if;
end process;
vga_master:
process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
begin
CYC_O <= '0';
STB_O <= '0';
pixel_cnt_rst <= '0';
request_cnt_rst <= '0';
request_cnt_en <= '0';
read_bus_en <= '0';
sn <= s;
case s is
when init =>
if stat_vga_rdy = '1' then
sn <= idle;
end if;
when idle =>
pixel_cnt_rst <= '1';
if vga_master_en = '1' and vga_scan_rdy = '1' then
sn <= rdy;
end if;
when rdy =>
-- pixel_cnt_rst <= '1';
if fifo_almost_empty = '1' then
sn <= bus_request;
end if;
when bus_request =>
CYC_O <= '1';
request_cnt_rst <= '1';
if SRDY_I = '1' then
sn <= bus_access;
end if;
when bus_access =>
CYC_O <= '1';
STB_O <= '1';
request_cnt_en <= '1';
read_bus_en <= '1';
if fifo_almost_full = '1' then
sn <= bus_data;
end if;
when bus_data =>
CYC_O <= '1';
read_bus_en <= '1';
if read_cnt = request_cnt then
sn <= rdy;
if vga_master_en = '0' then
sn <= idle;
end if;
end if;
when others =>
sn <= idle;
end case;
end process;
request_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= 0;
elsif request_cnt_en = '1' and SRDY_I = '1' then
if request_cnt /= MAX_REQUEST_CNT-1 then
request_cnt <= request_cnt + 1;
end if;
end if;
end if;
end process;
read_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
read_cnt <= 0;
elsif read_bus_en = '1' and ACK_I = '1' then
if read_cnt /= MAX_REQUEST_CNT-1 then
read_cnt <= read_cnt + 1;
end if;
end if;
end if;
end process;
pixel_counter:
process(CLK_I)
variable pixel_cntx : natural range 0 to tsvga.ts_h.ncyc_scan/2-1;
variable pixel_cnty : natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
begin
if rising_edge(CLK_I) then
if pixel_cnt_rst = '1' then
pixel_cntx := 0;
pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
elsif request_cnt_en = '1' and SRDY_I = '1' then
if pixel_cntx /= tsvga.ts_h.ncyc_scan/2-1 then
pixel_cntx := pixel_cntx + 1;
else
pixel_cntx := 0;
if pixel_cnty /= 0 then
pixel_cnty := pixel_cnty - tsvga.ts_h.ncyc_scan;
else
pixel_cnty := tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
end if;
end if;
end if;
ADDR_O <= vga_mem_offset + (to_unsigned(pixel_cntx, 29) & "000") + (to_unsigned(pixel_cnty, 30) & "00");
end if;
end process;
inst_char_gen : entity work.char_gen
GENERIC MAP
(
tsvga => tsvga,
CHARACTER_SCALE => 1,
CHAR_ROM_SIZE_X => 8, -- Pixels
CHAR_ROM_SIZE_Y => 16, -- Pixels
CHAR_ROM_DEPTH => 256, -- Chars
MAX_CHAR_PER_LINE => 80, -- Chars
MAX_LINE_PER_FRAME => 32, -- Chars
CHAR_SPACING_X => 0, -- Pixels
CHAR_SPACING_Y => 0, -- Pixels
SCREEN_OFFSET_X => 16, -- Pixels
SCREEN_OFFSET_Y => 16 -- Pixels
)
PORT MAP
(
rst => RST_I,
sys_clk => CLK_I,
vga_clk => vga_clk,
ce => cg_en,
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,
clr_line => cg_clr_line,
ascii_data => cg_ascii_data,
ascii_data_we => cg_ascii_data_we,
ascii_posy_we => cg_ascii_posy_we,
ascii_posx_we => cg_ascii_posx_we,
ready => cg_rdy,
pos_x => stat_hpos,
pos_y => stat_vpos,
char_draw_en => cg_draw
);
SRDY_O <= CYC_I; -- and cg_rdy;
cg_ascii_data <= SDAT_I(7 downto 0);
cg_ascii_data_we <= ADDR_I(2) and CYC_I and STB_I and WE_I;
cg_ascii_posy_we <= ADDR_I(3) and CYC_I and STB_I and WE_I;
cg_ascii_posx_we <= ADDR_I(4) and CYC_I and STB_I and WE_I;
cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I;
cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I;
SDAT_O <= X"0000000" & "000" & cg_rdy;
scan_rdy <= stat_hready and stat_vready;
cg_en <= stat_scan;
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= CYC_I and STB_I and not WE_I;
end if;
end if;
end process;
data_valid_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
vga_master_en <= '0';
vga_mem_offset <= X"40000000";
elsif (CYC_I and STB_I and WE_I) = '1' then
if ADDR_I(8) = '1' then
vga_master_en <= SDAT_I(0);
elsif ADDR_I(9) = '1' then
vga_mem_offset <= SDAT_I(31 downto 2) & "00";
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------
end Behavioral;
lib/VGA_ctrl/src/vga_types.vhd
+32 -4
View File
@@ -12,10 +12,14 @@ use IEEE.MATH_REAL.ALL;
package vga_types is
-- Constants
constant VGA_NUM_CH : natural := 2;
-- Types
type color_range_t is (r, g, b);
type color_range_t is (r, g, b, a);
type color_t is array (color_range_t) of unsigned(7 downto 0);
type color_array_t is array (0 to VGA_NUM_CH-1) of color_t;
type color_op_t is (op_over, op_xor, op_alpha);
type scan_timespec_t is
record
@@ -42,8 +46,8 @@ package vga_types is
(
f_pxl_clk => 100E6,
nfps => 6,
ts_h => (8,5,2,3,'0'),
ts_v => (6,4,2,3,'0')
ts_h => (80,5,2,3,'0'),
ts_v => (60,4,2,3,'0')
);
-- 640 x 480 @ 60 Hz (not recommended)
@@ -127,6 +131,9 @@ package vga_types is
function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural;
function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural;
function to_color_t(x : unsigned) return color_t;
function to_unsigned(x : color_t) return unsigned;
end vga_types;
@@ -207,7 +214,28 @@ package body vga_types is
end DCM_PERIOD;
function to_color_t(x : unsigned) return color_t is
variable result : color_t;
begin
result(r) := x(x'right+7 downto x'right+0);
result(g) := x(x'right+15 downto x'right+8);
result(b) := x(x'right+23 downto x'right+16);
result(a) := x(x'right+31 downto x'right+24);
return result;
end to_color_t;
function to_unsigned(x : color_t) return unsigned is
variable result : unsigned(31 downto 0);
begin
result(7 downto 0) := x(r);
result(15 downto 8) := x(g);
result(23 downto 16) := x(b);
result(31 downto 24) := x(a);
return result;
end to_unsigned;
end vga_types;
lib/ac97_ctrl/sim/tb_ac97_wb.fdo
+20
View File
@@ -0,0 +1,20 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
##
vlib work
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/sync_fifo_ctrl.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r_dist.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_sync_dist.vhd"
vcom -explicit -93 "../../misc/singleshot.vhd"
vcom -explicit -93 "../src/core/ac_out.vhd"
vcom -explicit -93 "../src/core/ac_in.vhd"
vcom -explicit -93 "../src/core/ac_io.vhd"
vcom -explicit -93 "../src/core/ac97_wb.vhd"
vcom -explicit -93 "../src/tb_ac97_wb.vhd"
vsim -t 1ps -lib work tb_ac97_wb
do {tb_ac97_wb.wdo}
view wave
view structure
view signals
run 700us
lib/ac97_ctrl/sim/tb_ac97_wb.wdo
+77
View File
@@ -0,0 +1,77 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ac97_wb/clk_o
add wave -noupdate -format Logic /tb_ac97_wb/rst_o
add wave -noupdate -format Logic /tb_ac97_wb/int_i
add wave -noupdate -format Logic /tb_ac97_wb/cyc_o
add wave -noupdate -format Logic /tb_ac97_wb/stb_o
add wave -noupdate -format Logic /tb_ac97_wb/we_o
add wave -noupdate -format Logic /tb_ac97_wb/ack_i
add wave -noupdate -format Logic /tb_ac97_wb/mrdy_o
add wave -noupdate -format Logic /tb_ac97_wb/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_o
add wave -noupdate -format Logic /tb_ac97_wb/dout_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dout_reg
add wave -noupdate -format Literal /tb_ac97_wb/dout_cnt
add wave -noupdate -format Logic /tb_ac97_wb/ac97_bit_clk
add wave -noupdate -format Logic /tb_ac97_wb/ac97_reset_n
add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_out
add wave -noupdate -format Logic /tb_ac97_wb/ac97_ssync
add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_in
add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_reg_we
add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_pending
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_data
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_addr
add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_cmd_we
add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_tx_pcm_we
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/stat_reg
add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_reg_re
add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_pending
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_data
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_addr
add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_tx_pcm_addr
add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_rx_pcm_addr
add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_sync_strobe
add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_slot_valid
add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_ready
add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_data_start
add wave -noupdate -format Logic /tb_ac97_wb/clk_o
add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_status
add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_frame
add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_frame_valid
add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_tx
add wave -noupdate -format Literal /tb_ac97_wb/uut/request
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_dout
add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_re
add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_we
add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_full
add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_empty
add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_data_start
add wave -noupdate -format Logic /tb_ac97_wb/clk_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_dout
add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_re
add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_we
add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_full
add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_empty
add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac97_stat
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {200000401 ps} 0} {{Cursor 2} {699514236 ps} 0} {{Cursor 4} {4999959266 ps} 0}
configure wave -namecolwidth 173
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {699260742 ps} {700038909 ps}
lib/ac97_ctrl/sim/tb_ac_in.fdo
+14
View File
@@ -0,0 +1,14 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
##
vlib work
vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd"
vcom -explicit -93 "../src/core/ac_out.vhd"
vcom -explicit -93 "../src/core/ac_in.vhd"
vcom -explicit -93 "../src/tb_ac_in.vhd"
vsim -t 1ps -lib work tb_ac_in
do {tb_ac_in.wdo}
view wave
view structure
view signals
run 700us
lib/ac97_ctrl/sim/tb_ac_in.wdo
+43
View File
@@ -0,0 +1,43 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ac_in/uut/rst
add wave -noupdate -format Logic /tb_ac_in/uut/clk
add wave -noupdate -format Logic /tb_ac_in/uut/sync_frame
add wave -noupdate -format Logic /tb_ac_in/uut/sync_status
add wave -noupdate -divider {AC97 lines}
add wave -noupdate -format Logic /tb_ac_in/uut/ac_reset
add wave -noupdate -format Logic /tb_ac_in/uut/ac_bit_clk
add wave -noupdate -format Logic /tb_ac_in/uut/ac_sdata_in
add wave -noupdate -format Logic /tb_ac_in/uut/ac_ssync
add wave -noupdate -divider Debug
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_data
add wave -noupdate -format Literal /tb_ac_in/uut/pcm_out_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/pcm_out_data
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ac_in/uut/data_array
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/tag
add wave -noupdate -format Literal /tb_ac_in/uut/sac
add wave -noupdate -format Literal /tb_ac_in/uut/bitcnt
add wave -noupdate -format Literal /tb_ac_in/uut/slotcnt
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/rx_reg
add wave -noupdate -format Logic /tb_ac_in/uut/stat_read
add wave -noupdate -format Logic /tb_ac_in/uut/host_update
add wave -noupdate -format Logic /tb_ac_in/uut/slot_end
add wave -noupdate -format Logic /tb_ac_in/uut/sync_end
add wave -noupdate -format Logic /tb_ac_in/uut/last_slot
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {53431686 ps} 0} {{Cursor 2} {44308511 ps} 0} {{Cursor 4} {677821715 ps} 0}
configure wave -namecolwidth 173
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {52190046 ps} {56168939 ps}
lib/ac97_ctrl/sim/tb_ac_io.fdo
+15
View File
@@ -0,0 +1,15 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
##
vlib work
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
vcom -explicit -93 "../src/core/ac_out.vhd"
vcom -explicit -93 "../src/core/ac_in.vhd"
vcom -explicit -93 "../src/core/ac_io.vhd"
vcom -explicit -93 "../src/tb_ac_io.vhd"
vsim -t 1ps -lib work tb_ac_io
do {tb_ac_io.wdo}
view wave
view structure
view signals
run 700us
lib/ac97_ctrl/sim/tb_ac_io.wdo
+51
View File
@@ -0,0 +1,51 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ac_io/uut/rst
add wave -noupdate -format Logic /tb_ac_io/uut/clk
add wave -noupdate -format Logic /tb_ac_io/uut/ready
add wave -noupdate -format Literal /tb_ac_io/uut/slot_valid
add wave -noupdate -format Logic /tb_ac_io/uut/sync_strobe
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_data
add wave -noupdate -format Literal /tb_ac_io/uut/rx_pcm_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/rx_pcm_data
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_data
add wave -noupdate -format Logic /tb_ac_io/uut/cmd_we
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_data
add wave -noupdate -format Logic /tb_ac_io/uut/tx_pcm_we
add wave -noupdate -divider {AC97 lines}
add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_in
add wave -noupdate -format Logic /tb_ac_io/uut/ac_bit_clk
add wave -noupdate -format Logic /tb_ac_io/uut/ac_reset_n
add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_out
add wave -noupdate -format Logic /tb_ac_io/uut/ac_ssync
add wave -noupdate -divider Debug
add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_in/stat_read
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/rx_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_out/tx_reg
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/bitcnt
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/sac
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/tag
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/data_array
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/bitcnt
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slotcnt
add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_out/ssync
add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slot_valid
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {0 ps} 0} {{Cursor 2} {292930000 ps} 0} {{Cursor 4} {4999959266 ps} 0}
configure wave -namecolwidth 173
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {735 us}
lib/ac97_ctrl/sim/tb_ac_out.fdo
+13
View File
@@ -0,0 +1,13 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
##
vlib work
vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd"
vcom -explicit -93 "../src/core/ac_out.vhd"
vcom -explicit -93 "../src/tb_ac_out.vhd"
vsim -t 1ps -lib work tb_ac_out
do {tb_ac_out.wdo}
view wave
view structure
view signals
run 600us
lib/ac97_ctrl/sim/tb_ac_out.wdo
+41
View File
@@ -0,0 +1,41 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_ac_out/rst
add wave -noupdate -format Logic /tb_ac_out/clk
add wave -noupdate -format Logic /tb_ac_out/ce
add wave -noupdate -divider {Host hand shake}
add wave -noupdate -format Logic /tb_ac_out/sync_tx
add wave -noupdate -divider {Command I/F}
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_data
add wave -noupdate -format Logic /tb_ac_out/uut/cmd_we
add wave -noupdate -divider {PCM I/F}
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_data
add wave -noupdate -format Logic /tb_ac_out/pcm_in_we
add wave -noupdate -divider {AC97 I/F}
add wave -noupdate -format Logic /tb_ac_out/ac_bit_clk
add wave -noupdate -format Logic /tb_ac_out/ac_reset
add wave -noupdate -format Logic /tb_ac_out/ac_sdata_out
add wave -noupdate -format Logic /tb_ac_out/ac_ssync
add wave -noupdate -divider Debug
add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/uut/tx_reg
add wave -noupdate -format Literal /tb_ac_out/uut/sac
add wave -noupdate -format Literal /tb_ac_out/uut/bitcnt
add wave -noupdate -format Literal /tb_ac_out/uut/slotcnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {544839100 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {532851785 ps} {556826415 ps}
lib/ac97_ctrl/src/core/ac97_wb.vhd
+351
View File
@@ -0,0 +1,351 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ac97_wb IS
Generic
(
fifo_depth : natural := 4
);
Port
(
-- J-Bus domain
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_O : out STD_LOGIC;
-- AC97 domain
ac97_sdata_in : in std_logic;
ac97_bit_clk : in std_logic;
ac97_reset_n : out std_logic;
ac97_sdata_out : out std_logic;
ac97_ssync : out std_logic
);
END ac97_wb;
ARCHITECTURE behavior OF ac97_wb IS
constant ac_data_width : natural := 20;
constant pcm_data_width : natural := 18;
constant stat_data_width : natural := 16;
signal cmd_reg_we : std_logic;
signal cmd_pending : std_logic;
signal ac_cmd_data : unsigned(ac_data_width-1 downto 0);
signal ac_cmd_addr : unsigned(ac_data_width-1 downto 0);
signal ac_cmd_we : std_logic;
signal ac_tx_pcm_we : std_logic;
signal stat_reg : unsigned(stat_data_width-1 downto 0);
signal stat_reg_re : std_logic;
signal stat_valid : std_logic;
signal stat_pending : std_logic;
signal ac_stat_data : unsigned(ac_data_width-1 downto 0);
signal ac_stat_addr : unsigned(ac_data_width-1 downto 0);
signal ac_stat_read : std_logic;
signal ac_stat_valid : std_logic;
signal ac_tx_pcm_data : unsigned(ac_data_width-1 downto 0);
signal ac_tx_pcm_addr : unsigned (3 downto 0);
signal ac_rx_pcm_data : unsigned(ac_data_width-1 downto 0);
signal ac_rx_pcm_addr : unsigned (3 downto 0);
signal ac_sync_strobe : unsigned(0 to 2);
signal ac_slot_valid : unsigned(0 to 12);
signal ac_ready : std_logic;
signal rx_frame_valid : std_logic;
signal sync_frame : std_logic;
signal sync_tx : std_logic;
signal sync_status : std_logic;
signal request : unsigned(3 to 12);
signal tx_data_start : std_logic;
signal tx_fifo_din : unsigned(pcm_data_width-1 downto 0);
signal tx_fifo_dout : unsigned(pcm_data_width-1 downto 0);
signal tx_fifo_re : std_logic;
signal tx_fifo_we : std_logic;
signal tx_fifo_full : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal rx_data_start : std_logic;
signal rx_fifo_din : unsigned(pcm_data_width-1 downto 0);
signal rx_fifo_dout : unsigned(pcm_data_width-1 downto 0);
signal rx_fifo_re : std_logic;
signal rx_fifo_we : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal ac97_stat : unsigned(31 downto 0);
signal addr_reg : unsigned(31 downto 0);
signal data_reg : unsigned(31 downto 0);
signal int_en_frame_sync : std_logic;
signal int_en_rx : std_logic;
signal int_en_tx : std_logic;
function GetRequest(slot1 : unsigned) return unsigned is
variable res : unsigned(3 to 12);
begin
res := (others => '0');
for i in res'range loop
res(i) := not slot1(14-i);
end loop;
return res;
end GetRequest;
begin
SRDY_O <= CYC_I;
INT_O <= (rx_fifo_almost_full and int_en_rx) or (tx_fifo_almost_empty and int_en_tx) or (sync_frame and int_en_frame_sync) ;
rx_frame_valid <= ac_slot_valid(0);
sync_frame <= ac_sync_strobe(0);
sync_status <= ac_sync_strobe(1);
sync_tx <= ac_sync_strobe(2);
request <= GetRequest(ac_stat_addr);
ac_stat_read <= not addr_reg(9);
ac_stat_valid <= '1' when (sync_status = '1' and ac_slot_valid(0 to 2) = "111") else '0';
ac97_stat <= ac_ready & "000" & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & not rx_fifo_almost_empty & tx_fifo_almost_full & stat_valid & cmd_pending;
command_logic:
process (CLK_I)
begin
if rising_edge(CLK_I) then
ac_cmd_we <= '0';
if RST_I = '1' then
cmd_pending <= '0';
elsif cmd_reg_we = '1' and cmd_pending = '0' then
cmd_pending <= '1';
elsif (rx_frame_valid and sync_tx) = '1' and cmd_pending = '1' then
ac_cmd_we <= '1';
cmd_pending <= '0';
end if;
end if;
end process;
status_logic:
process (CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
stat_pending <= '0';
elsif cmd_reg_we = '1' and cmd_pending = '0' then
stat_pending <= ac_stat_read;
elsif ac_stat_valid = '1' then
stat_pending <= '0';
end if;
end if;
end process;
command_register:
process (CLK_I)
begin
if rising_edge(CLK_I) then
if cmd_reg_we = '1' and cmd_pending = '0' then
ac_cmd_addr <= ac_stat_read & addr_reg(8 downto 2) & X"000";
ac_cmd_data <= data_reg(stat_data_width-1 downto 0) & X"0";
end if;
end if;
end process;
status_register:
process (CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
stat_valid <= '0';
elsif stat_pending = '1' and ac_stat_valid = '1' then
stat_reg <= ac_stat_data(ac_data_width-1 downto ac_data_width-stat_data_width);
stat_valid <= '1';
elsif stat_reg_re = '1' then
stat_valid <= '0';
end if;
end if;
end process;
-- Instantiate synchronous FIFO
inst_tx_fifo: entity work.fifo_sync_dist
GENERIC MAP
(
addr_width => fifo_depth,
data_width => pcm_data_width,
almost_full_thresh => 12,
almost_empty_thresh => 4
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => tx_fifo_we,
re => tx_fifo_re,
fifo_full => tx_fifo_full,
fifo_empty => tx_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => tx_fifo_din,
data_r => tx_fifo_dout
);
tx_logic:
process (CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ac_tx_pcm_addr <= "0011";
tx_data_start <= '0';
elsif sync_tx = '1' and (request(3) and request(4)) = '1' then
ac_tx_pcm_addr <= "0011";
tx_data_start <= '1';
elsif ac_tx_pcm_addr /= "0100" then
ac_tx_pcm_addr <= ac_tx_pcm_addr + 1;
else
tx_data_start <= '0';
end if;
end if;
end process;
ac_tx_pcm_we <= not tx_fifo_empty and tx_data_start;
tx_fifo_re <= ac_tx_pcm_we;
tx_fifo_din <= data_reg(pcm_data_width-1 downto 0);
-- Instantiate synchronous FIFO
inst_rx_fifo: entity work.fifo_sync_dist
GENERIC MAP
(
addr_width => fifo_depth,
data_width => pcm_data_width,
almost_full_thresh => 12,
almost_empty_thresh => 4
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => rx_fifo_we,
re => rx_fifo_re,
fifo_full => rx_fifo_full,
fifo_empty => rx_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => rx_fifo_din,
data_r => rx_fifo_dout
);
rx_fifo_din <= ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width);
rx_logic:
process (CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ac_rx_pcm_addr <= "0011";
rx_data_start <= '0';
elsif (rx_frame_valid and sync_frame) = '1' and (ac_slot_valid(3) and ac_slot_valid(4)) = '1' then
ac_rx_pcm_addr <= "0011";
rx_data_start <= '1';
elsif ac_rx_pcm_addr /= "0100" then
ac_rx_pcm_addr <= ac_rx_pcm_addr + 1;
else
rx_data_start <= '0';
end if;
end if;
end process;
rx_fifo_we <= rx_data_start;
inst_ac_io : entity work.ac_io
PORT MAP
(
rst => RST_I,
clk => CLK_I,
ready => ac_ready,
sync_strobe => ac_sync_strobe,
slot_valid => ac_slot_valid,
stat_addr => ac_stat_addr,
stat_data => ac_stat_data,
rx_pcm_addr => ac_rx_pcm_addr,
rx_pcm_data => ac_rx_pcm_data,
cmd_addr => ac_cmd_addr,
cmd_data => ac_cmd_data,
cmd_we => ac_cmd_we,
tx_pcm_addr => ac_tx_pcm_addr,
tx_pcm_data => ac_tx_pcm_data,
tx_pcm_we => ac_tx_pcm_we,
ac_sdata_in => ac97_sdata_in,
ac_bit_clk => ac97_bit_clk,
ac_reset_n => ac97_reset_n,
ac_sdata_out => ac97_sdata_out,
ac_ssync => ac97_ssync
);
ac_tx_pcm_data <= tx_fifo_dout & (ac_data_width-pcm_data_width-1 downto 0 => '0');
slave_data_out:
process (CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
int_en_frame_sync <= '0';
int_en_rx <= '0';
int_en_tx <= '0';
else
DAT_O <= (others => '-');
rx_fifo_re <= '0';
tx_fifo_we <= '0';
stat_reg_re <= '0';
cmd_reg_we <= '0';
ACK_O <= '0';
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
case ADDR_I(11 downto 10) is
when "00" =>
DAT_O <= ac97_stat;
if WE_I = '1' then
int_en_frame_sync <= DAT_I(0);
int_en_tx <= DAT_I(1);
int_en_rx <= DAT_I(2);
end if;
when "01" =>
addr_reg <= ADDR_I;
data_reg <= DAT_I;
stat_reg_re <= not WE_I;
cmd_reg_we <= WE_I;
DAT_O <= (31 downto stat_data_width => '0') & stat_reg;
when "10" =>
addr_reg <= ADDR_I;
data_reg <= DAT_I;
rx_fifo_re <= not WE_I;
tx_fifo_we <= WE_I;
DAT_O <= (31 downto pcm_data_width => '0') & rx_fifo_dout;
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavior;
lib/ac97_ctrl/src/core/ac_in.vhd
+309
View File
@@ -0,0 +1,309 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:27:43 08/26/2006
-- Design Name:
-- Module Name: ac_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ac_in is
Port (
rst : in std_logic;
clk : in std_logic;
sync_frame : out std_logic;
sync_status : out std_logic;
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
pcm_out_addr : in unsigned (3 downto 0);
pcm_out_data : out unsigned (19 downto 0);
ac_reset : in std_logic;
ac_bit_clk : in std_logic;
ac_sdata_in : in std_logic;
ac_ssync : in std_logic
);
end ac_in;
architecture Behavioral of ac_in is
------------------------------------------------------------------
COMPONENT singleshot
GENERIC (mode : integer);
PORT(
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
------------------------------------------------------------------
type sac_t is (ac_idle, ac_tag, ac_data);
subtype bitcnt_t is integer range 0 to 19;
subtype slotcnt_t is integer range 0 to 12;
subtype slot_valid_t is UNSIGNED(0 to 12);
subtype tag_t is UNSIGNED(15 downto 0);
subtype slot_t is UNSIGNED(19 downto 0);
type slot_array_t is array (natural range <>) of slot_t;
signal data_array : slot_array_t (1 to 12);
signal tag : tag_t;
signal sac, snac : sac_t;
signal bitcnt : bitcnt_t;
signal bitcnt_rst, bitcnt_en : STD_LOGIC;
signal slotcnt : slotcnt_t;
signal slotcnt_rst, slotcnt_en : STD_LOGIC;
signal rx_reg : slot_t;
signal stat_read, host_update : STD_LOGIC;
signal sync_end, slot_end, last_slot, start_of_frame : STD_LOGIC;
------------------------------------------------------------------
function GetSlotValid(data : tag_t) return slot_valid_t is
variable res : slot_valid_t := (others => '0');
begin
res := (others => '0');
for i in slot_valid_t'range loop
res(i) := data(data'left-i);
end loop;
return res;
end GetSlotValid;
------------------------------------------------------------------
begin
-------------------------------------------------------------
-- proc_status_flags
-------------------------------------------------------------
proc_status_flags:
process (rst, clk, host_update, tag, data_array)
begin
if rising_edge(clk) then
sync_status <= '0';
if rst = '1' then
slot_valid <= (others => '0');
stat_addr <= (others => '0');
stat_data <= (others => '0');
elsif host_update = '1' then
sync_status <= '1';
slot_valid <= GetSlotValid(tag);
stat_addr <= data_array(1);
stat_data <= data_array(2);
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_pcm_data
-------------------------------------------------------------
proc_pcm_data:
process (clk, pcm_out_addr, data_array)
variable slot_id : integer range 0 to 12;
begin
pcm_out_data <= (others => '-');
slot_id := to_integer(pcm_out_addr);
if (slot_id > 2) then
pcm_out_data <= data_array(slot_id);
end if;
end process;
-------------------------------------------------------------
-- proc_read_data
-------------------------------------------------------------
proc_read_data :
process (ac_reset, ac_bit_clk, slot_end, slotcnt)
begin
if ac_reset = '1' then
stat_read <= '0';
elsif rising_edge(ac_bit_clk) then
stat_read <= '0';
if slot_end = '1' and slotcnt /= 0 then
data_array(slotcnt) <= rx_reg;
if slotcnt = 2 then
stat_read <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_read_stat
-------------------------------------------------------------
proc_read_tag :
process (ac_reset, ac_bit_clk, sync_end)
begin
if ac_reset = '1' then
tag <= (others => '0');
elsif rising_edge(ac_bit_clk) then
if sync_end = '1' then
tag <= rx_reg(15 downto 0);
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_slot_count
-------------------------------------------------------------
proc_slot_count:
process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
begin
if rising_edge(ac_bit_clk) then
if slotcnt_rst = '1' then
slotcnt <= slotcnt_t'low;
elsif slotcnt_en = '1' then
if slotcnt /= slotcnt_t'high then
slotcnt <= slotcnt + 1;
else
slotcnt <= slotcnt_t'low;
end if;
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_bit_count
-------------------------------------------------------------
proc_bit_count:
process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
begin
if rising_edge(ac_bit_clk) then
if bitcnt_rst = '1' then
bitcnt <= bitcnt_t'low;
elsif bitcnt_en = '1' then
if bitcnt /= bitcnt_t'high then
bitcnt <= bitcnt + 1;
else
bitcnt <= bitcnt_t'low;
end if;
end if;
end if;
end process;
------------------------------------------------------------------
proc_ac_fsm:
process (bitcnt, slotcnt, sac, ac_ssync)
begin
snac <= sac;
bitcnt_rst <= '0';
bitcnt_en <= '1';
slotcnt_rst <= '0';
slotcnt_en <= '0';
slot_end <= '0';
sync_end <= '0';
last_slot <= '0';
start_of_frame <= '0';
if bitcnt = 19 then
slot_end <= '1';
end if;
if slotcnt = 12 and bitcnt = 19 then
last_slot <= '1';
end if;
case sac is
when ac_idle =>
bitcnt_rst <= '1';
slotcnt_rst <= '1';
if (ac_ssync = '1') then
snac <= ac_tag;
end if;
when ac_tag =>
if (bitcnt = 0) then
start_of_frame <= '1';
elsif (bitcnt = 15) then
slotcnt_en <= '1';
bitcnt_rst <= '1';
sync_end <= '1';
if (ac_ssync = '0') then
snac <= ac_data;
else
snac <= ac_idle;
end if;
end if;
when ac_data =>
if bitcnt = 19 then
slotcnt_en <= '1';
if slotcnt = 12 then
slotcnt_rst <= '1';
snac <= ac_tag;
end if;
end if;
when others => null;
end case;
end process;
proc_ac_fsm_next:
process (ac_reset, ac_bit_clk, snac)
begin
if ac_reset = '1' then
sac <= ac_idle;
elsif rising_edge(ac_bit_clk) then
sac <= snac;
end if;
end process;
-------------------------------------------------------------
-- Receive Shift Register
-------------------------------------------------------------
process (ac_reset, ac_bit_clk, ac_sdata_in)
begin
if ac_reset = '1' then
rx_reg <= (others => '0');
elsif falling_edge(ac_bit_clk) then
rx_reg <= rx_reg(rx_reg'left-1 downto 0) & ac_sdata_in;
end if;
end process;
------------------------------------------------------------------
singleshot_inst1: singleshot
GENERIC MAP (
mode => 0)
PORT MAP(
rst => rst,
clk => clk,
input => stat_read,
output => host_update
);
singleshot_inst2: singleshot
GENERIC MAP (
mode => 1)
PORT MAP(
rst => rst,
clk => clk,
input => start_of_frame,
output => sync_frame
);
-------------------------------------------------------------
end Behavioral;
lib/ac97_ctrl/src/core/ac_io.vhd
+189
View File
@@ -0,0 +1,189 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:29:55 08/26/2006
-- Design Name:
-- Module Name: ac_io - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ac_io is
Port
(
rst : in std_logic;
clk : in std_logic;
ready : out std_logic;
sync_strobe : out unsigned(0 to 2);
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
rx_pcm_addr : in unsigned (3 downto 0);
rx_pcm_data : out unsigned (19 downto 0);
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
tx_pcm_addr : in unsigned(3 downto 0);
tx_pcm_data : in unsigned(19 downto 0);
tx_pcm_we : in std_logic;
ac_sdata_in : in std_logic;
ac_bit_clk : in std_logic;
ac_reset_n : out std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
end ac_io;
architecture Behavioral of ac_io is
COMPONENT ac_in
Port
(
rst : in std_logic;
clk : in std_logic;
sync_frame : out std_logic;
sync_status : out std_logic;
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
pcm_out_addr : in unsigned (3 downto 0);
pcm_out_data : out unsigned (19 downto 0);
ac_reset : in std_logic;
ac_bit_clk : in std_logic;
ac_sdata_in : in std_logic;
ac_ssync : in std_logic
);
END COMPONENT;
COMPONENT ac_out
PORT
(
rst : in std_logic;
clk : in std_logic;
sync_tx : out std_logic;
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
pcm_in_addr : in unsigned(3 downto 0);
pcm_in_data : in unsigned(19 downto 0);
pcm_in_we : in std_logic;
ac_bit_clk : in std_logic;
ac_reset : in std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
END COMPONENT;
SIGNAL ac_reset : std_logic;
SIGNAL ssync_rx : std_logic;
SIGNAL ssync_tx : std_logic;
SIGNAL sync_frame : std_logic;
SIGNAL sync_status : std_logic;
SIGNAL sync_tx : std_logic;
begin
inst_ac_in: ac_in
PORT MAP
(
rst => rst,
clk => clk,
sync_frame => sync_frame,
sync_status => sync_status,
slot_valid => slot_valid,
stat_addr => stat_addr,
stat_data => stat_data,
pcm_out_addr => rx_pcm_addr,
pcm_out_data => rx_pcm_data,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_in => ac_sdata_in,
ac_ssync => ssync_rx
);
inst_ac_out: ac_out
PORT MAP
(
rst => rst,
clk => clk,
sync_tx => sync_tx,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cmd_we,
pcm_in_addr => tx_pcm_addr,
pcm_in_data => tx_pcm_data,
pcm_in_we => tx_pcm_we,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_out => ac_sdata_out,
ac_ssync => ssync_tx
);
------------------------------------------------------------------
ready <= not ac_reset;
ac_ssync <= ssync_tx;
ssync_rx <= ssync_tx;
sync_strobe <= sync_frame & sync_status & sync_tx;
------------------------------------------------------------------
proc_reset_gen:
process (rst, clk, ac_bit_clk)
type rstate_t is (s0, s1);
variable rstate, rstaten : rstate_t;
subtype cnt_t is integer range 0 to 999;
variable cnt : cnt_t;
begin
if rising_edge(clk) then
if rst = '1' then
rstate := s0;
cnt := cnt_t'high;
ac_reset <= '1';
ac_reset_n <= '0';
else
rstaten := rstate;
case rstate is
when s0 =>
if cnt /= 0 then
cnt := cnt - 1;
else
ac_reset_n <= '1';
if ac_bit_clk = '1' then
rstaten := s1;
cnt := cnt_t'high;
end if;
end if;
when s1 =>
if cnt /= 0 then
cnt := cnt - 1;
else
ac_reset <= '0';
end if;
end case;
rstate := rstaten;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
lib/ac97_ctrl/src/core/ac_out.vhd
+276
View File
@@ -0,0 +1,276 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:12 06/05/2007
-- Design Name:
-- Module Name: ac_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ac_out is
Port (
rst : in std_logic;
clk : in std_logic;
sync_tx : out std_logic;
cmd_addr : in unsigned (19 downto 0);
cmd_data : in unsigned (19 downto 0);
cmd_we : in std_logic;
pcm_in_addr : in unsigned (3 downto 0);
pcm_in_data : in unsigned (19 downto 0);
pcm_in_we : in std_logic;
ac_reset : in std_logic;
ac_bit_clk : in std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
end ac_out;
architecture Behavioral of ac_out is
------------------------------------------------------------------
COMPONENT singleshot
GENERIC (mode : integer);
PORT(
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
------------------------------------------------------------------
subtype tag_t is UNSIGNED(15 downto 0);
subtype slot_valid_t is UNSIGNED(1 to 12);
signal slot_valid : slot_valid_t;
subtype slot_t is UNSIGNED(19 downto 0);
type slot_array_t is array (natural range <>) of slot_t;
signal data_array : slot_array_t (1 to 12);
signal tx_reg : UNSIGNED(19 downto 0);
signal last_slot, ssync : STD_LOGIC;
type sac_t is (ac_idle, ac_tag, ac_data);
signal sac, snac : sac_t;
subtype bitcnt_t is integer range 0 to 19;
subtype slotcnt_t is integer range 0 to 12;
signal bitcnt : bitcnt_t;
signal bitcnt_rst, bitcnt_en : STD_LOGIC;
signal slotcnt : slotcnt_t;
signal slotcnt_rst, slotcnt_en : STD_LOGIC;
signal slot_start : STD_LOGIC;
------------------------------------------------------------------
function CreateTag(slot_valid : slot_valid_t) return tag_t is
variable tag : tag_t := (others => '0');
begin
tag := (others => '0');
for i in slot_valid_t'range loop
tag(15-i) := slot_valid(i);
if slot_valid(i) = '1' then
tag(15) := '1';
end if;
end loop;
tag(0) := '0'; -- ID0
tag(1) := '0'; -- ID1
tag(2) := '0'; -- Reserved
-- tag(15) := '1'; -- Frame is valid
return tag;
end CreateTag;
begin
------------------------------------------------------------------
proc_slot_reg:
process (clk, cmd_addr, cmd_data, cmd_we, pcm_in_data, pcm_in_we, pcm_in_addr, last_slot)
variable slot_id : integer range 0 to 12;
begin
slot_id := to_integer(pcm_in_addr);
if rising_edge(clk) then
if rst = '1' then
for i in data_array'range(1) loop
data_array(i) <= (others => '0');
end loop;
slot_valid <= (others => '0');
elsif last_slot = '1' then
slot_valid <= (others => '0');
else
if cmd_we = '1' then
slot_valid(1) <= '1';
slot_valid(2) <= '1';
data_array(1) <= cmd_addr;
data_array(2) <= cmd_data;
end if;
if pcm_in_we = '1' then
if (slot_id > 2) then
data_array(slot_id) <= pcm_in_data;
slot_valid(slot_id) <= '1';
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------
-- proc_slot_count
-------------------------------------------------------------
proc_slot_count:
process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
begin
if rising_edge(ac_bit_clk) then
if slotcnt_rst = '1' then
slotcnt <= slotcnt_t'low;
elsif slotcnt_en = '1' then
if slotcnt /= slotcnt_t'high then
slotcnt <= slotcnt + 1;
else
slotcnt <= slotcnt_t'low;
end if;
end if;
end if;
end process;
------------------------------------------------------------------
-- proc_bit_count
------------------------------------------------------------------
proc_bit_count:
process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
begin
if rising_edge(ac_bit_clk) then
if bitcnt_rst = '1' then
bitcnt <= bitcnt_t'low;
elsif bitcnt_en = '1' then
if bitcnt /= bitcnt_t'high then
bitcnt <= bitcnt + 1;
else
bitcnt <= bitcnt_t'low;
end if;
end if;
end if;
end process;
------------------------------------------------------------------
proc_ac_fsm:
process (bitcnt, slotcnt, sac)
begin
snac <= sac;
bitcnt_rst <= '0';
bitcnt_en <= '1';
slotcnt_rst <= '0';
slotcnt_en <= '0';
slot_start <= '0';
ssync <= '0';
if bitcnt = 0 then
slot_start <= '1';
end if;
case sac is
when ac_idle =>
bitcnt_rst <= '1';
slotcnt_rst <= '1';
snac <= ac_tag;
when ac_tag =>
ssync <= '1';
if (bitcnt = 15) then
slotcnt_en <= '1';
bitcnt_rst <= '1';
snac <= ac_data;
end if;
when ac_data =>
if bitcnt = 19 then
slotcnt_en <= '1';
if slotcnt = 12 then
slotcnt_rst <= '1';
snac <= ac_tag;
end if;
end if;
when others => null;
end case;
end process;
proc_ac_fsm_next:
process (ac_reset, ac_bit_clk, snac)
begin
if ac_reset = '1' then
sac <= ac_idle;
elsif rising_edge(ac_bit_clk) then
sac <= snac;
end if;
end process;
------------------------------------------------------------------
proc_tx_shift_reg:
process (ac_reset, ac_bit_clk, tx_reg, ssync, slot_valid, data_array)
begin
if ac_reset = '1' then
tx_reg <= (others => '0');
elsif rising_edge(ac_bit_clk) then
last_slot <= '0';
if slot_start = '1' then
if ssync = '1' then
tx_reg <= CreateTag(slot_valid) & "0000";
else
if slotcnt /= 0 then
tx_reg <= data_array(slotcnt);
if slotcnt = 12 then
last_slot <= '1';
end if;
end if;
end if;
else
tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '0';
end if;
end if;
end process;
------------------------------------------------------------------
proc_ac_sync_out:
process (ac_reset, ac_bit_clk, ssync, tx_reg)
begin
if ac_reset = '1' then
ac_ssync <= '0';
ac_sdata_out <= '0';
elsif rising_edge(ac_bit_clk) then
ac_ssync <= ssync;
ac_sdata_out <= tx_reg(tx_reg'left);
end if;
end process;
------------------------------------------------------------------
singleshot_inst1: singleshot
GENERIC MAP (
mode => 0)
PORT MAP(
rst => rst,
clk => clk,
input => last_slot,
output => sync_tx
);
end Behavioral;
lib/ac97_ctrl/src/tb_ac97_wb.vhd
+152
View File
@@ -0,0 +1,152 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:47 06/05/2007
-- Design Name: eval_ac
-- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name: ac_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_ac97_wb IS
END tb_ac97_wb;
ARCHITECTURE behavior OF tb_ac97_wb IS
constant SYS_CLK_PERIOD : time := 10 ns;
CONSTANT BIT_CLK_PERIOD : time := 100 ns;
-- constant BIT_CLK_PERIOD : time := 81.38 ns;
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal WE_O : std_logic := '0';
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal INT_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0);
signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
SIGNAL ac97_bit_clk : std_logic := '0';
SIGNAL ac97_reset_n : std_logic;
SIGNAL ac97_sdata_out : std_logic;
SIGNAL ac97_ssync : std_logic;
SIGNAL ac97_sdata_in : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : entity work.ac97_wb
GENERIC MAP
(
fifo_depth => 4
)
PORT MAP
(
-- J-Bus domain
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_O,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I,
INT_O => INT_I,
-- AC97 domain
ac97_sdata_in => ac97_sdata_in,
ac97_bit_clk => ac97_bit_clk,
ac97_reset_n => ac97_reset_n,
ac97_sdata_out => ac97_sdata_out,
ac97_ssync => ac97_ssync
);
ac97_sdata_in <= ac97_sdata_out;
CLK_GEN: process
begin
wait for SYS_CLK_PERIOD/2;
CLK_O <= not CLK_O;
end process;
bit_clk_gen : PROCESS
begin
if (ac97_reset_n = '0') then
ac97_bit_clk <= '0';
wait until ac97_reset_n = '1';
wait for 150 us;
end if;
wait for BIT_CLK_PERIOD/2;
ac97_bit_clk <= not ac97_bit_clk;
END PROCESS;
STIMULUS: process
begin
wait for 3*SYS_CLK_PERIOD;
RST_O <= '0';
wait for 200 us;
wait until rising_edge(CLK_O);
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
DAT_O <= X"0000_0000";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O);
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
CYC_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"5555_1000";
ADDR_O <= X"0000_0800";
wait until rising_edge(CLK_O);
DAT_O <= X"5555_1001";
wait until rising_edge(CLK_O);
STB_O <= '0';
CYC_O <= '0';
WAIT;
END PROCESS;
END;
lib/ac97_ctrl/src/tb_ac_in.vhd
+203
View File
@@ -0,0 +1,203 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:47 06/05/2007
-- Design Name: eval_ac
-- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name: ac_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_ac_in IS
END tb_ac_in;
ARCHITECTURE behavior OF tb_ac_in IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ac_in
Port (
rst : in std_logic;
clk : in std_logic;
sync_frame : out std_logic;
sync_status : out std_logic;
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
pcm_out_addr : in unsigned (3 downto 0);
pcm_out_data : out unsigned (19 downto 0);
ac_reset : in std_logic;
ac_bit_clk : in std_logic;
ac_sdata_in : in std_logic;
ac_ssync : in std_logic
);
END COMPONENT;
COMPONENT ac_out
PORT(
rst : in std_logic;
clk : in std_logic;
sync_tx : out std_logic;
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
pcm_in_addr : in unsigned(3 downto 0);
pcm_in_data : in unsigned(19 downto 0);
pcm_in_we : in std_logic;
ac_bit_clk : in std_logic;
ac_reset : in std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
END COMPONENT;
constant SYS_CLK_PERIOD : time := 10 ns;
constant BIT_CLK_PERIOD : time := 81.38 ns;
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '0';
SIGNAL cmd_we : std_logic := '0';
SIGNAL pcm_in_we : std_logic := '0';
SIGNAL ac_bit_clk : std_logic := '0';
SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL pcm_in_addr : unsigned(3 downto 0) := "0011";
SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL ac_sdata_in : std_logic;
SIGNAL pcm_out_addr : unsigned(3 downto 0) := "0101";
SIGNAL ac_reset : std_logic := '1';
--Outputs
SIGNAL sync_frame : std_logic;
SIGNAL sync_status : std_logic;
SIGNAL sync_tx : std_logic;
SIGNAL ac_sdata_out : std_logic;
SIGNAL ac_ssync : std_logic;
SIGNAL stat_addr : unsigned(19 downto 0);
SIGNAL stat_data : unsigned(19 downto 0);
SIGNAL stat_valid : std_logic;
SIGNAL pcm_out_data : unsigned(19 downto 0);
SIGNAL pcm_out_valid : std_logic;
SIGNAL pcm_out_avail : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ac_in PORT MAP(
rst => rst,
clk => clk,
sync_frame => sync_frame,
sync_status => sync_status,
stat_addr => stat_addr,
stat_data => stat_data,
pcm_out_addr => pcm_out_addr,
pcm_out_data => pcm_out_data,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_in => ac_sdata_in,
ac_ssync => ac_ssync
);
inst_ac_out: ac_out PORT MAP(
rst => rst,
clk => clk,
sync_tx => sync_tx,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cmd_we,
pcm_in_addr => pcm_in_addr,
pcm_in_data => pcm_in_data,
pcm_in_we => pcm_in_we,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_out => ac_sdata_out,
ac_ssync => ac_ssync
);
ac_sdata_in <= ac_sdata_out;
sys_clk_gen :
PROCESS
BEGIN
wait for SYS_CLK_PERIOD;
clk <= not clk;
END PROCESS;
bit_clk_gen :
PROCESS
BEGIN
wait for BIT_CLK_PERIOD;
ac_bit_clk <= not ac_bit_clk;
END PROCESS;
tb_out : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100*SYS_CLK_PERIOD;
rst <= '0';
wait for 100*SYS_CLK_PERIOD;
ac_reset <= '0';
wait until rising_edge(clk) and sync_tx = '1';
wait for 100*SYS_CLK_PERIOD;
cmd_data <= X"12340";
cmd_addr <= X"8B930";
wait until rising_edge(clk);
cmd_we <= '1';
wait until rising_edge(clk);
cmd_we <= '0';
for k in 1 to 10 loop
pcm_in_we <= '0';
wait until rising_edge(clk) and sync_tx = '1';
wait for 100*SYS_CLK_PERIOD;
for i in 3 to 12 loop
pcm_in_addr <= to_unsigned(i, 4);
pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
pcm_in_we <= '1';
wait until rising_edge(clk);
end loop;
end loop;
pcm_in_we <= '0';
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
tb_in : PROCESS(clk, pcm_out_addr, sync_status)
BEGIN
if rising_edge(clk) then
if sync_status = '1' then
pcm_out_addr <= "0011";
elsif pcm_out_addr /= "1100" then
pcm_out_addr <= pcm_out_addr + 1;
end if;
end if;
END PROCESS;
END;
lib/ac97_ctrl/src/tb_ac_io.vhd
+186
View File
@@ -0,0 +1,186 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:47 06/05/2007
-- Design Name: eval_ac
-- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name: ac_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_ac_io IS
END tb_ac_io;
ARCHITECTURE behavior OF tb_ac_io IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ac_io
Port (
rst : in std_logic;
clk : in std_logic;
ready : out std_logic;
sync_strobe : out unsigned(0 to 2);
slot_valid : out unsigned(0 to 12);
stat_addr : out unsigned (19 downto 0);
stat_data : out unsigned (19 downto 0);
rx_pcm_addr : in unsigned (3 downto 0);
rx_pcm_data : out unsigned (19 downto 0);
cmd_addr : in unsigned(19 downto 0);
cmd_data : in unsigned(19 downto 0);
cmd_we : in std_logic;
tx_pcm_addr : in unsigned(3 downto 0);
tx_pcm_data : in unsigned(19 downto 0);
tx_pcm_we : in std_logic;
ac_sdata_in : in std_logic;
ac_bit_clk : in std_logic;
ac_reset_n : out std_logic;
ac_sdata_out : out std_logic;
ac_ssync : out std_logic
);
END COMPONENT;
constant SYS_CLK_PERIOD : time := 10 ns;
CONSTANT BIT_CLK_PERIOD : time := 100 ns;
-- constant BIT_CLK_PERIOD : time := 81.38 ns;
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '0';
SIGNAL acio_ready : std_logic;
SIGNAL cmd_we : std_logic := '0';
SIGNAL tx_pcm_we : std_logic := '0';
SIGNAL ac_bit_clk : std_logic := '0';
SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL tx_pcm_addr : unsigned(3 downto 0) := "0011";
SIGNAL tx_pcm_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL ac_sdata_in : std_logic;
SIGNAL rx_pcm_addr : unsigned(3 downto 0) := "0101";
--Outputs
SIGNAL slot_valid : unsigned(0 to 12);
SIGNAL sync_strobe : unsigned(0 to 2);
SIGNAL ac_reset_n : std_logic;
SIGNAL ac_sdata_out : std_logic;
SIGNAL ac_ssync : std_logic;
SIGNAL stat_addr : unsigned(19 downto 0);
SIGNAL stat_data : unsigned(19 downto 0);
SIGNAL rx_pcm_data : unsigned(19 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ac_io PORT MAP(
rst => rst,
clk => clk,
ready => acio_ready,
sync_strobe => sync_strobe,
slot_valid => slot_valid,
stat_addr => stat_addr,
stat_data => stat_data,
rx_pcm_addr => rx_pcm_addr,
rx_pcm_data => rx_pcm_data,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cmd_we,
tx_pcm_addr => tx_pcm_addr,
tx_pcm_data => tx_pcm_data,
tx_pcm_we => tx_pcm_we,
ac_sdata_in => ac_sdata_in,
ac_bit_clk => ac_bit_clk,
ac_reset_n => ac_reset_n,
ac_sdata_out => ac_sdata_out,
ac_ssync => ac_ssync
);
ac_sdata_in <= ac_sdata_out;
sys_clk_gen :
PROCESS
BEGIN
wait for SYS_CLK_PERIOD;
clk <= not clk;
END PROCESS;
bit_clk_gen : PROCESS
begin
if (ac_reset_n = '0') then
ac_bit_clk <= '0';
wait until ac_reset_n = '1';
wait for 150 us;
end if;
wait for BIT_CLK_PERIOD/2;
ac_bit_clk <= not ac_bit_clk;
END PROCESS;
tb_out : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100*SYS_CLK_PERIOD;
rst <= '0';
wait until (ac_reset_n = '1');
wait until rising_edge(clk) and sync_strobe(2) = '1';
wait for 100*SYS_CLK_PERIOD;
cmd_data <= X"12340";
cmd_addr <= X"8B930";
wait until rising_edge(clk);
cmd_we <= '1';
wait until rising_edge(clk);
cmd_we <= '0';
for k in 1 to 10 loop
tx_pcm_we <= '0';
wait until rising_edge(clk) and sync_strobe(2) = '1';
wait for 10*BIT_CLK_PERIOD;
for i in 3 to 12 loop
tx_pcm_addr <= to_unsigned(i, 4);
tx_pcm_data <= to_unsigned(2048*k + integer(i), 20);
tx_pcm_we <= '1';
wait until rising_edge(clk);
end loop;
end loop;
tx_pcm_we <= '0';
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
tb_in : PROCESS(clk, rx_pcm_addr, sync_strobe)
BEGIN
if rising_edge(clk) then
if sync_strobe(1) = '1' then
rx_pcm_addr <= "0011";
elsif rx_pcm_addr /= "1100" then
rx_pcm_addr <= rx_pcm_addr + 1;
end if;
end if;
END PROCESS;
END;
lib/ac97_ctrl/src/tb_ac_out.vhd
+149
View File
@@ -0,0 +1,149 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:47 06/05/2007
-- Design Name: eval_ac
-- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd
-- Project Name: ac_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ac_out
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_ac_out IS
END tb_ac_out;
ARCHITECTURE behavior OF tb_ac_out IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ac_out
PORT(
rst : IN std_logic;
clk : IN std_logic;
sync_tx : OUT std_logic;
cmd_addr : IN unsigned(19 downto 0);
cmd_data : IN unsigned(19 downto 0);
cmd_we : IN std_logic;
pcm_in_addr : IN unsigned(3 downto 0);
pcm_in_data : IN unsigned(19 downto 0);
pcm_in_we : IN std_logic;
ac_bit_clk : IN std_logic;
ac_reset : in std_logic;
ac_sdata_out : OUT std_logic;
ac_ssync : OUT std_logic
);
END COMPONENT;
constant SYS_CLK_PERIOD : time := 10 ns;
constant BIT_CLK_PERIOD : time := 81.38 ns;
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '0';
SIGNAL ce : std_logic := '0';
SIGNAL cmd_we : std_logic := '0';
SIGNAL pcm_in_we : std_logic := '0';
SIGNAL ac_bit_clk : std_logic := '0';
SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0');
SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0');
SIGNAL pcm_in_addr : unsigned(3 downto 0) := (others=>'0');
SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0');
--Outputs
SIGNAL sync_tx : std_logic;
SIGNAL ac_reset : std_logic;
SIGNAL ac_sdata_out : std_logic;
SIGNAL ac_ssync : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ac_out PORT MAP(
rst => rst,
clk => clk,
sync_tx => sync_tx,
cmd_addr => cmd_addr,
cmd_data => cmd_data,
cmd_we => cmd_we,
pcm_in_addr => pcm_in_addr,
pcm_in_data => pcm_in_data,
pcm_in_we => pcm_in_we,
ac_reset => ac_reset,
ac_bit_clk => ac_bit_clk,
ac_sdata_out => ac_sdata_out,
ac_ssync => ac_ssync
);
sys_clk_gen :
PROCESS
BEGIN
wait for SYS_CLK_PERIOD;
clk <= not clk;
END PROCESS;
bit_clk_gen :
PROCESS
BEGIN
wait for BIT_CLK_PERIOD;
ac_bit_clk <= not ac_bit_clk;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100*SYS_CLK_PERIOD;
rst <= '0';
wait for 100*SYS_CLK_PERIOD;
ac_reset <= '0';
wait until rising_edge(clk) and sync_tx = '1';
wait for 100*SYS_CLK_PERIOD;
cmd_data <= X"aaaa0";
cmd_addr <= X"1DFC0";
wait until rising_edge(clk);
cmd_we <= '1';
wait until rising_edge(clk);
cmd_we <= '0';
for k in 1 to 10 loop
pcm_in_we <= '0';
wait until rising_edge(clk) and sync_tx = '1';
wait for 100*SYS_CLK_PERIOD;
for i in 3 to 12 loop
pcm_in_addr <= to_unsigned(i, 4);
pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
pcm_in_we <= '1';
wait until rising_edge(clk);
end loop;
end loop;
pcm_in_we <= '0';
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
lib/filter/sim/tb_fir_iterative.fdo
+5 -3
View File
@@ -1,11 +1,13 @@
vmap ieee_proposed ../../../Common/sim/ieee_proposed
vlib work
vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../src/filter_pkg.vhd"
vcom -explicit -93 "../src/fir_stage_pkg.vhd"
vcom -explicit -93 "../src/fir_pkg.vhd"
vcom -explicit -93 "../src/fir_stage.vhd"
vcom -explicit -93 "../src/fir_iterative_pkg.vhd"
vcom -explicit -93 "../src/fir_iterative.vhd"
vcom -explicit -93 "../src/tb_fir_iterative.vhd"
vsim -t 1ps -lib work tb_fir_iterative
lib/filter/sim/tb_fir_iterative.wdo
+65 -7
View File
@@ -53,8 +53,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
add wave -noupdate -divider {FIR Stage}
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/in_valid
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out_clr
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
@@ -64,12 +62,72 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/valid
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/p_valid
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/out_valid
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
add wave -noupdate -format Literal /tb_fir_iterative/coeffs
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
add wave -noupdate -format Literal /tb_fir_iterative/xi
add wave -noupdate -format Literal /tb_fir_iterative/yo
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem
add wave -noupdate -divider {Xmem Dual}
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
add wave -noupdate -format Literal /tb_fir_iterative/coeffs
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi
add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
add wave -noupdate -format Logic /tb_fir_iterative/y_valid
add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
add wave -noupdate -divider {FIR Stage}
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1892287 ps} 0}
WaveRestoreCursors {{Cursor 1} {5100000 ps} 0}
configure wave -namecolwidth 140
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -83,4 +141,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {1750644 ps} {2771198 ps}
WaveRestoreZoom {0 ps} {42 us}
lib/filter/sim/tb_fir_parallel.fdo
+5 -3
View File
@@ -1,11 +1,13 @@
vmap ieee_proposed ../../../Common/sim/ieee_proposed
vlib work
vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../src/filter_pkg.vhd"
vcom -explicit -93 "../src/fir_stage_pkg.vhd"
vcom -explicit -93 "../src/fir_pkg.vhd"
vcom -explicit -93 "../src/fir_stage.vhd"
vcom -explicit -93 "../src/fir_parallel_pkg.vhd"
vcom -explicit -93 "../src/fir_parallel.vhd"
vcom -explicit -93 "../src/tb_fir_parallel.vhd"
vsim -t 1ps -lib work tb_fir_parallel
lib/filter/sim/tb_fir_semi_parallel.fdo
+20
View File
@@ -0,0 +1,20 @@
vmap ieee_proposed ../../../Common/sim/ieee_proposed
vlib work
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../src/filter_pkg.vhd"
vcom -explicit -93 "../src/fir_pkg.vhd"
vcom -explicit -93 "../src/fir_stage_sys.vhd"
vcom -explicit -93 "../src/delay_line.vhd"
vcom -explicit -93 "../src/fir_semi_parallel.vhd"
vcom -explicit -93 "../src/tb_fir_semi_parallel.vhd"
vsim -t 1ps -lib work tb_fir_semi_parallel
do {tb_fir_semi_parallel.wdo}
view wave
view structure
view signals
run 50us
lib/filter/sim/tb_fir_semi_parallel.wdo
+57
View File
@@ -0,0 +1,57 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/rst
add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/clk
add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr
add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/h_in
add wave -noupdate -format Logic /tb_fir_semi_parallel/dout_vld
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_in
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_out
add wave -noupdate -format Logic /tb_fir_semi_parallel/rdy
add wave -noupdate -divider {Real out}
add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/xi
add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/yo
add wave -noupdate -divider -height 50 <NULL>
add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/count0
add wave -noupdate -format Logic /tb_fir_semi_parallel/din_vld
add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/start
add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/count_array
add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/en_array
add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/ce_array
add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr
add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we
add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/x
add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/accu_load
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/accu
add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/y
add wave -noupdate -divider {stage 1}
add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/clk
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/yin
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/prod
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/x_out
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/y_out
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__0/inst_delay_line/inst_dpram_1w1r/ram
add wave -noupdate -divider {stage 2}
add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/clk
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/yin
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/prod
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/x_out
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/y_out
add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__1/inst_delay_line/inst_dpram_1w1r/ram
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {486552931 ps} 0} {{Cursor 2} {49902384 ps} 0} {{Cursor 3} {148250000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {52500 ns}
lib/filter/sim/tb_fir_stage.fdo
+5 -2
View File
@@ -1,9 +1,12 @@
vmap ieee_proposed ../../../Common/sim/ieee_proposed
vlib work
vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../src/filter_pkg.vhd"
vcom -explicit -93 "../src/fir_stage_pkg.vhd"
vcom -explicit -93 "../src/fir_pkg.vhd"
vcom -explicit -93 "../src/fir_stage.vhd"
vcom -explicit -93 "../src/tb_fir_stage.vhd"
vsim -t 1ps -lib work tb_fir_stage
lib/filter/sim/tb_fir_stage_sys.fdo
+17
View File
@@ -0,0 +1,17 @@
vmap ieee_proposed ../../../Common/sim/ieee_proposed
vlib work
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../src/filter_pkg.vhd"
vcom -explicit -93 "../src/fir_pkg.vhd"
vcom -explicit -93 "../src/fir_stage_sys.vhd"
vcom -explicit -93 "../src/tb_fir_stage_sys.vhd"
vsim -t 1ps -lib work tb_fir_stage_sys
do {tb_fir_stage_sys.wdo}
view wave
view structure
view signals
run 2us
lib/filter/sim/tb_fir_stage_sys.wdo
+28
View File
@@ -0,0 +1,28 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_fir_stage_sys/clk
add wave -noupdate -divider Input
add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x_in
add wave -noupdate -format Literal /tb_fir_stage_sys/xi
add wave -noupdate -divider Output
add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y_out
add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_stage_sys/yo
add wave -noupdate -divider {Stage signals}
add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x
add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1060000 ps} 0}
configure wave -namecolwidth 140
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {706931 ps} {1268317 ps}

Some files were not shown because too many files have changed in this diff Show More