This commit was manufactured by cvs2svn to create tag 'R7'.

git-svn-id: http://moon:8086/svn/vhdl/tags/R7@121 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo

@@ -1,13 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/core/mips_types.vhd"
-vcom -explicit  -93 "../src/core/mips_instr.vhd"
-vcom -explicit  -93 "../src/tb_eval_muldiv.vhd"
-vsim -t 1ps   -lib work tb_eval_muldiv
-do {tb_eval_muldiv.wdo}
-view wave
-
-view structure
-view signals
-run 2400ns

lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo

@@ -1,27 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_eval_muldiv/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0
-add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1
-add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2
-add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3
-add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result
-add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0}
-configure wave -namecolwidth 149
-configure wave -valuecolwidth 171
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {2520 ns}

lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo

@@ -11,9 +11,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
 add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
 add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/result
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo
 add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
@@ -62,7 +61,7 @@ add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
 add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
 add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {1278050000 ps} 0}
+WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {102205454 ps} 0}
 configure wave -namecolwidth 149
 configure wave -valuecolwidth 171
 configure wave -justifyvalue left
@@ -76,4 +75,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {0 ps} {5250 us}
+WaveRestoreZoom {102150244 ps} {102363615 ps}

lib/CPUs/MIPS/src/core/dcache.vhd

@@ -14,23 +14,22 @@ ENTITY dcache IS
 	);
 	Port
 	(
-		clk			: in  STD_LOGIC;
-		rst			: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		STB_O		: out STD_LOGIC;
+		CYC_O		: out STD_LOGIC;
 		en			: in  STD_LOGIC;
 		cpu_en		: in  STD_LOGIC;
-		cpu_r_wn	: in  STD_LOGIC;
-		cpu_we		: in  unsigned(3 downto 0);
+		cpu_we		: in  STD_LOGIC;
+		cpu_be		: in  unsigned(3 downto 0);
 		cpu_addr	: in  word_t;
 		cpu_din		: in  word_t;
 		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC;
-		mem_req		: out STD_LOGIC;
-		mem_gnt		: in  STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_addr	: out word_t;
-		mem_din		: in  word_t;
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC
+		cpu_busy	: out STD_LOGIC
 	);
 END dcache;
 
@@ -93,14 +92,13 @@ END COMPONENT;
 	constant cache_index_width	: natural := lg2(cache_size) - word_index_width;
 	constant tag_width			: natural := 32 - word_index_width - cache_index_width - 2;
 	constant tag_parity_width	: natural := 3;
-	constant tram_data_width	: natural := 2 + tag_parity_width + tag_width;
+	constant tram_data_width	: natural := 1 + tag_parity_width + tag_width;
 	constant tram_addr_width	: natural := cache_index_width;
 	
 	subtype	tram_data_t is unsigned (tram_data_width-1 downto 0);
 
 	type dcache_entry_t is record
 		valid	: std_logic;
-		dirty	: std_logic;
 		tv_p	: unsigned(tag_parity_width-1 downto 0);
 		tag		: unsigned(tag_width-1 downto 0);
 	end record;
@@ -113,9 +111,8 @@ END COMPONENT;
 	variable result : dcache_entry_t;
 	begin
 		result.valid	:= x(0);
-		result.dirty	:= x(1);
-		result.tv_p		:= x(4 downto 2);
-		result.tag		:= x(tag_width+4 downto 5);
+		result.tv_p		:= x(3 downto 1);
+		result.tag		:= x(tag_width+3 downto 4);
 		
 		return result;
 	end to_dcache_entry;
@@ -124,19 +121,17 @@ END COMPONENT;
 	variable result : tram_data_t;
 	begin
 		result(0)										:= x.valid;
-		result(1)										:= x.dirty;
-		result(4 downto 2)								:= x.tv_p;
-		result(tag_width+4 downto 5)					:= x.tag;
+		result(3 downto 1)								:= x.tv_p;
+		result(tag_width+3 downto 4)					:= x.tag;
 		
 		return result;
 	end to_tram_data;
 
-	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache, wr_cache);
+	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
 	signal s, sn : cache_state_t;
 	
 	signal	cache_busy			: std_logic;
-	signal	cache_read_miss		: std_logic;
-	signal	cache_write_miss	: std_logic;
+	signal	cache_hit			: std_logic;
 	signal	tag_match			: std_logic;
 	signal  word_index_reg		: unsigned(word_index_width-1 downto 0);
 	signal  cache_index_reg		: unsigned(cache_index_width-1 downto 0);
@@ -148,15 +143,16 @@ END COMPONENT;
 	signal  cpu_dram_dout		: word_t;
 	signal  cpu_dram_din		: word_t;
 	signal  cpu_data_reg		: word_t;
-	signal  cpu_we_reg			: unsigned(3 downto 0);
-	signal  ctrl_force_we		: unsigned(3 downto 0);
-	signal  cpu_was_write		: std_logic;
+	signal  cpu_be_reg			: unsigned(3 downto 0);
+	signal  cpu_we_reg			: std_logic;
+	signal	ctrl_dram_en		: std_logic;
 	signal  ctrl_dram_addr		: unsigned(lg2(cache_size)-1 downto 0);
 	signal  ctrl_dram_din		: word_t;
 	signal	ctrl_dram_we		: unsigned(3 downto 0);
 	signal	cpu_dram_we			: unsigned(3 downto 0);
-	signal	dram_en				: std_logic;
-	signal	cpu_was_en			: std_logic;
+	signal	cpu_dram_en			: std_logic;
+	signal	cpu_en2				: std_logic;
+	signal	cpu_we2				: std_logic;
 
 	signal  tram_addr_rd		: unsigned(cache_index_width-1 downto 0);
 	signal  tram_dout			: tram_data_t;
@@ -175,52 +171,72 @@ END COMPONENT;
 	signal	cpu_reg_en				: std_logic;
 	signal	was_miss				: std_logic;
 	signal	data_write				: std_logic;
-	signal	cpu_we2					: std_logic;
+	signal	cpu_hit_we				: std_logic;
+	signal	instant_raw				: std_logic;
 
 begin
 
+	cpu_hit_we	<= cpu_we2 and cache_hit;
 	
-cpu_index_reg:
-	process(clk)
+cpu_index_register:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				cache_index_reg	<= (others => '0');
 				tag_index_reg	<= (others => '0');
-				cpu_was_write	<= '0';
-			elsif cpu_reg_en = '1' and en = '1' then
+			elsif cpu_reg_en = '1' and en = '1' and instant_raw = '0' then
 				word_index_reg	<= cpu_word_index;
 				cache_index_reg	<= cpu_cache_index;
 				tag_index_reg	<= cpu_tag;
-				cpu_data_reg	<= cpu_din;
-				cpu_we_reg		<= cpu_we;
-				cpu_was_write	<= not cpu_r_wn;
 			end if;
 		end if;
 	end process;	
 
-cpu_was_wr_reg:
-	process(clk)
+cpu_data_register:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			cpu_was_en	<= '0';
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cpu_we_reg	<= '0';
+			elsif cpu_reg_en = '1' and en = '1' then
+				cpu_data_reg	<= cpu_din;
+				cpu_be_reg		<= cpu_be;
+				cpu_we_reg		<= cpu_we;
+			end if;
+		end if;
+	end process;	
+
+cpu_was_wr_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			cpu_en2	<= '0';
 			cpu_we2		<= '0';
 			if cpu_en = '1' and en = '1' then
-				cpu_we2		<= not cpu_r_wn;
-				cpu_was_en	<= '1';
+				cpu_we2			<= cpu_we;
+				cpu_en2			<= '1';
 				cpu_dram_din	<= cpu_din;
 			end if;
 		end if;
 	end process;	
 
+instant_raw_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			instant_raw	<= cpu_hit_we and cpu_en and en and not cpu_we;
+		end if;
+	end process;	
+
 inst_tag_ram : dpram_1w1r
 	GENERIC MAP (
 		addr_width	=> tram_addr_width,
 		data_width	=> tram_data_width
 	)
 	PORT MAP (
-		clka	=> clk,
-		clkb	=> clk,
+		clka	=> CLK_I,
+		clkb	=> CLK_I,
 		en_a	=> '1',
 		en_b	=> tram_re,
 		we_a	=> tram_we,
@@ -240,10 +256,10 @@ gen_data_ram:
 			data_width	=> word_t'length/4
 		)
 		PORT MAP (
-			clk_a	=> clk,
-			clk_b	=> clk,
-			en_a	=> '1',
-			en_b	=> dram_en,
+			clk_a	=> CLK_I,
+			clk_b	=> CLK_I,
+			en_a	=> ctrl_dram_en,
+			en_b	=> '1',
 			we_a	=> ctrl_dram_we(i),
 			we_b	=> cpu_dram_we(i),
 			addr_a	=> ctrl_dram_addr,
@@ -256,10 +272,10 @@ gen_data_ram:
 	end generate;	
 	
 cache_state_next:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				s	<= init;
 			else
 				s	<= sn;
@@ -267,24 +283,24 @@ cache_state_next:
 		end if;
 	end process;	
 
-	cpu_busy			<= cache_busy;
+	cpu_busy			<= cache_busy or instant_raw;
 	cpu_dout			<= cpu_dram_dout;
 	
 	tag_match			<= '1' when tag_index_reg = cache_entry_out.tag else '0';
-	cache_read_miss		<= not (tag_match and cache_entry_out.valid) and not cpu_was_write;
-	cache_write_miss	<= not (tag_match and cache_entry_out.valid and cpu_was_write);
+	cache_hit			<= tag_match and cache_entry_out.valid;
 	tram_din			<= to_tram_data(cache_entry_in);
 	tram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
 	cache_entry_out		<= to_dcache_entry(tram_dout);
-	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg);
-	mem_addr			<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
+	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_hit_we = '0' and instant_raw = '0') else (cache_index_reg & word_index_reg);
+	ADDR_O				<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
 	ctrl_dram_addr		<= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
-	ctrl_dram_din		<= mem_din;
-	ctrl_dram_we		<= (3 downto 0 => (data_write and mem_valid)) or ctrl_force_we;
-	cpu_dram_we			<= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0');
+	ctrl_dram_din		<= DAT_I;
+	ctrl_dram_we		<= (others => '1');
+	ctrl_dram_en		<= data_write and ACK_I;
+	cpu_dram_we			<= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
 	
 cache_state:
-	process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, cpu_r_wn, mem_gnt, mem_rdy, cpu_was_en, cpu_was_write, cpu_we_reg)
+	process(s, instant_raw, cache_hit, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg)
 	begin
 		cpu_reg_en				<= '0';
 		cache_busy 				<= '1';
@@ -293,9 +309,8 @@ cache_state:
 		ram_index_count_rst		<= '0';
 		mem_index_count_en		<= '0';
 		mem_index_count_rst		<= '0';
-		mem_req					<= '0';
-		mem_en					<= '0';
-		dram_en					<= '0';
+		CYC_O					<= '0';
+		STB_O					<= '0';
 		tram_re					<= '0';
 		was_miss				<= '0';
 		data_write				<= '0';
@@ -303,8 +318,6 @@ cache_state:
 		cache_entry_in.tv_p		<= (others => '0');
 		cache_entry_in.tag		<= tag_index_reg;
 		cache_entry_in.valid	<= '0';
-		cache_entry_in.dirty	<= '0';
-		ctrl_force_we			<= (others => '0');
 		sn	<= s;
 		
 		case s is
@@ -313,13 +326,13 @@ cache_state:
 		when ready =>
 			cache_busy 		<= '0';
 			cpu_reg_en		<= '1';
-			dram_en			<= cpu_en or cpu_was_en;
 			tram_re			<= cpu_en;
-			if cpu_was_en = '1' then
-				if cache_read_miss = '1' then
+			if cpu_en2 = '1' then
+				if cache_hit = '0' and cpu_we_reg = '0' then
 					sn						<= mem_request;
 					cpu_reg_en				<= '0';
 					cache_busy 				<= '1';
+					CYC_O					<= '1';
 				end if;	
 			end if;	
 		when flush =>
@@ -332,65 +345,53 @@ cache_state:
 				sn	<= ready;
 				if cpu_en = '1' then
 					cpu_reg_en			<= '1';
-					dram_en			<= '1';
-					tram_re			<= '1';
+					tram_re				<= '1';
 				end if;
 			end if;
 		when mem_request =>
 			ram_index_count_rst		<= '1';
 			mem_index_count_rst		<= '1';
-			mem_req		<= '1';
-			if mem_gnt = '1' then
+			CYC_O		<= '1';
+			if SRDY_I = '1' then
 				sn <= mem_access;
 			end if;	
 		when mem_access =>
-			data_write	<= '1';
-			mem_req		<= '1';
-			if mem_rdy = '1' then
-				mem_index_count_en	<= '1';
-				mem_en				<= '1';
-				if mem_index_count = 2**word_index_width-1 then
-					sn			<= mem_data;
+			data_write			<= '1';
+			mem_index_count_en	<= '1';
+			CYC_O				<= '1';
+			STB_O				<= '1';
+			if mem_index_count = 2**word_index_width-1 then
+				if SRDY_I = '1' then
+					sn <= mem_data;
 				end if;	
 			end if;	
 		when mem_data =>
-			mem_req		<= '1';
+			CYC_O		<= '1';
 			data_write	<= '1';
 			if ram_index_count = 2**word_index_width-1 then
-				if mem_valid = '1' then
+				if ACK_I = '1' then
 					sn			<= upd_cache;
 				end if;	
 			end if;	
 		when upd_cache =>
-			mem_req					<= '1';
 			tram_addr_wr			<= cache_index_reg;
 			tram_we					<= '1';
 			cache_entry_in.valid	<= '1';
-			if cpu_was_write = '1' then
-				sn					<= wr_cache;
-			else	
-				sn					<= rd_cache;
-			end if;	
-			
+			sn						<= rd_cache;
 		when rd_cache =>
 			tram_re					<= '1';
-			dram_en					<= '1';
 			was_miss				<= '1';
 			sn	<= ready;
 
-		when wr_cache =>
-			tram_re					<= '1';
-			ctrl_force_we			<= cpu_we_reg;
-			sn	<= ready;
 		when others => 
 			sn	<= ready;
 		end case;
 	end process;
 
 cache_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if cache_index_count_en = '0' then
 				cache_index_count	<= 2**cache_index_width-1;
 			elsif cache_index_count /= 0 then
@@ -400,12 +401,12 @@ cache_index_counter:
 	end process;	
 		
 ram_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if ram_index_count_rst = '1' then
 				ram_index_count	<= 0;
-			elsif data_write = '1' and mem_valid = '1' then
+			elsif data_write = '1' and ACK_I = '1' then
 				if ram_index_count /= 2**word_index_width-1 then
 					ram_index_count 	<= ram_index_count + 1;
 				end if;
@@ -414,12 +415,12 @@ ram_index_counter:
 	end process;	
 
 mem_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if mem_index_count_rst = '1' then
 				mem_index_count	<= 0;
-			elsif mem_index_count_en = '1' then
+			elsif mem_index_count_en = '1' and SRDY_I = '1' then
 				if mem_index_count /= 2**word_index_width-1 then
 					mem_index_count 	<= mem_index_count + 1;
 				end if;

lib/CPUs/MIPS/src/core/icache.vhd

@@ -14,20 +14,19 @@ ENTITY icache IS
 	);
 	Port
 	(
-		clk			: in  STD_LOGIC;
-		rst			: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		STB_O		: out STD_LOGIC;
+		CYC_O		: out STD_LOGIC;
 		en			: in  STD_LOGIC;
 		cpu_en		: in  STD_LOGIC;
 		cpu_addr	: in  word_t;
 		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC;
-		mem_req		: out STD_LOGIC;
-		mem_gnt		: in  STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_addr	: out word_t;
-		mem_din		: in  word_t;
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC
+		cpu_busy	: out STD_LOGIC
 	);
 END icache;
 
@@ -143,10 +142,10 @@ begin
 
 	
 cpu_index_reg:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				cache_index_reg	<= (others => '0');
 				tag_index_reg	<= (others => '0');
 			elsif cpu_reg_en = '1' then
@@ -163,8 +162,8 @@ inst_tag_ram : dpram_1w1r
 		data_width	=> tag_ram_data_width
 	)
 	PORT MAP (
-		clka	=> clk,
-		clkb	=> clk,
+		clka	=> CLK_I,
+		clkb	=> CLK_I,
 		en_a	=> '1',
 		en_b	=> tag_ram_re,
 		we_a	=> tag_ram_we,
@@ -180,8 +179,8 @@ inst_data_ram : dpram_1w1r
 		data_width	=> word_t'length
 	)
 	PORT MAP (
-		clka	=> clk,
-		clkb	=> clk,
+		clka	=> CLK_I,
+		clkb	=> CLK_I,
 		en_a	=> '1',
 		en_b	=> data_ram_re,
 		we_a	=> data_ram_we,
@@ -193,10 +192,10 @@ inst_data_ram : dpram_1w1r
 	
 	
 cache_state_next:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				s	<= init;
 			else
 				s	<= sn;
@@ -213,13 +212,13 @@ cache_state_next:
 	tag_ram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
 	cache_entry_out		<= to_icache_entry(tag_ram_data_rd);
 	data_ram_addr_rd	<= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg);
-	mem_addr			<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
+	ADDR_O				<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
 	data_ram_addr_wr	<= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
-	data_ram_data_wr	<= mem_din;
-	data_ram_we			<= data_write and mem_valid;
+	data_ram_data_wr	<= DAT_I;
+	data_ram_we			<= data_write and ACK_I;
 
 cache_state:
-	process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, mem_gnt, mem_rdy, en)
+	process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, en)
 	begin
 		cpu_reg_en				<= '0';
 		cache_busy 				<= '1';
@@ -228,8 +227,8 @@ cache_state:
 		ram_index_count_rst		<= '0';
 		mem_index_count_en		<= '0';
 		mem_index_count_rst		<= '0';
-		mem_req					<= '0';
-		mem_en					<= '0';
+		CYC_O					<= '0';
+		STB_O					<= '0';
 		data_ram_re				<= '0';
 		tag_ram_re				<= '0';
 		was_miss				<= '0';
@@ -250,6 +249,7 @@ cache_state:
 					sn						<= mem_request;
 					cpu_reg_en				<= '0';
 					cache_busy 				<= '1';
+					CYC_O					<= '1';
 				elsif cpu_en = '1' then
 					cpu_reg_en			<= '1';
 					data_ram_re			<= '1';
@@ -273,37 +273,35 @@ cache_state:
 		when mem_request =>
 			ram_index_count_rst		<= '1';
 			mem_index_count_rst		<= '1';
-			mem_req		<= '1';
-			if mem_gnt = '1' then
+			CYC_O		<= '1';
+			if SRDY_I = '1' then
 				sn <= mem_access;
 			end if;	
 		when mem_access =>
+			mem_index_count_en	<= '1';
 			data_write	<= '1';
-			mem_req		<= '1';
-			if mem_rdy = '1' then
-				mem_index_count_en	<= '1';
-				mem_en				<= '1';
-				if mem_index_count = 2**word_index_width-1 then
+			CYC_O		<= '1';
+			STB_O		<= '1';
+			if mem_index_count = 2**word_index_width-1 then
+				if SRDY_I = '1' then
 					sn			<= mem_data;
 				end if;	
 			end if;	
 		when mem_data =>
-			mem_req		<= '1';
+			CYC_O		<= '1';
 			data_write	<= '1';
 			if ram_index_count = 2**word_index_width-1 then
-				if mem_valid = '1' then
+				if ACK_I = '1' then
 					sn			<= upd_cache;
 				end if;	
 			end if;	
 		when upd_cache =>
-			mem_req					<= '1';
 			tag_ram_addr_wr			<= cache_index_reg;
 			tag_ram_we				<= '1';
 			cache_entry_in.valid	<= '1';
 			sn						<= rd_cache;
 			
 		when rd_cache =>
---			mem_req					<= '1';
 			tag_ram_re				<= '1';
 			data_ram_re				<= '1';
 			was_miss				<= '1';
@@ -314,9 +312,9 @@ cache_state:
 	end process;
 
 cache_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if cache_index_count_en = '0' then
 				cache_index_count	<= 2**cache_index_width-1;
 			elsif cache_index_count /= 0 then
@@ -326,12 +324,12 @@ cache_index_counter:
 	end process;	
 		
 ram_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if ram_index_count_rst = '1' then
 				ram_index_count	<= 0;
-			elsif data_write = '1' and mem_valid = '1' then
+			elsif data_write = '1' and ACK_I = '1' then
 				if ram_index_count /= 2**word_index_width-1 then
 					ram_index_count 	<= ram_index_count + 1;
 				end if;
@@ -340,12 +338,12 @@ ram_index_counter:
 	end process;	
 
 mem_index_counter:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
+		if rising_edge(CLK_I) then
 			if mem_index_count_rst = '1' then
 				mem_index_count	<= 0;
-			elsif mem_index_count_en = '1' then
+			elsif mem_index_count_en = '1' and SRDY_I = '1' then
 				if mem_index_count /= 2**word_index_width-1 then
 					mem_index_count 	<= mem_index_count + 1;
 				end if;

lib/CPUs/MIPS/src/core/mips_bcu.vhd

@@ -46,7 +46,6 @@ architecture Behavioral of bcu is
 begin
 
 	flags.eq	<= '1' when op1_in = op2_in else '0' after 3 ns;
-	flags.z		<= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns;
 	flags.ltz	<= op1_in(op1_in'left) after 1 ns;
 
 --------------------------------------------------------------------------

lib/CPUs/MIPS/src/core/mips_bui.vhd

@@ -29,318 +29,429 @@ library work;
 use work.mips_types.all;
 
 entity bui is
+	Generic
+	(
+		icache_size	: natural := 2048;	-- words
+		dcache_size	: natural := 2048	-- words
+	);
 	Port
 	(
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		ce				: in  STD_LOGIC;
-		cpu_wait		: out STD_LOGIC;
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		ADDR_O			: out word_t;
+		DAT_I			: in  word_t;
+		DAT_O			: out word_t;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		cpu_imem_err	: out STD_LOGIC;
 		cpu_imem_rdy	: out STD_LOGIC;
 		cpu_imem_en		: in  STD_LOGIC;
 		cpu_imem_addr	: in  word_t;
 		cpu_imem_din	: out word_t;
+		cpu_dmem_err	: out STD_LOGIC;
 		cpu_dmem_rdy	: out STD_LOGIC;
 		cpu_dmem_en		: in  STD_LOGIC;
-		cpu_dmem_re		: in  STD_LOGIC;
-		cpu_dmem_we		: in  unsigned(3 downto 0);
+		cpu_dmem_we		: in  STD_LOGIC;
+		cpu_dmem_be		: in  unsigned(3 downto 0);
 		cpu_dmem_dout	: in  word_t;
 		cpu_dmem_din	: out word_t;
-		cpu_dmem_addr	: in  word_t;
-		mem_valid		: in  STD_LOGIC;
-		mem_rdy			: in  STD_LOGIC;
-		mem_addr		: out word_t;
-		mem_din			: in  word_t;
-		mem_dout		: out word_t;
-		mem_re			: out STD_LOGIC;
-		mem_we			: out unsigned(3 downto 0);
-		mem_ce			: out STD_LOGIC
+		cpu_dmem_addr	: in  word_t
 	);
-	
 end bui;
 
 architecture behavior of bui is
 
-COMPONENT icache
+	COMPONENT icache
 	GENERIC
 	(
-		cache_size	: natural := 2048;	-- words
-		line_size	: natural := 8		-- words
+		cache_size	: natural;	-- words
+		line_size	: natural	-- words
 	);
 	PORT
 	(
-		clk			: in  STD_LOGIC;
-		rst			: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		STB_O		: out STD_LOGIC;
+		CYC_O		: out STD_LOGIC;
 		en			: in  STD_LOGIC;
 		cpu_en		: in  STD_LOGIC;
 		cpu_addr	: in  word_t;
 		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_req		: out STD_LOGIC;
-		mem_gnt		: in  STD_LOGIC;
-		mem_addr	: out word_t;
-		mem_din		: in  word_t;
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC
+		cpu_busy	: out STD_LOGIC
 	);
-END COMPONENT;
+	END COMPONENT;
 
-COMPONENT dcache
+	COMPONENT dcache
 	GENERIC
 	(
-		cache_size	: natural := 2048;	-- words
-		line_size	: natural := 8		-- words
+		cache_size	: natural;	-- words
+		line_size	: natural	-- words
 	);
 	PORT
 	(
-		clk			: in  STD_LOGIC;
-		rst			: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		STB_O		: out STD_LOGIC;
+		CYC_O		: out STD_LOGIC;
 		en			: in  STD_LOGIC;
 		cpu_en		: in  STD_LOGIC;
-		cpu_r_wn	: in  STD_LOGIC;
-		cpu_we		: in  unsigned(3 downto 0);
+		cpu_we		: in  STD_LOGIC;
+		cpu_be		: in  unsigned(3 downto 0);
 		cpu_addr	: in  word_t;
 		cpu_din		: in  word_t;
 		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC;
-		mem_req		: out STD_LOGIC;
-		mem_gnt		: in  STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_addr	: out word_t;
-		mem_din		: in  word_t;
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC
+		cpu_busy	: out STD_LOGIC
 	);
-END COMPONENT;
+	END COMPONENT;
 
-	type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, d_bus_start, d_bus_access, d_bus_finish);
+	type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish);
 	
-	signal s, sn : bus_state_t;
-	signal dmem_re			: std_logic;
-	signal dmem_we			: unsigned(3 downto 0);
+	signal s, sn 			: bus_state_t;
+	signal bus_idle			: std_logic;
+	signal busy				: std_logic;
+	signal dmem_be			: unsigned(3 downto 0);
 	signal dcache_dout		: word_t;
-	signal dmem_dout		: word_t;
-	signal dmem_din			: word_t;
-	signal dmem_addr		: word_t;
-	signal imem_addr		: word_t;
-	signal imem_mem_out_en	: std_logic;
-	signal dmem_mem_out_en 	: std_logic;
-	signal imem_valid 		: std_logic;
-	signal dmem_valid 		: std_logic;
-	signal dmem_ack			: std_logic;
-	signal dcache_req		: std_logic;
-	signal dcache_busy1		: std_logic;
-	signal dcache_busy2		: std_logic;
-	signal icache_busy 		: std_logic;
-	signal bus_req	 		: std_logic;
-	signal bus_bsy	 		: std_logic;
-	signal icache_mem_en	: std_logic;
-	signal icache_mem_req	: std_logic;
-	signal icache_mem_gnt	: std_logic;
-	signal icache_mem_addr	: word_t;
-	signal dcache_mem_en	: std_logic;
-	signal dcache_mem_req	: std_logic;
 	signal dcache_mem_gnt	: std_logic;
-	signal dcache_mem_addr	: word_t;
-	signal contention		: std_logic;
+	signal icache_mem_gnt 	: std_logic;
+	signal dmem_mem_wr_gnt	: std_logic;
+	signal dmem_mem_rd_gnt	: std_logic;
+	signal dcache_busy		: std_logic;
+	signal icache_busy 		: std_logic;
+	signal CYC_O_icache		: std_logic;
+	signal CYC_O_dcache		: std_logic;
+	signal CYC_O_dmem_rd	: std_logic;
+	signal CYC_O_dmem_wr	: std_logic;
+	signal SRDY_I_icache	: std_logic;
+	signal SRDY_I_dcache	: std_logic;
+	signal ADDR_O_icache	: word_t;
+	signal ADDR_O_dcache	: word_t;
+	signal ADDR_O_dmem_rd	: word_t;
+	signal ADDR_O_dmem_wr	: word_t;
+	signal STB_O_icache		: std_logic;
+	signal STB_O_dcache		: std_logic;
+	signal STB_O_dmem_rd	: std_logic;
+	signal STB_O_dmem_wr	: std_logic;
+	signal DAT_I_dmem_rd	: word_t;
+	signal DAT_O_dmem_wr	: word_t;
+	signal SEL_O_dmem_wr	: unsigned(3 downto 0);
 	signal dcached			: std_logic;
-	signal duncached_access	: std_logic;
+	signal dcache_en		: std_logic;
+	signal uncached_access	: std_logic;
+	
+	type timeout_cnt_t is range 0 to 1E5-1;	
+	signal bus_timeout_cnt	: timeout_cnt_t;
+	signal bus_timeout		: std_logic;
+	
+	signal bout_fifo_din	: unsigned(68 downto 0);
+	signal bout_fifo_dout	: unsigned(68 downto 0);
+	signal bout_fifo_re		: std_logic;
+	signal bout_fifo_we		: std_logic;
+	signal bout_fifo_full	: std_logic;
+	signal bout_fifo_empty	: std_logic;
+	signal bout_rdy			: std_logic;
+
+	alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
+	alias bout_fifo_data_in is bout_fifo_din(63 downto 32);
+	alias bout_fifo_sel_in is bout_fifo_din(67 downto 64);
+	alias bout_fifo_we_in is bout_fifo_din(68);
+	alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0);
+	alias bout_fifo_data_out is bout_fifo_dout(63 downto 32);
+	alias bout_fifo_sel_out is bout_fifo_dout(67 downto 64);
+	alias bout_fifo_we_out is bout_fifo_dout(68);
+
+	signal write_fifo_din	: unsigned(67 downto 0);
+	signal write_fifo_dout	: unsigned(67 downto 0);
+	signal write_fifo_re	: std_logic;
+	signal write_fifo_we	: std_logic;
+	signal write_fifo_full	: std_logic;
+	signal write_fifo_empty	: std_logic;
+	signal write_busy		: std_logic;
+
+	alias write_fifo_addr_in is write_fifo_din(31 downto 0);
+	alias write_fifo_data_in is write_fifo_din(63 downto 32);
+	alias write_fifo_sel_in is write_fifo_din(67 downto 64);
+	alias write_fifo_addr_out is write_fifo_dout(31 downto 0);
+	alias write_fifo_data_out is write_fifo_dout(63 downto 32);
+	alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
+
+	signal read_cycle	: std_logic;
 
 begin
 
-	mem_ce 			<= mem_rdy and bus_req;
-	contention		<= 	dcache_req and icache_mem_req;
+
+	MRDY_O			<= '1';
+
+read_cyc_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				read_cycle		<= '0';
+			else
+				read_cycle 		<= (dmem_mem_rd_gnt and CYC_O_dmem_rd) 
+								or (dcache_mem_gnt and CYC_O_dcache) 
+								or (icache_mem_gnt and CYC_O_icache);
+			end if;
+		end if;
+	end process;	
+					
+	CYC_O			<= not bout_fifo_empty or read_cycle;
+	STB_O			<= not bout_fifo_empty;
+	ADDR_O			<= bout_fifo_addr_out;
+	DAT_O			<= bout_fifo_data_out;
+	SEL_O			<= bout_fifo_sel_out;
+	WE_O			<= bout_fifo_we_out;
 
 	cpu_imem_rdy	<= not icache_busy after 4.5 ns;
---	cpu_imem_din	<= imem_din;
---	cpu_wait		<= busy after 5.5 ns;
-	cpu_wait		<= '0';
-	cpu_dmem_rdy	<= not (dcache_busy1 or dcache_busy2) after 4.5 ns;
+	busy			<= CYC_O_dmem_rd or dcache_busy or (write_busy);
+	cpu_dmem_rdy	<= not busy after 4.5 ns;
 	
 inst_icache : icache
 	GENERIC MAP
 	(
-		cache_size	=> 2048,	-- words
+		cache_size	=> icache_size,	-- words
 		line_size	=> 8
 	)	
 	PORT MAP
 	(
-		clk			=> clk,
-		rst			=> rst,
+		CLK_I		=> CLK_I,
+		RST_I		=> RST_I,
+		STB_O		=> STB_O_icache,
+		CYC_O		=> CYC_O_icache,
+		ADDR_O		=> ADDR_O_icache,
+		DAT_I		=> DAT_I,
+		ACK_I		=> ACK_I,
+		SRDY_I		=> SRDY_I_icache,
 		en			=> '1',
 		cpu_en		=> cpu_imem_en,
 		cpu_addr	=> cpu_imem_addr,
 		cpu_dout	=> cpu_imem_din,
-		cpu_busy	=> icache_busy,
-		mem_en		=> icache_mem_en,
-		mem_req		=> icache_mem_req,
-		mem_gnt		=> icache_mem_gnt,
-		mem_addr	=> icache_mem_addr,
-		mem_din		=> mem_din,
-		mem_valid	=> imem_valid,
-		mem_rdy		=> mem_rdy
+		cpu_busy	=> icache_busy
 	);
 
+	SRDY_I_icache	<= bout_rdy and icache_mem_gnt;
+
 inst_dcache : dcache
 	GENERIC MAP
 	(
-		cache_size	=> 2048,	-- words
+		cache_size	=> dcache_size,	-- words
 		line_size	=> 8
 	)
 	PORT MAP
 	(
-		clk			=> clk,
-		rst			=> rst,
+		CLK_I		=> CLK_I,
+		RST_I		=> RST_I,
+		CYC_O		=> CYC_O_dcache,
+		STB_O		=> STB_O_dcache,
+		ADDR_O		=> ADDR_O_dcache,
+		DAT_I		=> DAT_I,
+		ACK_I		=> ACK_I,
+		SRDY_I		=> SRDY_I_dcache,
 		en			=> dcached,
-		cpu_en		=> cpu_dmem_en,
-		cpu_r_wn	=> cpu_dmem_re,
+		cpu_en		=> dcache_en,
 		cpu_we		=> cpu_dmem_we,
+		cpu_be		=> cpu_dmem_be,
 		cpu_addr	=> cpu_dmem_addr,
 		cpu_din		=> cpu_dmem_dout,
 		cpu_dout	=> dcache_dout,
-		cpu_busy	=> dcache_busy2,
-		mem_req		=> dcache_mem_req,
-		mem_gnt		=> dcache_mem_gnt,
-		mem_en		=> dcache_mem_en,
-		mem_addr	=> dcache_mem_addr,
-		mem_din		=> mem_din,
-		mem_valid	=> dmem_valid,
-		mem_rdy		=> mem_rdy
+		cpu_busy	=> dcache_busy
 	);
 
-	dcached			<= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0';
-	cpu_dmem_din	<= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns;
+	SRDY_I_dcache	<= bout_rdy and dcache_mem_gnt;
 
-dcache_flags:
-	process(clk)
+	dcached			<= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0';
+	cpu_dmem_din	<= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd;
+	dcache_en		<= cpu_dmem_en and not busy;
+	
+-- Instantiate synchronous FIFO
+inst_bout_fifo: entity work.fifo_sync_dist
+	GENERIC MAP
+	(
+		addr_width	=> 4,
+		data_width	=> 69
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	bout_fifo_we,
+		re			=>	bout_fifo_re,
+		fifo_full	=>	bout_fifo_full,
+		fifo_empty	=>	bout_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  bout_fifo_din,
+		data_r		=>  bout_fifo_dout
+	);
+	bout_rdy			<= not bout_fifo_full;
+	bout_fifo_re		<= not bout_fifo_empty and SRDY_I;
+	
+	bout_fifo_we		<= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
+
+	bout_fifo_data_in	<= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
+	
+	bout_fifo_addr_in	<= ADDR_O_dmem_wr when dmem_mem_wr_gnt = '1' else
+						   ADDR_O_dmem_rd when dmem_mem_rd_gnt = '1' else
+						   ADDR_O_dcache when dcache_mem_gnt = '1' else
+						   ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
+
+	bout_fifo_sel_in	<= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '0');
+	bout_fifo_we_in		<= '1' when dmem_mem_wr_gnt = '1' else '0';
+
+-- Instantiate synchronous FIFO
+inst_write_fifo: entity work.fifo_sync_dist
+	GENERIC MAP
+	(
+		addr_width			=> 4,
+		data_width			=> 68
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	write_fifo_we,
+		re			=>	write_fifo_re,
+		fifo_full	=>	write_busy,
+		fifo_empty	=>	write_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  write_fifo_din,
+		data_r		=>  write_fifo_dout
+	);
+
+	CYC_O_dmem_wr	<= not write_fifo_empty;
+	DAT_O_dmem_wr	<= write_fifo_data_out;
+	ADDR_O_dmem_wr	<= write_fifo_addr_out;
+	SEL_O_dmem_wr	<= write_fifo_sel_out;
+
+	write_fifo_data_in	<= cpu_dmem_dout;
+	write_fifo_addr_in	<= cpu_dmem_addr;
+	write_fifo_sel_in	<= cpu_dmem_be;
+	write_fifo_re		<= STB_O_dmem_wr;
+	write_fifo_we		<= cpu_dmem_en and not busy and cpu_dmem_we;
+	
+dmem_rd_flags:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				dcache_busy1		<= '0';
-				dcache_req		<= '0';
+		if rising_edge(CLK_I) then
+			uncached_access	<= '0';
+			if RST_I = '1' then
+				CYC_O_dmem_rd		<= '0';
 			else	
-				duncached_access <= '0';
-				if dmem_ack = '1' then
-					duncached_access <= '1';
-					dcache_req		<= '0';
-					if dmem_re = '1' then
-						if dmem_valid = '1' then
-							dcache_busy1		<= '0';
-						end if;	
-					else
-						dcache_busy1		<= '0';
-					end if;	
+				if ACK_I = '1' and dmem_mem_rd_gnt = '1' then
+					uncached_access		<= '1';
+					CYC_O_dmem_rd		<= '0';
 				end if;	
-				if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then
-					dcache_req		<= '1';
-					dcache_busy1		<= '1';
-					if dcached = '1' and cpu_dmem_re = '1' then
-						dcache_req		<= '0';
-						dcache_busy1	<= '0';
+				if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then
+					if dcached = '0' then
+						CYC_O_dmem_rd	<= '1';
 					end if;	
 				end if;
 			end if;
 		end if;
 	end process;	
 	
-dcache_regs:
-	process(clk)
+dmem_rd_data:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then
-				dmem_dout		<= cpu_dmem_dout;
-				dmem_addr		<= cpu_dmem_addr;
-				dmem_re			<= cpu_dmem_re;
-				dmem_we			<= cpu_dmem_we;
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				DAT_I_dmem_rd		<= (others => '0');
+			elsif ACK_I = '1' and CYC_O_dmem_rd = '1' then
+				DAT_I_dmem_rd		<= DAT_I;
 			end if;
 		end if;
 	end process;	
 	
-dcache_data:
-	process(clk)
+dmem_rd_regs:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				dmem_din		<= (others => '0');
-			elsif dmem_valid = '1' then
-				dmem_din		<= mem_din;
+		if rising_edge(CLK_I) then
+			if cpu_dmem_en = '1' and busy = '0' then
+				ADDR_O_dmem_rd		<= cpu_dmem_addr;
 			end if;
 		end if;
 	end process;	
 	
 bus_state_next:
-	process(clk)
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
 				s	<= init;
-			elsif ce = '1' then
+			else
 				s	<= sn;
 			end if;
 		end if;
 	end process;	
 	
 bus_state:
-	process(s, icache_mem_en, icache_mem_req, dcache_mem_req, dcache_mem_en, dcache_req, dmem_re, mem_rdy, mem_valid)
+	process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK_I)
 	begin
 		
-		imem_mem_out_en	<= '0';
-		dmem_mem_out_en	<= '0';
-		icache_mem_gnt	<= '0';
-		dcache_mem_gnt	<= '0';
-		imem_valid		<= '0';
-		dmem_valid		<= '0';
-		dmem_ack		<= '0';
-		bus_bsy			<= '1';
-		
-		sn				<= s;
+		icache_mem_gnt		<= '0';
+		dcache_mem_gnt		<= '0';
+		dmem_mem_rd_gnt		<= '0';	
+		dmem_mem_wr_gnt		<= '0';	
+		STB_O_dmem_rd		<= '0';
+		STB_O_dmem_wr		<= '0';
+		bus_idle			<= '0';
+		sn					<= s;
 		case s is
 		when init =>
-			if mem_rdy = '1' then
-				sn		<= ready;
-			end if;	
+			sn		<= ready;
 		when ready =>
-			bus_bsy		<= not mem_rdy;
-			if dcache_req = '1' then
-				if dcache_busy1 = '1' then
-					if mem_rdy = '1' then
-						dmem_mem_out_en	<= '1';
-						if dmem_re = '0' then
-							dmem_ack	<= '1';
-						else
-							sn			<= d_bus_access;
-						end if;
-					end if;
-				end if;	
-			elsif icache_mem_req = '1' then
-				sn				<= i_cache_bus_access;
-			elsif dcache_mem_req = '1' then
-				sn				<= d_cache_bus_access;
+			bus_idle	<= '1';
+			if CYC_O_dmem_wr = '1' then
+				sn			<= write_bus;
+			elsif CYC_O_dmem_rd = '1' then
+				sn			<= read_bus;
+			elsif CYC_O_icache = '1' then
+				sn			<= icache_bus_access;
+			elsif CYC_O_dcache = '1' then
+				sn			<= dcache_bus_access;
 			end if;
-		when i_cache_bus_access =>
+		when icache_bus_access =>
 			icache_mem_gnt	<= '1';
-			if icache_mem_en = '1' then
-				imem_mem_out_en	<= '1';
-			elsif icache_mem_req = '0' then
-				sn				<= ready;
-			end if;	
-			imem_valid	<= mem_valid;
-		when d_cache_bus_access =>
-			dcache_mem_gnt	<= '1';
-			if dcache_mem_en = '1' then
-				dmem_mem_out_en	<= '1';
-			elsif dcache_mem_req = '0' then
-				sn				<= ready;
-			end if;	
-			dmem_valid	<= mem_valid;
-		when d_bus_access =>
-			if mem_valid = '1' then
-				dmem_ack	<= '1';
-				dmem_valid	<= '1';
+			if CYC_O_icache = '0' then
 				sn			<= ready;
-			end if;
-		when d_bus_finish =>
-			if mem_rdy = '1' then
+			end if;	
+		when dcache_bus_access =>
+			dcache_mem_gnt	<= '1';
+			if CYC_O_dcache = '0' then
+				sn			<= ready;
+			end if;	
+		when write_bus =>
+			dmem_mem_wr_gnt	<= '1';	
+			if CYC_O_dmem_wr = '1' then
+				if bout_rdy = '1' then
+					STB_O_dmem_wr	<= '1';
+				end if;
+			else
+				sn			<= ready;
+			end if;	
+		when read_bus =>
+			dmem_mem_rd_gnt	<= '1';	
+			if bout_rdy = '1' then
+				STB_O_dmem_rd	<= '1';
+				sn				<= read_finish;
+			end if;	
+		when read_finish =>
+			dmem_mem_rd_gnt	<= '1';	
+			if ACK_I = '1' then
 				sn			<= ready;
 			end if;
 		when others =>
@@ -349,45 +460,34 @@ bus_state:
 				
 	end process;	
 
-bus_request:
-	process(clk)
+bus_timeout_counter:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				bus_req 	<= '0';
-			elsif dmem_mem_out_en = '1' or imem_mem_out_en = '1' then
-				bus_req		<= '1';
-			elsif mem_rdy = '1' then
-				bus_req 	<= '0';
-			end if;	
+		if rising_edge(CLK_I) then
+			if bus_idle = '0' then
+				if bus_timeout_cnt /= 0 then
+					bus_timeout_cnt	<= bus_timeout_cnt - 1;
+				else
+					bus_timeout	<= '1';
+				end if;	
+			else
+				bus_timeout_cnt	<= timeout_cnt_t'high;
+				bus_timeout		<= '0';
+			end if;
 		end if;
 	end process;	
 
-bus_out:
-	process(clk)
+bus_err:
+	process(CLK_I)
 	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				mem_dout	<= (others => '0');
-				mem_addr	<= (others => '0');
-				mem_re		<= '0';
-				mem_we		<= (others => '0');
-			elsif dmem_mem_out_en = '1' then
-				if dcache_mem_gnt = '1' then
-					mem_addr	<= dcache_mem_addr;
-					mem_re		<= '1';
-					mem_we		<= (others => '0');
-				else
-					mem_dout	<= dmem_dout;
-					mem_addr	<= dmem_addr;
-					mem_re		<= dmem_re;
-					mem_we		<= dmem_we;
-				end if;
-			elsif imem_mem_out_en = '1' then
-				mem_addr	<= icache_mem_addr;
-				mem_re		<= '1';
-				mem_we		<= (others => '0');
-			end if;	
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cpu_imem_err	<= '0';
+				cpu_dmem_err	<= '0';
+			elsif bus_timeout = '1' then
+				cpu_imem_err	<= icache_mem_gnt;
+				cpu_dmem_err	<= dcache_mem_gnt or dmem_mem_wr_gnt or dmem_mem_rd_gnt;
+			end if;
 		end if;
 	end process;	
 

lib/CPUs/MIPS/src/core/mips_cop.vhd

@@ -82,12 +82,12 @@ architecture Behavioral of cop is
 	signal cop_pipe_ID : cop_pipe_t;
 	signal cop_pipe_EX : cop_pipe_t;
 	
-	function eval_int(ip, im : unsigned) return STD_LOGIC is
+	function eval_int(ip : unsigned) return STD_LOGIC is
 	variable result : STD_LOGIC;
 	begin
 			result := '0';
 			for i in ip'range loop
-				result := result or (ip(i) and im(i));
+				result := result or ip(i);
 			end loop;
 
 			return result;
@@ -128,7 +128,7 @@ begin
 	eflags.Sys		<= events.syscall;
 	eflags.Bp		<= events.break;
 	eflags.RI		<= events.illegal;
-	eflags.Int		<= eval_int(ip, im) and status(0);
+	eflags.Int		<= eval_int(ip) and status(0);
 
 	exception		<= eflags.Ov or eflags.Sys or eflags.Bp or eflags.RI or eflags.IAdEL or eflags.IAdEK or eflags.DAdEL or eflags.DAdES or eflags.Int after 1 ns;
 	
@@ -280,9 +280,9 @@ cop_ip_reg_write:
 			if rst = '1' then
 				ip(1 downto 0) <= (others => '0');
 			elsif ip_reg_we = '1' then
-				ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8);
+				ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8) and im(1 downto 0);
 			end if;	
-			ip(7 downto 2)	<= events.Int;
+			ip(7 downto 2)	<= events.Int and im(7 downto 2);
 		end if;
 	end process;
 
@@ -338,7 +338,7 @@ cop_register_read:
 				reg	:= test_reg;
 
 			when others =>
-				reg	:= X"DEADBEEF";
+				reg	:= (others => '-');
 
 			end case;	
 			dout	<= reg;

lib/CPUs/MIPS/src/core/mips_pipeline.vhd

@@ -35,14 +35,16 @@ entity pipeline is
 		clk			: in  STD_LOGIC;
 		halt		: in  STD_LOGIC;
 		int			: in  unsigned(5 downto 0);
+		imem_err	: in  STD_LOGIC;
 		imem_rdy	: in  STD_LOGIC;
 		imem_en		: out STD_LOGIC;
 		imem_addr	: out word_t;
 		imem_data	: in  word_t;
+		dmem_err	: in  STD_LOGIC;
 		dmem_rdy	: in  STD_LOGIC;
 		dmem_en		: out STD_LOGIC;
-		dmem_re		: out STD_LOGIC;
-		dmem_we		: out unsigned(3 downto 0);
+		dmem_we		: out STD_LOGIC;
+		dmem_be		: out unsigned(3 downto 0);
 		dmem_addr	: out word_t;
 		dmem_din	: in  word_t;
 		dmem_dout	: out word_t
@@ -309,20 +311,22 @@ proc_stage_pc_next:
 			branch_ce	<= '0';
 			cop_ctrl.exc_left		<= '0';
 			if rst = '1' then
-				pc.nxt	<= RESET_VECTOR;
-				pc.last	<= RESET_VECTOR;
-			elsif cop_stat.exc_commit = '1' then
-				pc.nxt	<= cop_stat.exc_vec;
-			elsif sdu.ID_stall = '0' then
-				cop_ctrl.exc_left		<= cop_stat.exc_exit;
-				branch_ce	<= '1';
+				pc.nxt	<= pc.curr;
 				pc.last	<= pc.curr;
-				if ID_stage.ctrl.jump = '1' then
-					pc.nxt	<= ID_stage.jimm32;
-				elsif ID_stage.ctrl.jump_long = '1' then
-					pc.nxt	<= ID_stage.reg_a;
-				else
-					pc.nxt	<= pc.curr + 4;
+			else
+				if cop_stat.exc_commit = '1' then
+					pc.nxt	<= cop_stat.exc_vec;
+				elsif sdu.ID_stall = '0' then
+					cop_ctrl.exc_left		<= cop_stat.exc_exit;
+					branch_ce	<= '1';
+					pc.last	<= pc.curr;
+					if ID_stage.ctrl.jump = '1' then
+						pc.nxt	<= ID_stage.jimm32;
+					elsif ID_stage.ctrl.jump_long = '1' then
+						pc.nxt	<= ID_stage.reg_a;
+					else
+						pc.nxt	<= pc.curr + 4;
+					end if;
 				end if;
 			end if;
 		end if;	
@@ -343,7 +347,7 @@ proc_stage_branch:
 					end if;
 
 				when bc_lez_gtz =>
-					if (EX_stage.ctrl.bc_not xor (bcu_flags.z or bcu_flags.ltz)) = '1' then
+					if (EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz)) = '1' then
 						pc.is_branch <= true;
 					end if;
 
@@ -517,7 +521,7 @@ inst_reg_dual: reg_dual
 --------------------------------------------------------------------------
 	EX_stage.reg_a_rptr		<= extract_rs(EX_stage.IR);
 	EX_stage.reg_b_rptr		<= extract_rt(EX_stage.IR);
-	EX_stage.result			<= mul_result when EX_stage.ctrl.mul_access = '1' else alu_result;
+	EX_stage.result			<= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result;
 	
 proc_stage_ID_EX_1:
 	process(clk_1)
@@ -621,8 +625,8 @@ proc_stage_DMEM_ADDR:
 			end if;
 		end if;
 	end process;
-	dmem_we		<= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
-	dmem_re		<= not EX_stage.ctrl.dmem_we;
+	dmem_be		<= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
+	dmem_we		<= EX_stage.ctrl.dmem_we;
 	dmem_dout	<= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
 	dmem_addr	<= EX_stage.va;
 	cop_din		<= EX_stage.reg_b;
@@ -667,7 +671,7 @@ proc_wptr_mux:
 proc_stage_bcu_op:
 	process(clk_1)
 	begin
-		if rising_edge(clk_1) then
+		if rising_edge(clk_1) and sdu.EX_stall = '0' then
 			bcu_op_a		<= ID_stage.reg_a;
 			bcu_op_b		<= ID_stage.reg_b;
 		end if;

lib/CPUs/MIPS/src/core/mips_top.vhd

@@ -31,17 +31,20 @@ use work.mips_types.all;
 entity mips_top is
 	Port
 	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		int			: in  unsigned (5 downto 0);
-		mem_valid	: in  STD_LOGIC;
-		mem_rdy		: in  STD_LOGIC;
-		mem_en		: out STD_LOGIC;
-		mem_re		: out STD_LOGIC;
-		mem_we		: out unsigned(3 downto 0);
-		mem_din		: in  unsigned (WORD_WIDTH-1 downto 0);
-		mem_dout	: out unsigned (WORD_WIDTH-1 downto 0);
-		mem_addr	: out unsigned (WORD_WIDTH-1 downto 0)
+		debug		: out unsigned(1 downto 0);
+		RST_I		: in  STD_LOGIC;
+		CLK_I		: in  STD_LOGIC;
+		ACK_I		: in  STD_LOGIC;
+		SRDY_I		: in  STD_LOGIC;
+		ADDR_O		: out word_t;
+		DAT_I		: in  word_t;
+		DAT_O		: out word_t;
+		WE_O		: out STD_LOGIC;
+		SEL_O		: out unsigned(3 downto 0);
+		CYC_O		: out STD_LOGIC;
+		STB_O		: out STD_LOGIC;
+		MRDY_O		: out STD_LOGIC;
+		INT			: in  unsigned (5 downto 0)
 	);
 	
 end mips_top;
@@ -49,116 +52,139 @@ end mips_top;
 architecture rtl of mips_top is
 
 	COMPONENT pipeline is
-	Port (
+	Port 
+	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
 		halt		: in  STD_LOGIC;
 		int			: in  unsigned (5 downto 0);
+		imem_err	: in  STD_LOGIC;
 		imem_rdy	: in  STD_LOGIC;
 		imem_en		: out STD_LOGIC;
 		imem_addr	: out word_t;
 		imem_data	: in  word_t;
+		dmem_err	: in  STD_LOGIC;
 		dmem_rdy	: in  STD_LOGIC;
 		dmem_en		: out STD_LOGIC;
-		dmem_re		: out STD_LOGIC;
-		dmem_we		: out unsigned(3 downto 0);
+		dmem_we		: out STD_LOGIC;
+		dmem_be		: out unsigned(3 downto 0);
 		dmem_addr	: out word_t;
 		dmem_din	: in  word_t;
 		dmem_dout	: out word_t
 	);
 	END COMPONENT;
-	signal halt				: std_logic;
+	signal imem_err			: std_logic;
 	signal imem_rdy			: std_logic;
 	signal imem_en			: std_logic;
 	signal imem_addr		: word_t;
 	signal imem_din			: word_t;
+	signal dmem_err			: std_logic;
 	signal dmem_rdy			: std_logic;
 	signal dmem_en			: std_logic;
-	signal dmem_re			: std_logic;
+	signal dmem_we			: std_logic;
 	signal dmem_addr		: word_t;
 	signal dmem_dout		: word_t;
 	signal dmem_din			: word_t;
-	signal dmem_we			: unsigned(3 downto 0);
+	signal dmem_be			: unsigned(3 downto 0);
+
 
 	COMPONENT bui
-	Port
+	GENERIC
 	(
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		ce				: in  STD_LOGIC;
-		cpu_wait		: out STD_LOGIC;
+		icache_size	: natural;
+		dcache_size	: natural
+	);
+	PORT
+	(
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		ADDR_O			: out word_t;
+		DAT_I			: in  word_t;
+		DAT_O			: out word_t;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		cpu_imem_err	: out STD_LOGIC;
 		cpu_imem_rdy	: out STD_LOGIC;
 		cpu_imem_en		: in  STD_LOGIC;
 		cpu_imem_addr	: in  word_t;
 		cpu_imem_din	: out word_t;
+		cpu_dmem_err	: out STD_LOGIC;
 		cpu_dmem_rdy	: out STD_LOGIC;
 		cpu_dmem_en		: in  STD_LOGIC;
-		cpu_dmem_re		: in  STD_LOGIC;
-		cpu_dmem_we		: in  unsigned(3 downto 0);
-		cpu_dmem_addr	: in  word_t;
-		cpu_dmem_din	: out word_t;
+		cpu_dmem_we		: in  STD_LOGIC;
+		cpu_dmem_be		: in  unsigned(3 downto 0);
 		cpu_dmem_dout	: in  word_t;
-		mem_valid		: in  STD_LOGIC;
-		mem_rdy			: in  STD_LOGIC;
-		mem_addr		: out word_t;
-		mem_din			: in  word_t;
-		mem_dout		: out word_t;
-		mem_re			: out STD_LOGIC;
-		mem_we			: out unsigned(3 downto 0);
-		mem_ce			: out STD_LOGIC
+		cpu_dmem_din	: out word_t;
+		cpu_dmem_addr	: in  word_t
 	);
 	END COMPONENT;
 
 begin
 
 -------------------------------------------------------------------
+	debug(0)		<= imem_err;
+	debug(1)		<= dmem_err;
 	
 inst_pipeline: pipeline
 	PORT MAP
 	(
-		rst			=> rst,
-		clk			=> clk,
-		halt		=> halt,
-		int			=> int,
+		rst			=> RST_I,
+		clk			=> CLK_I,
+		halt		=> '0',
+		int			=> INT,
+		imem_err	=> imem_err,
 		imem_rdy	=> imem_rdy,
 		imem_en		=> imem_en,
 		imem_addr	=> imem_addr,
 		imem_data	=> imem_din,
+		dmem_err	=> dmem_err,
 		dmem_rdy	=> dmem_rdy,
 		dmem_en		=> dmem_en,
-		dmem_re		=> dmem_re,
 		dmem_we		=> dmem_we,
+		dmem_be		=> dmem_be,
 		dmem_addr	=> dmem_addr,
 		dmem_din	=> dmem_din,
 		dmem_dout	=> dmem_dout
 	);
 
 inst_bui: bui
+	GENERIC MAP
+	(
+		icache_size	=> 4096,	-- words
+		dcache_size	=> 4096		-- words
+	)
 	PORT MAP
 	(
-		rst				=> rst,
-		clk				=> clk,
-		ce				=> '1',
-		cpu_wait		=> halt,
+		RST_I			=> RST_I,
+		CLK_I			=> CLK_I,
+		ACK_I			=> ACK_I,
+		SRDY_I			=> SRDY_I,
+		ADDR_O			=> ADDR_O,
+		DAT_I			=> DAT_I,
+		DAT_O			=> DAT_O,
+		WE_O			=> WE_O,
+		SEL_O			=> SEL_O,
+		CYC_O			=> CYC_O,
+		STB_O			=> STB_O,
+		MRDY_O			=> MRDY_O,
+		cpu_imem_err	=> imem_err,
 		cpu_imem_rdy	=> imem_rdy,
 		cpu_imem_en		=> imem_en,
 		cpu_imem_addr	=> imem_addr,
 		cpu_imem_din	=> imem_din,
+		cpu_dmem_err	=> dmem_err,
 		cpu_dmem_rdy	=> dmem_rdy,
 		cpu_dmem_en		=> dmem_en,
-		cpu_dmem_re		=> dmem_re,
 		cpu_dmem_we		=> dmem_we,
+		cpu_dmem_be		=> dmem_be,
 		cpu_dmem_addr	=> dmem_addr,
 		cpu_dmem_din	=> dmem_din,
-		cpu_dmem_dout	=> dmem_dout,
-		mem_valid		=> mem_valid,
-		mem_rdy			=> mem_rdy,
-		mem_addr		=> mem_addr,
-		mem_din			=> mem_din,
-		mem_dout		=> mem_dout,
-		mem_re			=> mem_re,
-		mem_we			=> mem_we,
-		mem_ce			=> mem_en
+		cpu_dmem_dout	=> dmem_dout
 	);
 
 end rtl;

lib/CPUs/MIPS/src/core/mips_types.vhd

@@ -159,7 +159,6 @@ package mips_types is
 	end record;
 		
 	type bcu_flags_t is record
-		z				: STD_LOGIC;
 		eq				: STD_LOGIC;
 		ltz				: STD_LOGIC;
 	end record;

lib/CPUs/MIPS/src/mips_muldiv.vhd

@@ -1,83 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The arithmetic logic unit
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.mips_types.all;
-
-entity muldiv is
-	Port 
-	(
-		rst			: in  std_logic;
-		clk			: in  std_logic;
-		din_vld_hi	: in  std_logic;
-		din_vld_lo	: in  std_logic;
-		din_hi		: in  word_t;
-		din_lo		: in  word_t;
-		hilo_sel	: in  std_logic;
-		dout		: out word_t
-	);
-end muldiv;
-
-architecture Behavioral of muldiv is
-
-	signal reg_hi, reg_lo : word_t;
-	
---------------------------------------------------------------------------
-begin
-
---------------------------------------------------------------------------
-proc_reg_out:
-	process(hilo_sel, reg_hi, reg_lo)
-	begin
-		if hilo_sel = '1' then
-			dout <= reg_hi;
-		else	
-			dout <= reg_lo;
-		end if;
-	end process;	
-	
-proc_reg_in:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				reg_hi <= (others => '0');
-				reg_lo <= (others => '0');
-			elsif din_vld_hi = '1' then
-				if hilo_sel = '1' then
-					reg_hi <= din_hi;
-				else
-					reg_lo <= din_hi;
-				end if;
-			end if;
-			if din_vld_lo = '1' then
-				reg_lo <= din_lo;
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
-end Behavioral;

lib/CPUs/MIPS/src/tb_eval_muldiv.vhd

@@ -1,156 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: Testbench for JCPU
---            also writes 'opc.lst' for JASM-assembler
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-use work.mips_types.all;
-use work.mips_instr.all;
-
-ENTITY tb_eval_muldiv IS
-END tb_eval_muldiv;
-
-ARCHITECTURE behavior OF tb_eval_muldiv IS 
-
-	constant CLK_PERIOD : time := 10 ns;
-	signal rst 			: std_logic := '1';
-	signal clk 			: std_logic := '1';
-	signal ce  			: std_logic := '0';
-	signal mul_divn		: std_logic := '1';
-	signal op_valid		: std_logic := '0';
-	signal op1_in		: word_t := (others => '-');
-	signal op2_in		: word_t := (others => '-');
-	signal result		: unsigned (2*word_t'length-1 downto 0);
-	signal res_valid 	: std_logic;
-	signal busy 		: std_logic;
-	signal result_reg	: unsigned (2*word_t'length-1 downto 0);
-	subtype pp_t is unsigned (39 downto 0);
-	
-	signal pp0, pp1, pp2, pp3 : pp_t;
-	
-	signal signed_mul	: std_logic := '1';
-	signal sign1 		: std_logic;
-	signal sign2 		: std_logic;
-	signal cy			: std_logic;
-	
-BEGIN
-	
-	sign1	<= signed_mul and op1_in(op1_in'left);
-	sign2	<= signed_mul and op2_in(op1_in'left);
-	cy 		<= sign1;
-	
-	pp0 <= op1_in * op2_in(7 downto 0);
-	pp1 <= op1_in * op2_in(15 downto 8);
-	pp2 <= op1_in * op2_in(23 downto 16);
-	pp3 <= op1_in * op2_in(31 downto 24);
-	
-	result	<= ((63 downto 40 => '0') & pp0)
-			+ ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0'))
-			+ ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0'))
-			+ (pp3 & (23 downto 0 => '0'));
-		
-	result_reg	<= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000"));
-	
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		wait until rising_edge(clk);
-		rst <= '0';
-		wait for 10*CLK_PERIOD;
-	
-		wait until rising_edge(clk);
-		ce <= '1';
-
-		wait for 10*CLK_PERIOD;
-		op1_in		<= X"FFFF_FFFA"; -- (-6)
-		op2_in		<= X"0000_0005"; -- (+5)
-		op_valid	<= '1';
-		wait until rising_edge(clk);
-		op_valid	<= '0';
-		
-		wait for 10*CLK_PERIOD;
-		op1_in		<= X"0000_0006"; -- (+6)
-		op2_in		<= X"FFFF_FFFB"; -- (-5)
-		op_valid	<= '1';
-		wait until rising_edge(clk);
-		op_valid	<= '0';
-		
-		wait for 10*CLK_PERIOD;
-		op1_in		<= X"1234_5678";
-		op2_in		<= X"8765_4321";
-		op_valid	<= '1';
-		wait until rising_edge(clk);
-		op_valid	<= '0';
-		
-		wait for 10*CLK_PERIOD;
-		op1_in		<= X"8765_4321";
-		op2_in		<= X"1234_5678";
-		op_valid	<= '1';
-		wait until rising_edge(clk);
-		op_valid	<= '0';
-
-		wait for 10*CLK_PERIOD;
-		op1_in		<= X"1234_5678";
-		op2_in		<= X"1234_5678";
-		op_valid	<= '1';
-		wait until rising_edge(clk);
-		op_valid	<= '0';
-
-		wait for 10*CLK_PERIOD;
-		op1_in		<= X"8765_4321";
-		op2_in		<= X"8765_4321";
-		op_valid	<= '1';
-		wait until rising_edge(clk);
-		op_valid	<= '0';
-
-		wait for 10*CLK_PERIOD;
-		op1_in		<= X"789A_BCDE";
-		op2_in		<= X"8765_4321";
-		op_valid	<= '1';
-		wait until rising_edge(clk);
-		op_valid	<= '0';
-
-		wait for 10*CLK_PERIOD;
-		op1_in		<= X"8765_4321";
-		op2_in		<= X"789A_BCDE";
-		op_valid	<= '1';
-		wait until rising_edge(clk);
-		op_valid	<= '0';
-
-		wait; 
-	
-	end process;
-	
-END;

lib/CPUs/MIPS/syn/ise101/mips_top.prj

@@ -0,0 +1,20 @@
+vhdl work "../../src/core/mips_types.vhd"
+vhdl work "../../../../misc/dpram_2w2r.vhd"
+vhdl work "../../../../misc/dpram_1w1r_dist.vhd"
+vhdl work "../../../../misc/dpram_1w1r.vhd"
+vhdl work "../../../../FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../src/core/mips_instr.vhd"
+vhdl work "../../../../FIFO/src/fifo_sync_dist.vhd"
+vhdl work "../../src/core/mips_shifter.vhd"
+vhdl work "../../src/core/mips_reg.vhd"
+vhdl work "../../src/core/mips_muldiv.vhd"
+vhdl work "../../src/core/mips_idecode_rom.vhd"
+vhdl work "../../src/core/mips_cop.vhd"
+vhdl work "../../src/core/mips_bcu.vhd"
+vhdl work "../../src/core/mips_alu.vhd"
+vhdl work "../../src/core/icache.vhd"
+vhdl work "../../src/core/dcache.vhd"
+vhdl work "../../src/core/mips_pipeline.vhd"
+vhdl work "../../src/core/mips_bui.vhd"
+vhdl work "../../src/core/mips_top.vhd"

lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj

@@ -0,0 +1,20 @@
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"

lib/CPUs/MIPS/tools/Makefile

@@ -0,0 +1,8 @@
+all: ramgen romgen
+
+ramgen: src/ramgen.c
+	gcc -o ./ramgen.exe src/ramgen.c
+	
+romgen: src/romgen.c
+	gcc -o ./romgen.exe src/romgen.c
+	

lib/CPUs/MIPS/tools/make.sh

@@ -0,0 +1,51 @@
+#!/bin/sh
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: rom-file generation for cpu_core
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+# $Header: /tmp/cvsroot/VHDL/lib/CPUs/MIPS/tools/make.sh,v 1.1 2008-08-25 08:29:55 Jens Exp $
+# ----------------------------------------------------------------------
+TARGET=$2
+DSTDIR=$1
+
+JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
+
+$JASM_HOME/jasm.rb $TARGET.jsm
+
+irom_tcl_snippet="$TARGET.irom.tcl.snip"
+irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
+irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
+xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
+xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
+xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
+
+$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
+$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
+
+$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
+$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
+
+cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
+cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
+$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
+
+rm -f *.snip

lib/FIFO/src/async_fifo_ctrl.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.2 2008-10-25 11:21:47 Jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;
@@ -80,7 +80,7 @@ architecture Behavioral of async_fifo_ctrl is
 begin
 
 	ptr_w		<= bcnt_w(addr_width-1 downto 0);
-	ptr_r		<= bcnt_r(addr_width-1 downto 0);
+	ptr_r		<= bnxt_r(addr_width-1 downto 0);
 	winc		<= we and (not write_inhibit);
 	rinc		<= re and (not read_inhibit);
 	fifo_full	<= write_inhibit;

lib/FIFO/src/fifo_async.vhd

@@ -26,14 +26,13 @@ LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 
-use work.vga_types.all;
-
-entity linefifo is
+entity fifo_async is
 	Generic
 	(
-		depth					: natural := 64;
-		almost_full_thresh		: natural := 60;
-		almost_empty_thresh		: natural := 4
+		addr_width			: natural := 4;
+		data_width			: natural := 8;
+		almost_full_thresh	: integer := 12;
+		almost_empty_thresh	: integer := 4
 	);
 	Port
 	(
@@ -46,19 +45,16 @@ entity linefifo is
 		fifo_empty	: out STD_LOGIC;
 		fifo_afull	: out STD_LOGIC;
 		fifo_aempty	: out STD_LOGIC;
-		color_w		: in  color_t;
-		color_r		: out color_t
+		data_w		: in  unsigned (data_width-1 downto 0);
+		data_r		: out unsigned (data_width-1 downto 0)
 	);
-end linefifo;
+end fifo_async;
 
-architecture Behavioral of linefifo is
-	
-	constant data_width : integer := 8;
-	constant addr_width : integer := NextExpBaseTwo(depth);
+architecture Behavioral of fifo_async is
 	
 	signal buf_we_w		: STD_LOGIC;
-	signal ptr_w		: unsigned (ADDR_WIDTH-1 downto 0);
-	signal ptr_r		: unsigned (ADDR_WIDTH-1 downto 0);
+	signal ptr_w		: unsigned (addr_width-1 downto 0);
+	signal ptr_r		: unsigned (addr_width-1 downto 0);
 	signal full			: STD_LOGIC;
 	signal empty		: STD_LOGIC;
 	signal almost_full	: STD_LOGIC;
@@ -72,29 +68,7 @@ begin
 	fifo_afull <= almost_full;
 	fifo_aempty <= almost_empty;
 	
-gen_line:
-	for c in color_range_t generate
-	begin
-		inst_dpram: entity work.dpram
-		GENERIC MAP 
-		(
-			addr_width	=> addr_width,
-			data_width	=> data_width
-		)
-		PORT MAP(
-			clka		=> clk_w,
-			clkb		=> clk_r,
-			en_a		=> '1',
-			en_b		=> '1',
-			we_a		=> buf_we_w,
-			addr_a		=> ptr_w,
-			addr_b		=> ptr_r,
-			din_a		=> color_w(c),
-			dout_b		=> color_r(c)
-		);
-	end generate;	
-
-	inst_fifo_ctrl: entity work.async_fifo_ctrl
+inst_fifo_ctrl: entity work.async_fifo_ctrl
 	GENERIC MAP
 	(
 		addr_width			=> ADDR_WIDTH,
@@ -117,5 +91,23 @@ gen_line:
 
 	);
 
+inst_dpram_1w1r: entity work.dpram_1w1r
+	GENERIC MAP
+	(
+		addr_width	=> addr_width,
+		data_width	=> data_width
+	)
+	PORT MAP(
+		clka		=> clk_w,
+		clkb		=> clk_r,
+		en_a		=> '1',
+		en_b		=> '1',
+		we_a		=> buf_we_w,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> data_w,
+		dout_b		=> data_r
+	);
+
 end Behavioral;
 

lib/FIFO/src/fifo_sync.vhd

@@ -0,0 +1,119 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.fifo_ctrl_pkg.all;
+
+entity fifo_sync is
+	Generic 
+	(
+		addr_width			: natural := 4;
+		data_width			: natural := 8;
+		almost_full_thresh	: integer := 12;
+		almost_empty_thresh	: integer := 4
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		fifo_full	: out STD_LOGIC;
+		fifo_empty	: out STD_LOGIC;
+		fifo_afull	: out STD_LOGIC;
+		fifo_aempty	: out STD_LOGIC;
+		data_w		: in  unsigned (data_width-1 downto 0);
+		data_r		: out unsigned (data_width-1 downto 0)
+	);
+end fifo_sync;
+
+architecture Behavioral of fifo_sync is
+	
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
+	signal ptr_w		: unsigned (addr_width-1 downto 0);
+	signal ptr_r		: unsigned (addr_width-1 downto 0);
+	signal full			: STD_LOGIC;
+	signal empty		: STD_LOGIC;
+	signal almost_full	: STD_LOGIC;
+	signal almost_empty	: STD_LOGIC;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
+	
+begin
+
+	mem_wr_en	<= not full;
+	mem_rd_en	<= not pre_empty;
+	fifo_full	<= full;
+	fifo_empty	<= empty;
+	fifo_afull	<= almost_full;
+	fifo_aempty	<= almost_empty;
+
+inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> addr_width,
+		almost_full_thresh	=> almost_full_thresh,
+		almost_empty_thresh	=> almost_empty_thresh
+	)
+	PORT MAP
+	(
+		rst				=>	rst,
+		clk				=>	clk,
+		we				=>	we,
+		re				=>	re,
+		ptr_w			=>	ptr_w,
+		ptr_r			=>	ptr_r,
+		fifo_full		=>	full,
+		fifo_empty		=>	empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
+		fifo_afull		=>	almost_full,
+		fifo_aempty		=>	almost_empty
+
+	);
+
+inst_dpram_1w1r: entity work.dpram_1w1r
+	GENERIC MAP
+	(
+		addr_width	=> addr_width,
+		data_width	=> data_width
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> mem_wr_en,
+		en_b		=> mem_rd_en,
+		we_a		=> we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> data_w,
+		dout_b		=> data_r
+	);
+	
+end Behavioral;
+

lib/FIFO/src/fifo_sync_dist.vhd

@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.fifo_ctrl_pkg.all;
+
+entity fifo_sync_dist is
+	Generic (
+		addr_width			: natural := 4;
+		data_width			: natural := 8;
+		almost_full_thresh	: integer := 12;
+		almost_empty_thresh	: integer := 4
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		fifo_full	: out STD_LOGIC;
+		fifo_empty	: out STD_LOGIC;
+		fifo_afull	: out STD_LOGIC;
+		fifo_aempty	: out STD_LOGIC;
+		data_w		: in  unsigned (data_width-1 downto 0);
+		data_r		: out unsigned (data_width-1 downto 0)
+	);
+end fifo_sync_dist;
+
+architecture Behavioral of fifo_sync_dist is
+	
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
+	signal ptr_w		: unsigned (addr_width-1 downto 0);
+	signal ptr_r		: unsigned (addr_width-1 downto 0);
+	signal full			: STD_LOGIC;
+	signal empty		: STD_LOGIC;
+	signal almost_full	: STD_LOGIC;
+	signal almost_empty	: STD_LOGIC;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
+	
+begin
+
+	mem_wr_en	<= not full;
+	mem_rd_en	<= not pre_empty;
+	fifo_full	<= full;
+	fifo_empty	<= empty;
+	fifo_afull	<= almost_full;
+	fifo_aempty	<= almost_empty;
+
+	inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> addr_width,
+		almost_full_thresh	=> almost_full_thresh,
+		almost_empty_thresh	=> almost_empty_thresh
+	)
+	PORT MAP
+	(
+		rst				=>	rst,
+		clk				=>	clk,
+		we				=>	we,
+		re				=>	re,
+		ptr_w			=>	ptr_w,
+		ptr_r			=>	ptr_r,
+		fifo_full		=>	full,
+		fifo_empty		=>	empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
+		fifo_afull		=>	almost_full,
+		fifo_aempty		=>	almost_empty
+
+	);
+
+	inst_dpram_1w1r: entity work.dpram_1w1r_dist
+	GENERIC MAP (
+		addr_width	=> addr_width,
+		data_width	=> data_width
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> mem_wr_en,
+		en_b		=> mem_rd_en,
+		we_a		=> we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> data_w,
+		dout_b		=> data_r
+	);
+	
+end Behavioral;
+

lib/FIFO/src/sync_fifo_ctrl.vhd

@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.2 2008-10-12 18:04:36 Jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;
@@ -42,6 +42,8 @@ entity sync_fifo_ctrl is
 		re				: in  STD_LOGIC;
 		ptr_w			: out unsigned (addr_width-1 downto 0);
 		ptr_r			: out unsigned (addr_width-1 downto 0);
+		fifo_pre_full	: out STD_LOGIC;
+		fifo_pre_empty	: out STD_LOGIC;
 		fifo_full		: out STD_LOGIC;
 		fifo_empty		: out STD_LOGIC;
 		fifo_afull		: out STD_LOGIC;
@@ -61,11 +63,13 @@ architecture Behavioral of sync_fifo_ctrl is
 	
 begin
 
-	read <= '1' when re = '1' and empty = '0' else '0';
-	write <= '1' when we = '1' and full = '0' else '0';
+	read	<= re and not empty;
+	write	<= we and not full;
 
-	fifo_full <= full;
-	fifo_empty <= empty;
+	fifo_full		<= full;
+	fifo_empty		<= empty;
+	fifo_pre_full	<= pre_full;
+	fifo_pre_empty	<= pre_empty;
 
 
 proc_diff_gen:
@@ -131,14 +135,14 @@ proc_empty_reg:
 	end process;
 	
 proc_status_w:
-	process(was_write, pW_next, pR_next, pW, pR, we, re)
+	process(was_write, pW_next, pR_next, pW, pR, write, read)
 	begin
-		if (pW_next = pR) and (we = '1' or was_write = '1') then
+		if (pW_next = pR) and (write = '1' or was_write = '1') then
 			pre_full <= '1';
 		else
 			pre_full <= '0';
 		end if;
-		if (pR_next = pW) and (re = '1' or was_write = '0') then
+		if (pR_next = pW) and (read = '1' or was_write = '0') then
 			pre_empty <= '1';
 		else
 			pre_empty <= '0';
@@ -160,36 +164,36 @@ proc_flag_write:
 	end process;
 	
 proc_ptr_w:
-	process(rst, clk, pW, we, full)
+	process(rst, clk, pW, write, full)
 	begin
 		if rst = '1' then
 			pW <= to_unsigned(0, addr_width);
 			pW_next <= to_unsigned(0, addr_width);
 		elsif rising_edge(clk) then
-			if we = '1' then 
+			if write = '1' then 
 				pW <= pW_next;
 			end if;
 		end if;
 		pW_next <= pW;
-		if we = '1' and full = '0' then 
+		if write = '1' then 
 			pW_next <= pW + 1;
 		end if;
 		ptr_w		<= pW;
 	end process;
 
 proc_ptr_r:
-	process(rst, clk, pR_next, pR, re, empty)
+	process(rst, clk, pR_next, pR, read, empty)
 	begin
 		if rst = '1' then
 			pR <= to_unsigned(0, addr_width);
 			pR_next <= to_unsigned(0, addr_width);
 		elsif rising_edge(clk) then
-			if re = '1' then
+			if read = '1' then
 				pR <= pR_next;
 			end if;	
 		end if;
 		pR_next	<= pR;
-		if re = '1' and empty = '0' then
+		if read = '1' then
 			pR_next	<= pR + 1;
 		end if;
 		ptr_r		<= pR_next;

lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd

@@ -41,9 +41,11 @@ entity ddr_phy is
 		u_tag_wr		: out user_tag_t;
 		read_clk		: in  STD_LOGIC;
 		phy_ctrl		: in  phy_ctrl_t;
-		part_ctrl		: in part_ctrl_t;
-		sdr_data_w		: in unsigned(SDR_DATA_WIDTH-1 downto 0);
-		sdr_dm			: in unsigned(SDR_DM_WIDTH-1 downto 0);
+		part_ctrl		: in  part_ctrl_t;
+		sdr_data_w		: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
+		sdr_dm_wr_in	: in  unsigned(SDR_DM_WIDTH-1 downto 0);
+		sdr_dm_rd_in	: in  unsigned(SDR_DM_WIDTH-1 downto 0);
+		sdr_dm_rd_out	: out unsigned(SDR_DM_WIDTH-1 downto 0);
 		sdr_data_r		: out unsigned(SDR_DATA_WIDTH-1 downto 0);
 		sdr_data_vld	: out STD_LOGIC;
 		sdr_data_req_w	: out STD_LOGIC;
@@ -81,6 +83,9 @@ architecture tech of ddr_phy is
 	type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
 	signal u_tag_pipe : u_tag_array_t;
 	
+	type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0);
+	signal dm_out_pipe : dm_out_array_t;
+
 begin
 
 ------------------------------------------------------------------------------------------------------------------------------------------------
@@ -97,6 +102,19 @@ utag_pipe:
 		end if;
 	end process;
 
+dmout_pipe:
+	process(sys_rst, sys_clk0)
+	begin
+		if rising_edge(sys_clk0) then
+			for i in dm_out_pipe'length-1 downto 1 loop
+				dm_out_pipe(i) <= dm_out_pipe(i-1);
+			end loop;	
+			if phy_ctrl.utag_we = '1' then
+				dm_out_pipe(0) <= sdr_dm_rd_in;
+			end if;	
+		end if;
+	end process;
+
 WE_REGISTER:
 	process(sys_rst, sys_clk0)
 	begin
@@ -221,8 +239,8 @@ gen_ddr_dm_out:
 			Q	=> part_dm(n),							-- 1-bit DDR output
 			C	=> sys_clk270,							-- 1-bit clock input
 			CE	=> '1',									-- 1-bit clock enable input
-			D1	=> sdr_dm(n + DDR_DM_WIDTH),		-- 1-bit data input (positive edge)
-			D2	=> sdr_dm(n),						-- 1-bit data input (negative edge)
+			D1	=> sdr_dm_wr_in(n + DDR_DM_WIDTH),		-- 1-bit data input (positive edge)
+			D2	=> sdr_dm_wr_in(n),						-- 1-bit data input (negative edge)
 			R	=> '0',									-- 1-bit reset input
 			S	=> '0' 									-- 1-bit set input
 		);
@@ -349,10 +367,11 @@ misc_flags_and_data_out:
 		elsif rising_edge(sys_clk0) then
 			sdr_data_r		<= data_reg_r;
 			if p(3) = '1' then
-				u_tag_rd	<= u_tag_pipe(4);
+				u_tag_rd		<= u_tag_pipe(4);
+				sdr_dm_rd_out	<= dm_out_pipe(4);
 			end if;	
 			if phy_ctrl.we = '1' then
-				u_tag_wr	<= u_tag_pipe(0);
+				u_tag_wr		<= u_tag_pipe(0);
 			end if;	
 			sdr_data_req_w	<= phy_ctrl.we;
 			sdr_data_req_r	<= phy_ctrl.re;

lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd

@@ -87,12 +87,15 @@ architecture struct of sdram_ctrl_frontend is
 	signal u_cmd_we			: std_logic;
 	signal u_busy			: std_logic;
 	signal u_data_w			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal u_dm				: unsigned(SDR_DM_WIDTH-1 downto 0);
+	signal u_dm_wr_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
+	signal u_dm_rd_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
+	signal u_dm_rd_out		: unsigned(SDR_DM_WIDTH-1 downto 0);
 	signal u_data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
 	signal u_data_vld		: std_logic;
 	signal u_req_wr			: std_logic;
+	signal rdy				: std_logic;
 
-	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
+	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + SDR_DM_WIDTH;
 	signal cat_fifo_din				: unsigned(CAT_FIFO_WIDTH-1 downto 0);
 	signal cat_fifo_dout			: unsigned(CAT_FIFO_WIDTH-1 downto 0);
 	signal cat_fifo_re				: std_logic;
@@ -111,8 +114,8 @@ architecture struct of sdram_ctrl_frontend is
 --	signal write_fifo_almost_full	: std_logic;
 --	signal write_fifo_almost_empty	: std_logic;
 
-	signal read_fifo_din			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal read_fifo_dout			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal read_fifo_din			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
+	signal read_fifo_dout			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
 	signal read_fifo_re				: std_logic;
 	signal read_fifo_we				: std_logic;
 	signal read_fifo_full			: std_logic;
@@ -122,14 +125,22 @@ architecture struct of sdram_ctrl_frontend is
 
 	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
 	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH);
+	alias dm_rd_fifo_in is cat_fifo_din(SDR_DM_WIDTH-1 downto 0);
 	alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
 	alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH);
+	alias dm_rd_fifo_out is cat_fifo_dout(SDR_DM_WIDTH-1 downto 0);
+
 	alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH);
 	alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0);
 	alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH);
 	alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0);
+
+	alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-SDR_DM_WIDTH);
+	alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-SDR_DM_WIDTH-1 downto 0);
+	alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-SDR_DM_WIDTH);
+	alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-SDR_DM_WIDTH-1 downto 0);
 	
 begin 
    
@@ -180,7 +191,7 @@ begin
 	GENERIC MAP
 	(
 		addr_width	=> fifo_depth,
-		data_width	=> 2*DDR_DATA_WIDTH
+		data_width	=> 2*DDR_DATA_WIDTH + SDR_DM_WIDTH
 	)
 	PORT MAP
 	(
@@ -227,7 +238,9 @@ begin
 		u_cmd_we			=> u_cmd_we,
 		u_data_wr			=> u_data_w,
 		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm,
+		u_dm_wr_in			=> u_dm_wr_in,
+		u_dm_rd_in			=> u_dm_rd_in,
+		u_dm_rd_out			=> u_dm_rd_out,
 		
 		-- SDRAM signals
 		sd_clk_p			=> sd_clk_p,
@@ -248,22 +261,24 @@ begin
 ------------------------------------------------------------------------------------------
 	sys_rst_out			<= rst_out;
 	sys_clk_out			<= clk_out;
-	
-	busy				<= cat_fifo_full or write_fifo_full or read_fifo_full;
-	write_fifo_we 		<= en and not r_wn and not write_fifo_full and not cat_fifo_full and not read_fifo_full;
+	busy				<= not rdy;
+	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full);
+	write_fifo_we 		<= en and not r_wn and rdy;
 	write_fifo_data_in	<= din;
 	write_fifo_dm_in	<= not be;
-	cat_fifo_we			<= en and not cat_fifo_full and not write_fifo_full and not read_fifo_full;
+	cat_fifo_we			<= en and rdy;
 	cmd_fifo_in			<= UCMD_WRITE when r_wn = '0' else UCMD_READ;
 	addr_fifo_in		<= addr;
+	dm_rd_fifo_in		<= not be;
 	tag_fifo_in			<= (others=>'0');
-	dout				<= read_fifo_dout;
+	dout				<= read_fifo_data_out;
 	dout_vld			<= not read_fifo_empty;
 	
 	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
 	u_cmd				<= cmd_fifo_out;
 	u_addr				<= addr_fifo_out;
-	u_dm				<= write_fifo_dm_out;
+	u_dm_rd_in			<= dm_rd_fifo_out;
+	u_dm_wr_in			<= write_fifo_dm_out;
 	u_tag_in			<= tag_fifo_out;
 	
 	write_fifo_re		<= u_req_wr and (not write_fifo_empty);
@@ -271,7 +286,8 @@ begin
 	u_data_w			<= write_fifo_data_out;
 	read_fifo_re 		<= (not read_fifo_empty) and dout_re;
 	read_fifo_we		<= u_data_vld;
-	read_fifo_din		<= u_data_r;	
+	read_fifo_data_in	<= u_data_r;	
+	read_fifo_dm_in		<= u_dm_rd_out;
 
 	
 end architecture struct;

lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd

@@ -39,8 +39,8 @@ entity sdram_ctrl_top is
 	(
 		sys_rst_in			: in  STD_LOGIC;
 		sys_clk_in			: in  STD_LOGIC;
-		sys_rst_out			: out  STD_LOGIC;
-		sys_clk_out			: out  STD_LOGIC;
+		sys_rst_out			: out STD_LOGIC;
+		sys_clk_out			: out STD_LOGIC;
 		sys_clk_fb			: in  STD_LOGIC;
 		
 		-- User interface
@@ -54,8 +54,10 @@ entity sdram_ctrl_top is
 		u_addr				: in  user_addr_t;
 		u_cmd				: in  user_cmd_t;
 		u_cmd_we			: in  STD_LOGIC;
-		u_data_wr			: in unsigned(SDR_DATA_WIDTH-1 downto 0);
-		u_dm				: in unsigned(SDR_DM_WIDTH-1 downto 0);
+		u_data_wr			: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
+		u_dm_wr_in			: in  unsigned(SDR_DM_WIDTH-1 downto 0);
+		u_dm_rd_in			: in  unsigned(SDR_DM_WIDTH-1 downto 0);
+		u_dm_rd_out			: out unsigned(SDR_DM_WIDTH-1 downto 0);
 		u_data_rd			: out unsigned(SDR_DATA_WIDTH-1 downto 0);
 		
 		-- SDRAM signals
@@ -68,7 +70,7 @@ entity sdram_ctrl_top is
 		sd_we_n				: out  STD_LOGIC;
 		sd_addr				: out  sdr_addr_t;
 		sd_ba				: out  sdr_ba_t;
-		sd_dm				: out unsigned(DDR_DM_WIDTH-1 downto 0);
+		sd_dm				: out  unsigned(DDR_DM_WIDTH-1 downto 0);
 		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
 		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
 		
@@ -264,7 +266,9 @@ begin
 		sdr_data_req_w	=> u_data_req_w,
 		sdr_data_req_r	=> u_data_req_r,
 		sdr_data_w		=> u_data_wr,
-		sdr_dm			=> u_dm,
+		sdr_dm_wr_in	=> u_dm_wr_in,
+		sdr_dm_rd_in	=> u_dm_rd_in,
+		sdr_dm_rd_out	=> u_dm_rd_out,
 		sdr_data_r		=> u_data_rd,
 		sdr_data_vld	=> u_data_vld,
 		part_clk_p		=> sd_clk_p,

lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd

@@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is
 	signal u_busy			: std_logic;
 	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
 	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_data_vld		: std_logic;
 	signal u_req_wr			: std_logic;
@@ -121,7 +123,9 @@ begin
 		u_cmd_we			=> u_cmd_we,
 		u_data_wr			=> u_data_w,
 		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm,
+		u_dm_wr_in			=> u_dm,
+		u_dm_rd_in			=> u_dm_rd_in,
+		u_dm_rd_out			=> u_dm_rd_out,
 		
 		-- SDRAM signals
 		sd_clk_p			=> part_clk_p,

lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd

@@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl_fifo is
 	signal u_busy			: std_logic;
 	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
 	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_data_vld		: std_logic;
 	signal u_req_wr			: std_logic;
@@ -205,7 +207,9 @@ begin
 		u_cmd_we			=> u_cmd_we,
 		u_data_wr			=> u_data_w,
 		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm,
+		u_dm_wr_in			=> u_dm,
+		u_dm_rd_in			=> u_dm_rd_in,
+		u_dm_rd_out			=> u_dm_rd_out,
 		
 		-- SDRAM signals
 		sd_clk_p			=> part_clk_p,

lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd

@@ -67,6 +67,8 @@ architecture struct of tb_sdr_ctrl is
 	signal u_busy			: std_logic;
 	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
 	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_data_vld		: std_logic;
 	signal u_req_wr			: std_logic;
@@ -124,7 +126,9 @@ begin
 		u_cmd_we			=> u_cmd_we,
 		u_data_wr			=> u_data_w,
 		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm,
+		u_dm_wr_in			=> u_dm,
+		u_dm_rd_in			=> u_dm_rd_in,
+		u_dm_rd_out			=> u_dm_rd_out,
 		
 		-- SDRAM signals
 		sd_clk_p			=> part_clk_p,

lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd

@@ -67,6 +67,8 @@ architecture struct of tb_sdr_ctrl is
 	signal u_busy			: std_logic;
 	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
 	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_data_vld		: std_logic;
 	signal u_req_wr			: std_logic;
@@ -124,7 +126,9 @@ begin
 		u_cmd_we			=> u_cmd_we,
 		u_data_wr			=> u_data_w,
 		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm,
+		u_dm_wr_in			=> u_dm,
+		u_dm_rd_in			=> u_dm_rd_in,
+		u_dm_rd_out			=> u_dm_rd_out,
 		
 		-- SDRAM signals
 		sd_clk_p			=> part_clk_p,

lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd

@@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is
 	signal u_busy			: std_logic;
 	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
 	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_data_vld		: std_logic;
 	signal u_req_wr			: std_logic;
@@ -121,7 +123,9 @@ begin
 		u_cmd_we			=> u_cmd_we,
 		u_data_wr			=> u_data_w,
 		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm,
+		u_dm_wr_in			=> u_dm,
+		u_dm_rd_in			=> u_dm_rd_in,
+		u_dm_rd_out			=> u_dm_rd_out,
 		
 		-- SDRAM signals
 		sd_clk_p			=> part_clk_p,

lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd

@@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is
 	signal u_busy			: std_logic;
 	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
 	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
 	signal u_data_vld		: std_logic;
 	signal u_req_wr			: std_logic;
@@ -122,7 +124,9 @@ begin
 		u_cmd_we			=> u_cmd_we,
 		u_data_wr			=> u_data_w,
 		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm,
+		u_dm_wr_in			=> u_dm,
+		u_dm_rd_in			=> u_dm_rd_in,
+		u_dm_rd_out			=> u_dm_rd_out,
 		
 		-- SDRAM signals
 		sd_clk_p			=> part_clk_p,

lib/SDRAM/ddr_sdr_v1_5/ise9/sdram_ctrl_top.prj

@@ -0,0 +1,13 @@
+vhdl work "../../../misc/utils_pkg.vhd"
+vhdl work "../src/sdram_config.vhd"
+vhdl work "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../src/sdram_types.vhd"
+vhdl work "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../FIFO/src/dpram.vhd"
+vhdl work "../src/sdram_ctrl.vhd"
+vhdl work "../src/sdram_cmd.vhd"
+vhdl work "../src/reset_virtex4.vhd"
+vhdl work "../src/fifo_sync.vhd"
+vhdl work "../src/ddr_phy_virtex4.vhd"
+vhdl work "../src/clockgen_virtex4.vhd"
+vhdl work "../src/sdram_ctrl_top.vhd"

lib/SDRAM/ddr_sdr_v1_5/sim/compile_simprim.do

@@ -0,0 +1,6 @@
+vlib simprim
+
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd

lib/SDRAM/ddr_sdr_v1_5/sim/compile_unisim.do

@@ -0,0 +1,6 @@
+vlib unisim
+
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo

@@ -0,0 +1,28 @@
+## NOTE:  Do not edit this file.
+##
+
+vlib work
+vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_config.vhd"
+vcom -explicit  -93 "../src/sdram_types.vhd"
+vcom -explicit  -93 "../src/reset_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_cmd.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_frontend64_wb.vhd"
+vcom -explicit  -93 "../src/mt46v16m16.vhd"
+vcom -explicit  -93 "../src/tb_sdram_ctrl_frontend64_wb.vhd"
+
+#restart -force
+vsim -t 1ps   -lib work tb_sdram_ctrl_frontend64_wb
+do {tb_sdram_ctrl_frontend64_wb.wdo}
+view wave
+view structure
+view signals
+run 200us

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo

@@ -0,0 +1,50 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/rst_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/cyc_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/stb_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/we_o
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sel_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/ack_i
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/mrdy_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt
+add wave -noupdate -divider Part
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cs_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_we_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_ras_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cas_n
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_ba
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dm
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dqs
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {34438503 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {210 us}

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo

@@ -0,0 +1,28 @@
+## NOTE:  Do not edit this file.
+##
+
+vlib work
+vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_config.vhd"
+vcom -explicit  -93 "../src/sdram_types.vhd"
+vcom -explicit  -93 "../src/reset_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_cmd.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_frontend_wb.vhd"
+vcom -explicit  -93 "../src/mt46v16m16.vhd"
+vcom -explicit  -93 "../src/tb_sdram_ctrl_frontend_wb.vhd"
+
+#restart -force
+vsim -t 1ps   -lib work tb_sdram_ctrl_frontend_wb
+do {tb_sdram_ctrl_frontend_wb.wdo}
+view wave
+view structure
+view signals
+run 200us

lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo

@@ -0,0 +1,50 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt
+add wave -noupdate -divider Part
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {34438503 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {210 us}

lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd

@@ -0,0 +1,370 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: DDR physical layer (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity ddr_phy is
+	Port (
+		sys_rst			: in  STD_LOGIC;
+		sys_clk0		: in  STD_LOGIC;
+		sys_clk270		: in  STD_LOGIC;
+		u_tag_in		: in  user_tag_t;
+		u_tag_rd		: out user_tag_t;
+		u_tag_wr		: out user_tag_t;
+		read_clk		: in  STD_LOGIC;
+		phy_ctrl		: in  phy_ctrl_t;
+		part_ctrl		: in  part_ctrl_t;
+		sdr_data_w		: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
+		sdr_dm			: in unsigned(SDR_DM_WIDTH-1 downto 0);
+		sdr_data_r		: out unsigned(SDR_DATA_WIDTH-1 downto 0);
+		sdr_data_vld	: out STD_LOGIC;
+		sdr_data_req_w	: out STD_LOGIC;
+		sdr_data_req_r	: out STD_LOGIC;
+		part_clk_p		: out STD_LOGIC;
+		part_clk_n		: out STD_LOGIC;
+		part_dm			: out unsigned(DDR_DM_WIDTH-1 downto 0);
+		part_dqs		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+		part_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0);
+		part_ba			: out unsigned(DDR_BANK_WIDTH-1 downto 0);
+		part_addr		: out unsigned(DDR_ADDR_WIDTH-1 downto 0);
+		part_cs_n		: out STD_LOGIC;
+		part_we_n		: out STD_LOGIC;
+		part_cas_n		: out STD_LOGIC;
+		part_ras_n		: out STD_LOGIC;
+		part_cke		: out STD_LOGIC
+	);
+end ddr_phy;
+
+architecture tech of ddr_phy is
+
+	signal dqs_drive		: std_logic;
+	signal drive			: std_logic;
+	signal dqs				: unsigned(DDR_DQS_WIDTH-1 downto 0);  
+	signal dqs_zen			: unsigned(DDR_DQS_WIDTH-1 downto 0);  
+	signal dqs_rst			: std_logic;
+	signal ddr_data_w		: unsigned(DDR_DATA_WIDTH-1 downto 0);
+	signal data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal data_reg_r		: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal drive270			: unsigned(DDR_DATA_WIDTH-1 downto 0);
+	signal part_ctrl_reg	: part_ctrl_t;
+	signal we_reg			: std_logic;
+	signal read_en			: std_logic;
+	
+	type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
+	signal u_tag_pipe : u_tag_array_t;
+	
+begin
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+utag_pipe:
+	process(sys_rst, sys_clk0)
+	begin
+		if rising_edge(sys_clk0) then
+			for i in u_tag_pipe'length-1 downto 1 loop
+				u_tag_pipe(i) <= u_tag_pipe(i-1);
+			end loop;	
+			if phy_ctrl.utag_we = '1' then
+				u_tag_pipe(0) <= u_tag_in;
+			end if;	
+		end if;
+	end process;
+
+WE_REGISTER:
+	process(sys_rst, sys_clk0)
+	begin
+		if sys_rst = '1' then
+			we_reg <= '0';
+		elsif rising_edge(sys_clk0) then
+			we_reg	<= phy_ctrl.we;
+		end if;
+	end process;
+	
+DATA_DRIVE_GEN:
+	process(sys_clk0)
+	begin
+		if falling_edge(sys_clk0) then
+			dqs_rst		<= not we_reg;
+			drive 		<= we_reg;
+		end if;
+	end process;
+
+DQS_DRIVE_GEN:
+	process(sys_clk0)
+	variable p : unsigned(1 downto 0);
+	begin
+		if rising_edge(sys_clk0) then
+			if phy_ctrl.drive_en = '1' then
+				p := (others => '1');
+			else
+				p := p(p'left-1 downto 0) & '0';
+			end if;
+		end if;
+		dqs_drive <= p(p'left);
+	end process;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- SDRAM Clock
+ODDR_clk_p : ODDR
+	generic map
+	(
+		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+		INIT => '0',						-- Initial value for Q port ('1' or '0')
+		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
+	) 										
+	port map (
+		Q	=> part_clk_p,	-- 1-bit DDR output
+		C	=> sys_clk0,	-- 1-bit clock input
+		CE	=> '1',			-- 1-bit clock enable input
+		D1	=> '1',			-- 1-bit data input (positive edge)
+		D2	=> '0',			-- 1-bit data input (negative edge)
+		R	=> '0',			-- 1-bit reset input
+		S	=> '0' 			-- 1-bit set input
+	);
+
+ODDR_clk_n : ODDR
+	generic map
+	(
+		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+		INIT => '0',						-- Initial value for Q port ('1' or '0')
+		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
+	) 										
+	port map (
+		Q	=> part_clk_n,	-- 1-bit DDR output
+		C	=> sys_clk0,	-- 1-bit clock input
+		CE	=> '1',			-- 1-bit clock enable input
+		D1	=> '0',			-- 1-bit data input (positive edge)
+		D2	=> '1',			-- 1-bit data input (negative edge)
+		R	=> '0',			-- 1-bit reset input
+		S	=> '0' 			-- 1-bit set input
+	);
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- Data OUT DDR-FFs
+gen_ddr_data_out:
+	for n in 0 to DDR_DATA_WIDTH-1 generate
+	begin 
+	ODDR_data : ODDR
+		generic map
+		(
+			DDR_CLK_EDGE => "SAME_EDGE",				-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+			INIT => '0',								-- Initial value for Q port ('1' or '0')
+			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
+		) 										
+		port map (
+			Q	=> ddr_data_w(n),						-- 1-bit DDR output
+			C	=> sys_clk270,							-- 1-bit clock input
+			CE	=> '1',									-- 1-bit clock enable input
+			D1	=> sdr_data_w(n + DDR_DATA_WIDTH),		-- 1-bit data input (positive edge)
+			D2	=> sdr_data_w(n),						-- 1-bit data input (negative edge)
+			R	=> '0',									-- 1-bit reset input
+			S	=> '0' 									-- 1-bit set input
+		);
+	end generate gen_ddr_data_out;
+
+-- Sample tristate on clock90
+	process (sys_clk270)
+	begin  
+		if rising_edge(sys_clk270) then
+			for n in 0 to DDR_DATA_WIDTH-1 loop
+               drive270(n) <= drive;
+			end loop;
+		end if;
+	end process;
+
+-- Output mux
+out_mux_data:
+	for n in 0 to DDR_DATA_WIDTH-1 generate
+		part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
+	end generate;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- Data-mask OUT DDR-FFs
+gen_ddr_dm_out:
+	for n in 0 to DDR_DM_WIDTH-1 generate
+	begin 
+	ODDR_dm : ODDR
+		generic map
+		(
+			DDR_CLK_EDGE => "SAME_EDGE",				-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+			INIT => '0',								-- Initial value for Q port ('1' or '0')
+			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
+		) 										
+		port map (
+			Q	=> part_dm(n),							-- 1-bit DDR output
+			C	=> sys_clk270,							-- 1-bit clock input
+			CE	=> '1',									-- 1-bit clock enable input
+			D1	=> sdr_dm(n + DDR_DM_WIDTH),		-- 1-bit data input (positive edge)
+			D2	=> sdr_dm(n),						-- 1-bit data input (negative edge)
+			R	=> '0',									-- 1-bit reset input
+			S	=> '0' 									-- 1-bit set input
+		);
+	end generate gen_ddr_dm_out;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- DQS OUT DDR-FFs
+gen_dqs_out:
+	for n in 0 to DDR_DQS_WIDTH-1 generate
+	begin 
+	ODDR_dqs : ODDR
+		generic map
+		(
+			DDR_CLK_EDGE => "OPPOSITE_EDGE",			-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+			INIT => '0',								-- Initial value for Q port ('1' or '0')
+			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
+		) 										
+		port map (
+			Q	=> dqs(n),								-- 1-bit DDR output
+			C	=> sys_clk0,							-- 1-bit clock input
+			CE	=> '1',									-- 1-bit clock enable input
+			D2	=> '0',									-- 1-bit data input (positive edge)
+			D1	=> '1',									-- 1-bit data input (negative edge)
+			R	=> dqs_rst,								-- 1-bit reset input
+			S	=> '0' 									-- 1-bit set input
+		);
+	end generate gen_dqs_out;
+
+-- Tristate-Control fuer dqs      
+	process (sys_clk0) is
+	variable zctrl : boolean; 
+	begin
+		if rising_edge(sys_clk0) then
+			if dqs_drive = '1' then
+				zctrl := false;
+			else
+				zctrl := true;
+			end if;
+			if zctrl then 
+				dqs_zen <= (others => '1');
+			else
+				dqs_zen <= (others => '0');
+			end if;	
+		end if;
+	end process;
+
+-- Tristate-Buffer fuer dqs      
+gen_out_mux_dqs:
+	for n in 0 to DDR_DQS_WIDTH-1 generate
+		part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
+	end generate gen_out_mux_dqs;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+	process (sys_rst, sys_clk0) is
+	begin  
+		if sys_rst = '1' then
+			part_ctrl_reg.cmd		<= COMMAND(SD_DESELECT); 
+			part_ctrl_reg.ba		<= (others=>'0');
+			part_ctrl_reg.addr		<= (others=>'0');
+			part_ctrl_reg.cke		<= '0';
+		elsif rising_edge(sys_clk0) then
+			part_ctrl_reg <= part_ctrl;
+		end if;
+	end process;
+
+	process (sys_clk0) is
+	begin  
+		if falling_edge(sys_clk0) then
+			part_ras_n		<= part_ctrl_reg.cmd.ras_n;
+			part_cas_n		<= part_ctrl_reg.cmd.cas_n; 
+			part_we_n 		<= part_ctrl_reg.cmd.we_n; 
+			part_cs_n 		<= part_ctrl_reg.cmd.cs_n; 
+			part_ba   		<= part_ctrl_reg.ba; 
+			part_addr    	<= part_ctrl_reg.addr;
+			part_cke  		<= part_ctrl_reg.cke;
+		end if;
+	end process;
+
+-----------------------------------------------------------------
+-- READ DATA Processing
+-----------------------------------------------------------------
+gen_ddr_data_in:
+	for n in 0 to DDR_DATA_WIDTH-1 generate
+	begin 
+	IDDR_data : IDDR 
+		generic map
+		(
+			DDR_CLK_EDGE	=> "SAME_EDGE",					-- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" 
+			INIT_Q1			=> '0', 						-- Initial value of Q1: '0' or '1'
+			INIT_Q2			=> '0',							-- Initial value of Q2: '0' or '1'
+			SRTYPE			=> "SYNC"						-- Set/Reset type: "SYNC" or "ASYNC" 
+		)
+		port map
+		(
+			Q1				=> data_r(n),					-- 1-bit output for positive edge of clock 
+			Q2				=> data_r(n + DDR_DATA_WIDTH),	-- 1-bit output for negative edge of clock
+			C				=> read_clk, 					-- 1-bit clock input
+			CE				=> read_en,						-- 1-bit clock enable input
+			D				=> part_data(n),				-- 1-bit DDR data input
+			R				=> '0',							-- 1-bit reset
+			S				=> '0' 							-- 1-bit set
+		);
+	end generate;
+
+
+data_sample_stage:
+	process (sys_clk0)
+	begin
+		if falling_edge(sys_clk0) then
+			data_reg_r	<= data_r;
+		end if;
+	end process;
+
+misc_flags_and_data_out:
+	process (sys_rst, sys_clk0)
+	variable p : unsigned(3 downto 0);
+	begin
+		if sys_rst = '1' then
+			p				:= (others => '0');
+			read_en			<= '0';
+			sdr_data_vld	<= '0';
+			sdr_data_req_w	<= '0';
+			sdr_data_req_r	<= '0';
+		elsif rising_edge(sys_clk0) then
+			sdr_data_r		<= data_reg_r;
+			if p(3) = '1' then
+				u_tag_rd		<= u_tag_pipe(4);
+			end if;	
+			if phy_ctrl.we = '1' then
+				u_tag_wr		<= u_tag_pipe(0);
+			end if;	
+			sdr_data_req_w	<= phy_ctrl.we;
+			sdr_data_req_r	<= phy_ctrl.re;
+			sdr_data_vld	<= p(3);
+			read_en			<= p(1);
+			if phy_ctrl.re = '1' then
+				p := p(p'left-1 downto 0) & '1';
+			else
+				p := p(p'left-1 downto 0) & '0';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+end tech;

lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd

@@ -0,0 +1,111 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Reset generator (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity reset is
+	port
+	(
+		clk			: in std_logic;
+		rst_in		: in std_logic;
+		rst_out		: out std_logic
+	);
+end;
+
+architecture tech of reset is
+   
+	signal rst : std_logic;
+	signal shift_pipe : std_logic_vector(3 downto 0);
+	attribute KEEP : string;
+	attribute KEEP of shift_pipe	: signal is "TRUE";
+
+begin
+   
+	rst <= shift_pipe(0);
+
+bufg_reset: bufg
+	port map
+	(
+		o  => rst_out,  
+		i  => rst
+	);
+	
+fdp0: fdp
+	generic map 
+	(
+		init	=> '1'
+	)
+	port map 
+	(
+		d		=> rst_in,
+		c		=> clk,
+		pre		=> '0',
+		q		=> shift_pipe(3)
+	);
+
+fdp1: fdp
+	generic map 
+	(
+		init	=> '1'
+	)
+	port map
+	(
+
+		d		=> shift_pipe(3),
+		c		=> clk,
+		pre		=> '0',
+		q		=> shift_pipe(2)
+	);
+
+fdp2: fdp
+	generic map 
+	(
+		init	=> '1'
+	)
+	port map
+	(
+		d		=> shift_pipe(2),
+		c		=> clk,
+		pre		=> '0',
+		q		=> shift_pipe(1)
+	);
+
+fdp3: fdp
+	generic map 
+	(
+		init	=> '1'
+	)
+	port map
+	(
+
+		d		=> shift_pipe(1),
+		c		=> clk,
+		pre		=> '0',
+		q		=> shift_pipe(0)
+	);
+  
+end tech;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd

@@ -0,0 +1,268 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: SDRAM command controller
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_cmd is
+	Generic (BL 		: natural := 2);
+	Port (
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		enable			: in  STD_LOGIC;
+		u_tag_in		: in  user_tag_t;
+		u_tag_out		: out user_tag_t;
+		phy_ctrl		: out phy_ctrl_t;
+		cmd				: in  sdr_cmd_t;
+		cmd_we			: in  STD_LOGIC;
+		cmd_ack			: out STD_LOGIC;
+		col_addr		: in col_addr_t;
+		mode_word		: in  mode_word_t;
+		sdr_cmd_ctrl	: out sdr_cmd_lines_t;
+		sdr_addr		: out  sdr_addr_t;
+		sdr_ba			: out  sdr_ba_t
+	);
+end sdram_cmd;
+
+architecture behaviour of sdram_cmd is
+
+	signal st_sdr, st_sdr_next : sdr_state_t;
+	
+	signal cc_preset : natural range 0 to 10;
+	signal cc_load_en : std_logic;
+	signal cycle_finished : std_logic;
+
+	signal burst_preset : natural range 0 to 3;
+	signal burst_load_en : std_logic;
+	signal burst_finished : std_logic;
+
+begin
+
+	u_tag_out <= u_tag_in;
+	
+------------------------------------------------------------------------------------------
+
+fsm_sdr_state:
+	process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
+	begin
+		st_sdr_next		<= st_sdr;
+		sdr_cmd_ctrl <= COMMAND(SD_NOP);
+		
+		cc_load_en <= '0';
+		cc_preset <= TIMING(cmd);
+		burst_load_en <= '0';
+		cmd_ack	<= '0';
+		burst_preset <= BL/2-1;
+		phy_ctrl.re <= '0';
+		phy_ctrl.drive_en <= '0';
+		phy_ctrl.we <= '0';
+		phy_ctrl.utag_we <= '0';
+		sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
+		sdr_ba	 <= mode_word(mode_word_t'left downto mode_word_t'left-1);
+		
+		case st_sdr is 
+		when PWR_DOWN =>
+			sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
+			if enable = '1' then
+				st_sdr_next <= IDLE;
+			end if;	
+			
+		when PRECHARGE =>
+			if cycle_finished = '1' then
+				st_sdr_next <= IDLE;
+			end if;	
+
+		when MODE =>
+			if cycle_finished = '1' then
+				st_sdr_next <= IDLE;
+			end if;	
+
+		when IDLE =>
+			if cmd_we = '1' then
+				cmd_ack <= '1';
+				cc_load_en <= '1';
+				cc_preset <= TIMING(cmd);
+				sdr_cmd_ctrl <= COMMAND(cmd);
+				case cmd is
+					when SD_PRE =>
+						st_sdr_next <= PRECHARGE;
+					when SD_LMR =>
+						st_sdr_next <= MODE;
+					when SD_ACT =>
+						st_sdr_next <= ROW_ACT;
+					when SD_AR =>
+						st_sdr_next <= AUTO_REF;
+					when others	=> null;
+					end case;	
+			end if;	
+				
+		when ROW_ACT =>
+			if cycle_finished = '1' then
+				if cmd_we = '1' then
+					cmd_ack <= '1';
+					burst_load_en <= '1';
+					cc_load_en <= '1';
+					cc_preset <= TIMING(cmd);
+					sdr_cmd_ctrl <= COMMAND(cmd);
+					case cmd is
+					when SD_PRE =>
+						st_sdr_next <= PRECHARGE;
+					when SD_READ =>
+						phy_ctrl.utag_we <= '1';
+						st_sdr_next <= READ;
+						sdr_addr(col_addr_t'range) <= col_addr;
+					when SD_WRITE =>
+						phy_ctrl.utag_we <= '1';
+						phy_ctrl.drive_en <= '1';
+						st_sdr_next <= WRITE;
+						sdr_addr(col_addr_t'range) <= col_addr;
+					when others	=> null;
+					end case;	
+				end if;	
+			end if;	
+
+		when WRITE =>
+			phy_ctrl.drive_en <= '1';
+			phy_ctrl.we <= '1';
+			if burst_finished = '1' then
+				if cmd_we = '1' and cmd = SD_WRITE then
+					sdr_addr(col_addr_t'range) <= col_addr;
+					cmd_ack <= '1';
+					burst_load_en <= '1';
+					sdr_cmd_ctrl <= COMMAND(cmd);
+					phy_ctrl.utag_we <= '1';
+				else	
+					phy_ctrl.drive_en <= '0';
+					cc_load_en <= '1';
+					cc_preset <= TIMING(SD_WRITE)+1;
+					st_sdr_next <= ROW_ACT;
+				end if;
+			end if;	
+
+		when READ =>
+			phy_ctrl.re <= '1';
+			if burst_finished = '1' then
+				if cmd_we = '1' and cmd = SD_READ then
+					sdr_addr(col_addr_t'range) <= col_addr;
+					cmd_ack <= '1';
+					burst_load_en <= '1';
+					sdr_cmd_ctrl <= COMMAND(cmd);
+					phy_ctrl.utag_we <= '1';
+				else
+					cc_load_en <= '1';
+					cc_preset <= TIMING(SD_READ);
+					st_sdr_next <= ROW_ACT;
+				end if;
+			end if;	
+
+		when WRITE_A =>			-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+
+		when READ_A =>			-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+
+		when BURST_STOP =>		-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+			
+		when SELF_REF =>		-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+			
+		when PRE_PWR_DOWN =>	-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+
+		when ACT_PWR_DOWN =>	-- not implemented yet
+			cmd_ack <= '1';
+			st_sdr_next <= IDLE;
+		
+		when AUTO_REF =>
+			if cycle_finished = '1' then
+				st_sdr_next <= IDLE;
+			end if;	
+			
+		when others =>
+			st_sdr_next <= IDLE;
+		end case;
+		
+	end process;
+	
+fsm_sdr_state_next:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			st_sdr		<= PWR_DOWN;
+		elsif rising_edge(clk) then
+			st_sdr		<= st_sdr_next;
+		end if;
+	end process;
+	
+------------------------------------------------------------------------------------------
+cycle_counter:
+	process (rst, clk)
+	variable cycle_cnt : natural range 0 to 10;
+	begin
+		if rst = '1' then
+			cycle_cnt	:= 0;
+			cycle_finished	<= '0';
+		elsif rising_edge(clk) then
+			cycle_finished	<= '0';
+			if cc_load_en = '1' then
+				cycle_cnt := cc_preset;
+			elsif cycle_cnt /= 0 then
+				cycle_cnt := cycle_cnt - 1;
+			else
+				cycle_finished	<= '1';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+burst_counter:
+	process (rst, clk)
+	variable burst_cnt : natural range 0 to 3;
+	begin
+		if rst = '1' then
+			burst_cnt	:= 0;
+		elsif rising_edge(clk) then
+			burst_finished	<= '0';
+			if burst_load_en = '1' then
+				burst_cnt := burst_preset;
+			elsif burst_cnt /= 0 then
+				burst_cnt := burst_cnt - 1;
+			end if;	
+			if burst_cnt = 0 then
+				burst_finished	<= '1';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+end behaviour;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd

@@ -0,0 +1,74 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: User SDRAM component adjustments
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package sdram_config is
+
+	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
+	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
+	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
+	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
+	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
+
+	constant LMR_REG_BASE		: natural := 0;
+	constant LMR_REG_EXTENDED	: natural := 1;
+	constant LMR_OP_NORMAL		: natural := 0;
+	constant LMR_OP_RES_DLL		: natural := 2;
+	constant LMR_BT_SEQ			: natural := 0;
+	constant LMR_BT_ILVD		: natural := 1;
+	constant LMR_BL2			: natural := 1;
+	constant LMR_BL4			: natural := 2;
+	constant LMR_BL8			: natural := 3;
+	constant LMR_CL2			: natural := 2;
+	constant LMR_CL3			: natural := 3;
+	constant LMR_CL2_5			: natural := 6;
+
+	-- DDR SDRAM Hardware defined constants
+	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
+	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
+	constant ENABLE_PRE_ALL		: std_logic := '1';
+	constant ENABLE_AUTO_PRE	: std_logic := '0';
+
+	-- DDR-SDR TIMING constants ------------------------------------------------------------------
+	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
+	constant REFRESH_INTERVAL : real := 7.8125; -- us
+
+	-- These values are for your SDRAM part (see datasheet) 
+	constant TCAS : positive  := 2;   -- CAS latency [clocks]
+	constant TRP  : positive  := 2;   -- precharge command period
+	constant TRAS : positive  := 4;   -- active to precharge delay 
+	constant TRFC : positive  := 8;   -- auto refresh command period
+	constant TMRD : positive  := 2;   -- load mode register command cylce time
+	constant TRCD : positive  := 2;   -- active to read or write delay !
+	constant TWR  : positive  := 2;   -- write recovery time
+
+	constant PWR_UP_WAIT : natural := 1; -- µs
+	
+	subtype user_tag_t is unsigned(3 downto 0);
+	
+	----------------------------------------------------------------------------------------------
+	
+end sdram_config;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd

@@ -0,0 +1,491 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: SDRAM main controller and user I/F
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.utils_pkg.all;
+
+entity sdram_ctrl is
+	Generic
+	(
+		f_sysclk 		: natural := 100E6;
+		BL 				: natural := 2
+	);
+	Port (
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		u_busy			: out STD_LOGIC;
+		u_tag_in		: in  user_tag_t;
+		u_tag_out		: out user_tag_t;
+		u_addr			: in  user_addr_t;
+		u_cmd			: in  user_cmd_t;
+		u_cmd_we		: in  STD_LOGIC;
+		col_addr		: out col_addr_t;
+		sdr_cmd_busy	: in  STD_LOGIC;
+		sdr_cmd			: out  sdr_cmd_t;
+		sdr_cmd_we		: out  STD_LOGIC;
+		sdr_mode		: out  mode_word_t;
+		sdr_cke			: out  STD_LOGIC
+	);
+end sdram_ctrl;
+
+architecture behaviour of sdram_ctrl is
+
+	constant LMR_BURST_LEN		: natural := NextExpBaseTwo(BL);
+
+	type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
+	signal st_ctrl, st_ctrl_next : ctrl_state_t;
+	
+	constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
+	signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
+	signal pwr_up_cnt_rst : std_logic;
+	signal pwr_up_finished : std_logic;
+
+	signal cycle_cnt : natural range 0 to 255;
+	signal cc_preset : natural range 0 to 255;
+	signal cc_load_en : std_logic;
+	signal cycle_finished : std_logic;
+
+	signal seq_cnt : natural range 0 to 31;
+	signal seq_rst_en : std_logic;
+	signal seq_cnt_en : std_logic;
+	
+	constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
+	signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
+	signal refresh_request : std_logic;
+	signal refresh_cnt_rst : std_logic;
+
+	signal addr_reg_load_en : std_logic;
+
+	signal u_tag_reg : user_tag_t;
+	signal bank_addr_reg : bank_addr_t;
+	signal row_addr_reg : row_addr_t;
+	signal col_addr_reg : col_addr_t;
+	signal bank_addr_last : bank_addr_t;
+	signal row_addr_last : row_addr_t;
+	signal col_addr_last : col_addr_t;
+
+	signal u_bank_addr : bank_addr_t;
+	signal u_row_addr : row_addr_t;
+	signal u_col_addr : col_addr_t;
+
+	signal bank_active_reg : unsigned(0 to 3);
+	signal bank_is_active : std_logic;
+	signal bank_activate : std_logic;
+	signal bank_clr : std_logic;
+
+	type init_seq_rom_t is array (0 to 14) of init_seq_t;
+	
+	constant init_seq_rom : init_seq_rom_t :=
+	(
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_PRE,
+			mode_word	=> "000010000000000",
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_LMR,
+			mode_word	=> to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_LMR,
+			mode_word	=> to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
+			wait_cycle	=> 200
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_PRE,
+			mode_word	=> "000010000000000",
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_AR,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_AR,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		),
+		(
+			cmd			=> SD_LMR,
+			mode_word	=> to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
+			wait_cycle	=> 200
+		),
+		(
+			cmd			=> SD_NOP,
+			mode_word	=> (others => '0'),
+			wait_cycle	=> 0
+		)
+	
+	);
+		
+begin
+
+	u_row_addr		<= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
+	u_bank_addr		<= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
+	u_col_addr		<= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
+	bank_is_active	<= bank_active_reg(to_integer(u_bank_addr));
+
+------------------------------------------------------------------------------------------
+fsm_ctrl_state:
+	process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, bank_addr_last, row_addr_last, refresh_request, bank_is_active)
+	begin
+
+		u_busy 				<= '1';
+		pwr_up_cnt_rst		<= '0';
+		cc_preset			<= init_seq_rom(seq_cnt).wait_cycle;
+		cc_load_en			<= '0';
+		sdr_cmd				<= init_seq_rom(seq_cnt).cmd;
+		sdr_cmd_we			<= '0';
+		sdr_mode			<= bank_addr_reg & row_addr_reg;
+		col_addr			<= col_addr_reg;
+		sdr_cke				<= '1';
+		seq_cnt_en			<= '0';
+		seq_rst_en			<= '0';
+		addr_reg_load_en	<= '0';
+		refresh_cnt_rst		<= '0';
+		bank_activate		<= '0';
+		bank_clr			<= '0';
+		u_tag_out			<= u_tag_reg;
+		
+		st_ctrl_next		<= st_ctrl;
+		case st_ctrl is 
+		when RESET =>
+			sdr_cke			<= '0';
+			pwr_up_cnt_rst	<= '1';
+			st_ctrl_next	<= POWER_WAIT;
+			
+		when POWER_WAIT =>
+			sdr_cke			<= '0';
+			if pwr_up_finished = '1' then
+				seq_rst_en		<= '1';
+				st_ctrl_next	<= INIT;
+			end if;	
+
+		when INIT =>
+			sdr_mode	<= init_seq_rom(seq_cnt).mode_word;
+			sdr_cmd		<= init_seq_rom(seq_cnt).cmd;
+			cc_preset	<= init_seq_rom(seq_cnt).wait_cycle;
+			if seq_cnt = init_seq_rom_t'high then
+				bank_clr		<= '1';
+				refresh_cnt_rst	<= '1';
+				st_ctrl_next	<= USER_READY;
+			elsif sdr_cmd_busy = '0' then
+				cc_load_en		<= '1';
+				sdr_cmd_we		<= '1';
+				st_ctrl_next	<= INIT_WAIT;
+			end if;	
+				
+		when INIT_WAIT =>
+			if sdr_cmd_busy = '0' and cycle_finished = '1' then
+				seq_cnt_en		<= '1';
+				st_ctrl_next	<= INIT;
+			end if;	
+			
+		when USER_READY =>
+			if refresh_request = '1' then
+				st_ctrl_next	<= REFRESH_PRE;
+			else	
+				u_busy		<= '0';
+				col_addr				<= u_col_addr;
+				u_tag_out				<= u_tag_in;
+				sdr_mode				<= u_bank_addr & u_row_addr;
+				sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
+				if u_cmd_we = '1' then
+					addr_reg_load_en		<= '1';
+					case u_cmd is
+					when UCMD_NOP =>
+						sdr_cmd		<= SD_NOP;
+					when UCMD_LMR =>
+						sdr_cmd		<= SD_NOP;
+					when UCMD_WRITE =>
+						sdr_cmd					<= SD_WRITE;
+						if (u_row_addr /= row_addr_reg) then
+							st_ctrl_next		<= USER_WRITE_PRE;
+						elsif bank_is_active = '0' then
+							st_ctrl_next		<= USER_WRITE_ACT;
+						elsif sdr_cmd_busy = '1' then
+							st_ctrl_next		<= USER_WRITE;
+						else
+							sdr_cmd_we			<= '1';
+						end if;
+					when UCMD_READ =>
+						sdr_cmd					<= SD_READ;
+						if (u_row_addr /= row_addr_reg) then
+							st_ctrl_next		<= USER_READ_PRE;
+						elsif bank_is_active = '0' then
+							st_ctrl_next		<= USER_READ_ACT;
+						elsif sdr_cmd_busy = '1' then
+							st_ctrl_next		<= USER_READ;
+						else
+							sdr_cmd_we			<= '1';
+						end if;
+					when others => null;
+					end case;
+				end if;	
+			end if;	
+
+		when USER_WRITE_PRE =>
+		bank_clr		<= '1';
+		sdr_cmd					<= SD_PRE;
+		sdr_mode				<= bank_addr_last & row_addr_last;
+		sdr_mode(BIT_PRE_ALL)	<= ENABLE_PRE_ALL;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_WRITE_ACT;
+		end if;
+
+		when USER_WRITE_ACT =>
+		bank_activate	<= '1';
+		sdr_cmd				<= SD_ACT;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_WRITE;
+		end if;
+
+		when USER_WRITE =>
+		sdr_cmd					<= SD_WRITE;
+		sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READY;
+		end if;
+
+		when USER_READ_PRE =>
+		bank_clr		<= '1';
+		sdr_cmd			<= SD_PRE;
+		sdr_mode				<= bank_addr_last & row_addr_last;
+		sdr_mode(BIT_PRE_ALL)	<= ENABLE_PRE_ALL;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READ_ACT;
+		end if;
+
+		when USER_READ_ACT =>
+		bank_activate	<= '1';
+		sdr_cmd					<= SD_ACT;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READ;
+		end if;
+
+		when USER_READ =>
+		sdr_cmd					<= SD_READ;
+		sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READY;
+		end if;
+
+		when REFRESH_PRE =>
+		bank_clr		<= '1';
+		sdr_cmd					<= SD_PRE;
+--		sdr_mode				<= bank_addr_last & row_addr_last;
+		sdr_mode(BIT_PRE_ALL)	<= ENABLE_PRE_ALL;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= REFRESH;
+		end if;
+
+		when REFRESH =>
+		sdr_cmd			<= SD_AR;
+		if sdr_cmd_busy = '0' then
+			sdr_cmd_we		<= '1';
+			st_ctrl_next	<= USER_READY;
+			refresh_cnt_rst	<= '1';
+		end if;
+		
+		when others =>
+			st_ctrl_next <= RESET;
+		end case;
+		
+	end process;
+	
+fsm_ctrl_state_next:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			st_ctrl		<= RESET;
+		elsif rising_edge(clk) then
+			st_ctrl		<= st_ctrl_next;
+		end if;
+	end process;
+	
+------------------------------------------------------------------------------------------
+bank_active_register:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			if bank_clr = '1' then
+				bank_active_reg <= (others => '0');		-- assumes PRE_ALL !!!!!!!!!!!!!
+			elsif bank_activate = '1' then	
+				bank_active_reg(to_integer(bank_addr_reg)) <= '1';
+			end if;	
+		end if;
+	end process;
+
+
+------------------------------------------------------------------------------------------
+user_addr_register:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			bank_addr_reg <= (others => '0');
+			row_addr_reg <= (others => '0');
+			col_addr_reg <= (others => '0');
+			u_tag_reg <= (others => '0');
+		elsif rising_edge(clk) then
+			if addr_reg_load_en = '1' then
+				bank_addr_last <= bank_addr_reg;
+				row_addr_last <= row_addr_reg;
+				col_addr_last <= col_addr_reg;
+				bank_addr_reg <= u_bank_addr;
+				row_addr_reg <= u_row_addr;
+				col_addr_reg <= u_col_addr;
+				u_tag_reg <= u_tag_in;
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+power_up_counter:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			pwr_up_cnt	<= 0;
+			pwr_up_finished <= '0';
+		elsif rising_edge(clk) then
+			pwr_up_finished <= '0';
+			if pwr_up_cnt_rst = '1' then
+				pwr_up_cnt	<= PWR_UP_CLOCK_INTERVAL-1;
+			else
+				if pwr_up_cnt /= 0 then
+					pwr_up_cnt <= pwr_up_cnt - 1;
+				else
+					pwr_up_finished <= '1';
+				end if;	
+			end if;	
+		end if;
+	end process;
+
+
+------------------------------------------------------------------------------------------
+refresh_counter:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			refresh_cnt	<= 0;
+			refresh_request <= '0';
+		elsif rising_edge(clk) then
+			refresh_request <= '0';
+			if refresh_cnt_rst = '1' then
+				refresh_cnt	<= REFRESH_CLOCK_INTERVAL-1;
+			else
+				if refresh_cnt /= 0 then
+					refresh_cnt <= refresh_cnt - 1;
+				else
+					refresh_request <= '1';
+				end if;	
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+cycle_counter:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			cycle_cnt	<= 0;
+			cycle_finished	<= '0';
+		elsif rising_edge(clk) then
+			cycle_finished	<= '0';
+			if cc_load_en = '1' then
+				cycle_cnt <= cc_preset;
+			elsif cycle_cnt /= 0 then
+				cycle_cnt <= cycle_cnt - 1;
+			else
+				cycle_finished	<= '1';
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+seq_counter:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			seq_cnt	<= 0;
+		elsif rising_edge(clk) then
+			if seq_rst_en = '1' then
+				seq_cnt <= 0;
+			elsif seq_cnt_en = '1' then
+				if seq_cnt /= init_seq_rom_t'high then
+					seq_cnt <= seq_cnt + 1;
+				end if;	
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------------------------------
+end behaviour;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd

@@ -0,0 +1,272 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_ctrl_frontend64_wb is
+	Generic
+	(
+		BL 				: natural := 2;
+		f_sysclk 		: natural := 100E6;
+		fifo_depth		: integer := 4
+	);
+	Port
+	(
+		RST_I				: in  STD_LOGIC;
+		CLK_I				: in  STD_LOGIC;
+		CLK270_I			: in  STD_LOGIC;
+		CLK270VAR_I			: in  STD_LOGIC;
+		
+		CYC_I				: in  STD_LOGIC;
+		STB_I				: in  STD_LOGIC;
+		SEL_I				: in  unsigned(SDR_DM_WIDTH-1 downto 0);
+		WE_I				: in  STD_LOGIC;
+		ACK_O				: out STD_LOGIC;
+		MRDY_I				: in  STD_LOGIC;
+		SRDY_O				: out STD_LOGIC;
+		ADDR_I				: in  unsigned(31 downto 0);
+		DAT_I				: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
+		DAT_O				: out unsigned(SDR_DATA_WIDTH-1 downto 0);
+
+		-- SDRAM signals
+		sd_clk_p			: out  STD_LOGIC;
+		sd_clk_n			: out  STD_LOGIC;
+		sd_cke				: out  STD_LOGIC;
+		sd_cs_n				: out  STD_LOGIC;
+		sd_cas_n			: out  STD_LOGIC;
+		sd_ras_n			: out  STD_LOGIC;
+		sd_we_n				: out  STD_LOGIC;
+		sd_addr				: out  sdr_addr_t;
+		sd_ba				: out  sdr_ba_t;
+		sd_dm				: out unsigned(DDR_DM_WIDTH-1 downto 0);
+		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
+		
+	);
+end sdram_ctrl_frontend64_wb;
+
+architecture struct of sdram_ctrl_frontend64_wb is
+
+	-- Number of user data words for simulation
+	signal u_addr			: user_addr_t;
+	signal u_tag_in			: user_tag_t;
+	signal u_tag_rd			: user_tag_t;
+	signal u_tag_wr			: user_tag_t;
+	signal u_cmd			: user_cmd_t;
+	signal u_cmd_we			: std_logic;
+	signal u_busy			: std_logic;
+	signal u_data_w			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal u_dm_wr_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
+	signal u_data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal u_data_vld		: std_logic;
+	signal u_req_wr			: std_logic;
+	signal rdy				: std_logic;
+
+	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
+	signal cat_fifo_din				: unsigned(CAT_FIFO_WIDTH-1 downto 0);
+	signal cat_fifo_dout			: unsigned(CAT_FIFO_WIDTH-1 downto 0);
+	signal cat_fifo_re				: std_logic;
+	signal cat_fifo_we				: std_logic;
+	signal cat_fifo_full			: std_logic;
+	signal cat_fifo_empty			: std_logic;
+--	signal cat_fifo_almost_full		: std_logic;
+--	signal cat_fifo_almost_empty	: std_logic;
+
+	signal write_fifo_din			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
+	signal write_fifo_dout			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
+	signal write_fifo_re			: std_logic;
+	signal write_fifo_we			: std_logic;
+	signal write_fifo_full			: std_logic;
+	signal write_fifo_empty			: std_logic;
+--	signal write_fifo_almost_full	: std_logic;
+--	signal write_fifo_almost_empty	: std_logic;
+
+	signal read_fifo_din			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal read_fifo_dout			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal read_fifo_re				: std_logic;
+	signal read_fifo_we				: std_logic;
+	signal read_fifo_full			: std_logic;
+	signal read_fifo_empty			: std_logic;
+--	signal read_fifo_almost_full	: std_logic;
+--	signal read_fifo_almost_empty	: std_logic;
+
+	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+	alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+	alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+
+	alias write_fifo_dm_in is write_fifo_din(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
+	alias write_fifo_data_in is write_fifo_din(SDR_DATA_WIDTH-1 downto 0);
+	alias write_fifo_dm_out is write_fifo_dout(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
+	alias write_fifo_data_out is write_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
+
+	alias read_fifo_data_in is read_fifo_din(SDR_DATA_WIDTH-1 downto 0);
+	alias read_fifo_data_out is read_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
+	
+begin 
+   
+	-- Instantiate synchronous FIFO
+	inst_cat_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> CAT_FIFO_WIDTH
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	cat_fifo_we,
+		re			=>	cat_fifo_re,
+		fifo_full	=>	cat_fifo_full,
+		fifo_empty	=>	cat_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  cat_fifo_din,
+		data_r		=>  cat_fifo_dout
+	);
+
+	-- Instantiate synchronous FIFO
+	inst_write_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> write_fifo_din'length
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	write_fifo_we,
+		re			=>	write_fifo_re,
+		fifo_full	=>	write_fifo_full,
+		fifo_empty	=>	write_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  write_fifo_din,
+		data_r		=>  write_fifo_dout
+	);
+
+	-- Instantiate synchronous FIFO
+	inst_read_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> read_fifo_din'length
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	read_fifo_we,
+		re			=>	read_fifo_re,
+		fifo_full	=>	read_fifo_full,
+		fifo_empty	=>	read_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  read_fifo_din,
+		data_r		=>  read_fifo_dout
+	);
+
+	-- DDR SDRAM Controller Core
+	inst_sdram_ctrl : entity work.sdram_ctrl_top
+	Generic map
+	(
+		BL 				=> BL,
+		f_sysclk 		=> f_sysclk
+	)
+	Port map
+	(
+	
+		sys_rst_in			=> RST_I,
+		sys_clk0_in			=> CLK_I,
+
+		sys_clk270_in		=> CLK270_I,
+		capture_clk270_in	=> CLK270VAR_I,
+		
+		-- User interface
+		u_data_vld			=> u_data_vld,
+		u_data_req_w		=> u_req_wr,
+		u_data_req_r		=> open,
+		u_tag_in			=> u_tag_in,
+		u_tag_rd			=> u_tag_rd,
+		u_tag_wr			=> u_tag_wr,
+		u_busy				=> u_busy,
+		u_addr				=> u_addr,
+		u_cmd				=> u_cmd,
+		u_cmd_we			=> u_cmd_we,
+		u_data_wr			=> u_data_w,
+		u_data_rd			=> u_data_r,
+		u_dm				=> u_dm_wr_in,
+		
+		-- SDRAM signals
+		sd_clk_p			=> sd_clk_p,
+		sd_clk_n			=> sd_clk_n,
+		sd_cke				=> sd_cke,
+		sd_cs_n				=> sd_cs_n,
+		sd_cas_n			=> sd_cas_n,
+		sd_ras_n			=> sd_ras_n,
+		sd_we_n				=> sd_we_n,
+		sd_addr				=> sd_addr,
+		sd_ba				=> sd_ba,
+		sd_dm				=> sd_dm,
+		sd_dqs				=> sd_dqs,
+		sd_data				=> sd_data
+		
+	);
+
+------------------------------------------------------------------------------------------
+	SRDY_O				<= rdy;
+	ACK_O				<= not (read_fifo_empty);
+	DAT_O				<= read_fifo_data_out;
+	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
+	write_fifo_we 		<= STB_I and WE_I and rdy;
+	write_fifo_data_in	<= DAT_I;
+	write_fifo_dm_in	<= not SEL_I;
+	cat_fifo_we			<= STB_I and rdy;
+	cmd_fifo_in			<= UCMD_WRITE when WE_I = '1' else UCMD_READ;
+	addr_fifo_in		<= ADDR_I(25 downto 3) & "0";
+	tag_fifo_in			<= "000" & ADDR_I(2);
+	
+	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
+	u_cmd				<= cmd_fifo_out;
+	u_addr				<= addr_fifo_out;
+	u_dm_wr_in			<= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when u_tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
+	u_tag_in			<= tag_fifo_out;
+	u_data_w			<= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0);
+	
+	write_fifo_re		<= u_req_wr and (not write_fifo_empty);
+	cat_fifo_re			<= u_cmd_we;
+	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
+	read_fifo_we		<= u_data_vld;
+	read_fifo_data_in	<= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0);	
+
+end architecture struct;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd

@@ -0,0 +1,272 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_ctrl_frontend_wb is
+	Generic
+	(
+		BL 				: natural := 2;
+		f_sysclk 		: natural := 100E6;
+		fifo_depth		: integer := 4
+	);
+	Port
+	(
+		RST_I				: in  STD_LOGIC;
+		CLK_I				: in  STD_LOGIC;
+		CLK270_I			: in  STD_LOGIC;
+		CLK270VAR_I			: in  STD_LOGIC;
+		
+		CYC_I				: in  STD_LOGIC;
+		STB_I				: in  STD_LOGIC;
+		SEL_I				: in  unsigned(3 downto 0);
+		WE_I				: in  STD_LOGIC;
+		ACK_O				: out STD_LOGIC;
+		MRDY_I				: in  STD_LOGIC;
+		SRDY_O				: out STD_LOGIC;
+		ADDR_I				: in  unsigned(31 downto 0);
+		DAT_I				: in  unsigned(31 downto 0);
+		DAT_O				: out unsigned(31 downto 0);
+
+		-- SDRAM signals
+		sd_clk_p			: out  STD_LOGIC;
+		sd_clk_n			: out  STD_LOGIC;
+		sd_cke				: out  STD_LOGIC;
+		sd_cs_n				: out  STD_LOGIC;
+		sd_cas_n			: out  STD_LOGIC;
+		sd_ras_n			: out  STD_LOGIC;
+		sd_we_n				: out  STD_LOGIC;
+		sd_addr				: out  sdr_addr_t;
+		sd_ba				: out  sdr_ba_t;
+		sd_dm				: out unsigned(DDR_DM_WIDTH-1 downto 0);
+		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
+		
+	);
+end sdram_ctrl_frontend_wb;
+
+architecture struct of sdram_ctrl_frontend_wb is
+
+	-- Number of user data words for simulation
+	signal u_addr			: user_addr_t;
+	signal u_tag_in			: user_tag_t;
+	signal u_tag_rd			: user_tag_t;
+	signal u_tag_wr			: user_tag_t;
+	signal u_cmd			: user_cmd_t;
+	signal u_cmd_we			: std_logic;
+	signal u_busy			: std_logic;
+	signal u_data_w			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal u_dm_wr_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
+	signal u_data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal u_data_vld		: std_logic;
+	signal u_req_wr			: std_logic;
+	signal rdy				: std_logic;
+
+	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
+	signal cat_fifo_din				: unsigned(CAT_FIFO_WIDTH-1 downto 0);
+	signal cat_fifo_dout			: unsigned(CAT_FIFO_WIDTH-1 downto 0);
+	signal cat_fifo_re				: std_logic;
+	signal cat_fifo_we				: std_logic;
+	signal cat_fifo_full			: std_logic;
+	signal cat_fifo_empty			: std_logic;
+--	signal cat_fifo_almost_full		: std_logic;
+--	signal cat_fifo_almost_empty	: std_logic;
+
+	signal write_fifo_din			: unsigned(35 downto 0);
+	signal write_fifo_dout			: unsigned(35 downto 0);
+	signal write_fifo_re			: std_logic;
+	signal write_fifo_we			: std_logic;
+	signal write_fifo_full			: std_logic;
+	signal write_fifo_empty			: std_logic;
+--	signal write_fifo_almost_full	: std_logic;
+--	signal write_fifo_almost_empty	: std_logic;
+
+	signal read_fifo_din			: unsigned(31 downto 0);
+	signal read_fifo_dout			: unsigned(31 downto 0);
+	signal read_fifo_re				: std_logic;
+	signal read_fifo_we				: std_logic;
+	signal read_fifo_full			: std_logic;
+	signal read_fifo_empty			: std_logic;
+--	signal read_fifo_almost_full	: std_logic;
+--	signal read_fifo_almost_empty	: std_logic;
+
+	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+	alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+	alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+
+	alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4);
+	alias write_fifo_dm_in is write_fifo_din(3 downto 0);
+	alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4);
+	alias write_fifo_dm_out is write_fifo_dout(3 downto 0);
+
+	alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0);
+	alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0);
+	
+begin 
+   
+	-- Instantiate synchronous FIFO
+	inst_cat_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> CAT_FIFO_WIDTH
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	cat_fifo_we,
+		re			=>	cat_fifo_re,
+		fifo_full	=>	cat_fifo_full,
+		fifo_empty	=>	cat_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  cat_fifo_din,
+		data_r		=>  cat_fifo_dout
+	);
+
+	-- Instantiate synchronous FIFO
+	inst_write_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> write_fifo_din'length
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	write_fifo_we,
+		re			=>	write_fifo_re,
+		fifo_full	=>	write_fifo_full,
+		fifo_empty	=>	write_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  write_fifo_din,
+		data_r		=>  write_fifo_dout
+	);
+
+	-- Instantiate synchronous FIFO
+	inst_read_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width	=> fifo_depth,
+		data_width	=> read_fifo_din'length
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk			=>	CLK_I,
+		we			=>	read_fifo_we,
+		re			=>	read_fifo_re,
+		fifo_full	=>	read_fifo_full,
+		fifo_empty	=>	read_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  read_fifo_din,
+		data_r		=>  read_fifo_dout
+	);
+
+	-- DDR SDRAM Controller Core
+	inst_sdram_ctrl : entity work.sdram_ctrl_top
+	Generic map
+	(
+		BL 				=> BL,
+		f_sysclk 		=> f_sysclk
+	)
+	Port map
+	(
+	
+		sys_rst_in			=> RST_I,
+		sys_clk0_in			=> CLK_I,
+
+		sys_clk270_in		=> CLK270_I,
+		capture_clk270_in	=> CLK270VAR_I,
+		
+		-- User interface
+		u_data_vld			=> u_data_vld,
+		u_data_req_w		=> u_req_wr,
+		u_data_req_r		=> open,
+		u_tag_in			=> u_tag_in,
+		u_tag_rd			=> u_tag_rd,
+		u_tag_wr			=> u_tag_wr,
+		u_busy				=> u_busy,
+		u_addr				=> u_addr,
+		u_cmd				=> u_cmd,
+		u_cmd_we			=> u_cmd_we,
+		u_data_wr			=> u_data_w,
+		u_data_rd			=> u_data_r,
+		u_dm				=> u_dm_wr_in,
+		
+		-- SDRAM signals
+		sd_clk_p			=> sd_clk_p,
+		sd_clk_n			=> sd_clk_n,
+		sd_cke				=> sd_cke,
+		sd_cs_n				=> sd_cs_n,
+		sd_cas_n			=> sd_cas_n,
+		sd_ras_n			=> sd_ras_n,
+		sd_we_n				=> sd_we_n,
+		sd_addr				=> sd_addr,
+		sd_ba				=> sd_ba,
+		sd_dm				=> sd_dm,
+		sd_dqs				=> sd_dqs,
+		sd_data				=> sd_data
+		
+	);
+
+------------------------------------------------------------------------------------------
+	SRDY_O				<= rdy;
+	ACK_O				<= not (read_fifo_empty);
+	DAT_O				<= read_fifo_data_out;
+	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
+	write_fifo_we 		<= STB_I and WE_I and rdy;
+	write_fifo_data_in	<= DAT_I;
+	write_fifo_dm_in	<= not SEL_I;
+	cat_fifo_we			<= STB_I and rdy;
+	cmd_fifo_in			<= UCMD_WRITE when WE_I = '1' else UCMD_READ;
+	addr_fifo_in		<= ADDR_I(24 downto 2) & "0";
+	tag_fifo_in			<= "000" & ADDR_I(25);
+	
+	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
+	u_cmd				<= cmd_fifo_out;
+	u_addr				<= addr_fifo_out;
+	u_dm_wr_in			<= ("1111" & write_fifo_dm_out) when u_tag_wr(0) = '0' else (write_fifo_dm_out & "1111");
+	u_tag_in			<= tag_fifo_out;
+	u_data_w			<= write_fifo_data_out & write_fifo_data_out;
+	
+	write_fifo_re		<= u_req_wr and (not write_fifo_empty);
+	cat_fifo_re			<= u_cmd_we;
+	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
+	read_fifo_we		<= u_data_vld;
+	read_fifo_data_in	<= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32);	
+
+end architecture struct;

lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd

@@ -0,0 +1,244 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Top-level put all together
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_ctrl_top is
+	Generic
+	(
+		BL 				: natural := 2;
+		f_sysclk 		: natural := 100E6
+	);
+	Port
+	(
+		sys_rst_in			: in  STD_LOGIC;
+		sys_clk0_in			: in  STD_LOGIC;
+		sys_clk270_in		: in  STD_LOGIC;
+		capture_clk270_in	: in  STD_LOGIC;
+		
+		-- User interface
+		u_data_vld			: out STD_LOGIC;
+		u_data_req_w		: out STD_LOGIC;
+		u_data_req_r		: out STD_LOGIC;
+		u_busy				: out STD_LOGIC;
+		u_tag_in			: in  user_tag_t;
+		u_tag_rd			: out user_tag_t;
+		u_tag_wr			: out user_tag_t;
+		u_addr				: in  user_addr_t;
+		u_cmd				: in  user_cmd_t;
+		u_cmd_we			: in  STD_LOGIC;
+		u_data_wr			: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
+		u_dm				: in unsigned(SDR_DM_WIDTH-1 downto 0);
+		u_data_rd			: out unsigned(SDR_DATA_WIDTH-1 downto 0);
+		
+		-- SDRAM signals
+		sd_clk_p			: out  STD_LOGIC;
+		sd_clk_n			: out  STD_LOGIC;
+		sd_cke				: out  STD_LOGIC;
+		sd_cs_n				: out  STD_LOGIC;
+		sd_cas_n			: out  STD_LOGIC;
+		sd_ras_n			: out  STD_LOGIC;
+		sd_we_n				: out  STD_LOGIC;
+		sd_addr				: out  sdr_addr_t;
+		sd_ba				: out  sdr_ba_t;
+		sd_dm				: out  unsigned(DDR_DM_WIDTH-1 downto 0);
+		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
+		
+	);
+end sdram_ctrl_top;
+
+architecture rtl of sdram_ctrl_top is
+
+
+	signal phy_ctrl			: phy_ctrl_t;
+
+	signal u_tag			: user_tag_t;
+	signal sd_cmd_in		: sdr_cmd_t;
+	signal sd_cmd			: sdr_cmd_t;
+	signal sd_cmd_we		: std_logic;
+	signal cmd_ctrl			: sdr_cmd_lines_t;
+	signal cke				: std_logic;
+	signal ba				: unsigned(DDR_BANK_WIDTH-1 downto 0);
+	signal addr				: unsigned(DDR_ADDR_WIDTH-1 downto 0);
+
+	-- Clock generator
+
+	signal ctrl_rst			: std_logic;  
+	signal part_ctrl		: part_ctrl_t;  
+
+	-- SD command FIFO
+
+	constant CMD_FIFO_ADDR_WIDTH	: positive := 2;
+	constant CMD_FIFO_DATA_WIDTH	: positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
+	signal cmd_fifo_din				: unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
+	signal cmd_fifo_dout			: unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
+	signal cmd_fifo_re				: std_logic;
+	signal cmd_fifo_we				: std_logic;
+	signal cmd_fifo_full			: std_logic;
+	signal cmd_fifo_empty			: std_logic;
+
+	alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
+	alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
+	alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
+	alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
+
+	alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
+	alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
+	alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
+	alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
+
+begin 
+      	
+	---------------------------------
+	part_ctrl.cmd	<= cmd_ctrl;
+	part_ctrl.ba	<= ba;
+	part_ctrl.addr	<= addr;
+	part_ctrl.cke	<= cke;
+
+	---------------------------------
+	sd_cmd_we		<= not cmd_fifo_empty;
+	cmd_fifo_in		<= to_unsigned(sd_cmd_in, 4);
+	sd_cmd			<= sdr_cmd_t(to_integer(cmd_fifo_out));
+
+	---------------------------------
+	inst_reset: entity work.reset
+	port map
+	(
+		clk					=> sys_clk0_in,
+		rst_in				=> sys_rst_in,
+		rst_out				=> ctrl_rst
+	);
+	
+	-- Main controller
+	inst_sdram_ctrl : entity work.sdram_ctrl
+	Generic map 
+	(
+		f_sysclk	=> 100E6,
+		BL			=> BL
+	)
+	Port map 
+	(
+		rst				=> ctrl_rst,
+		clk				=> sys_clk0_in,
+		u_busy			=> u_busy,
+		u_tag_in		=> u_tag_in,
+		u_tag_out		=> tag_fifo_in,
+		u_cmd			=> u_cmd,
+		u_cmd_we		=> u_cmd_we,
+		u_addr			=> u_addr,
+		sdr_cmd_busy	=> cmd_fifo_full,
+		sdr_cmd			=> sd_cmd_in,
+		sdr_cmd_we		=> cmd_fifo_we,
+		col_addr		=> col_fifo_in,
+		sdr_mode		=> mode_fifo_in,
+		sdr_cke			=> cke
+	);
+   
+	-- Instantiate synchronous FIFO
+	inst_sd_cmd_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width			=> CMD_FIFO_ADDR_WIDTH,
+		data_width			=> CMD_FIFO_DATA_WIDTH,
+		almost_full_thresh	=> 2**(CMD_FIFO_ADDR_WIDTH-1),
+		almost_empty_thresh	=> 2**(CMD_FIFO_ADDR_WIDTH-1)
+	)
+	PORT MAP
+	(
+		rst			=>	ctrl_rst,
+		clk			=>	sys_clk0_in,
+		we			=>	cmd_fifo_we,
+		re			=>	cmd_fifo_re,
+		fifo_full	=>	cmd_fifo_full,
+		fifo_empty	=>	cmd_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  cmd_fifo_din,
+		data_r		=>  cmd_fifo_dout
+	);
+
+	-- DDR SDRAM command fsm
+	inst_sdram_cmd : entity work.sdram_cmd
+	Generic map
+	(
+		BL				=> BL
+	)
+	Port map
+	(
+		rst				=> ctrl_rst,
+		clk				=> sys_clk0_in,
+		u_tag_in		=> tag_fifo_out,
+		u_tag_out		=> u_tag,
+		phy_ctrl		=> phy_ctrl,
+		enable			=> cke,
+		cmd				=> sd_cmd,
+		cmd_we			=> sd_cmd_we,
+		cmd_ack			=> cmd_fifo_re,
+		sdr_cmd_ctrl	=> cmd_ctrl,
+		col_addr		=> col_fifo_out,
+		mode_word		=> mode_fifo_out,
+		sdr_ba			=> ba,
+		sdr_addr		=> addr
+	);
+   
+	-- DDR phy
+	inst_ddr_phy : entity work.ddr_phy
+	Port map
+	(
+		sys_rst			=> ctrl_rst,
+		sys_clk0		=> sys_clk0_in,
+		sys_clk270		=> sys_clk270_in,
+		u_tag_in		=> u_tag,
+		u_tag_rd		=> u_tag_rd,
+		u_tag_wr		=> u_tag_wr,
+		read_clk		=> capture_clk270_in,
+		phy_ctrl		=> phy_ctrl,
+		part_ctrl		=> part_ctrl,
+		sdr_data_req_w	=> u_data_req_w,
+		sdr_data_req_r	=> u_data_req_r,
+		sdr_data_w		=> u_data_wr,
+		sdr_dm			=> u_dm,
+		sdr_data_r		=> u_data_rd,
+		sdr_data_vld	=> u_data_vld,
+		part_clk_p		=> sd_clk_p,
+		part_clk_n		=> sd_clk_n,
+		part_addr		=> sd_addr,
+		part_ba			=> sd_ba,
+		part_dm			=> sd_dm,
+		part_dqs		=> sd_dqs,
+		part_data		=> sd_data,
+		part_cs_n		=> sd_cs_n,
+		part_we_n		=> sd_we_n,
+		part_cas_n		=> sd_cas_n,
+		part_ras_n		=> sd_ras_n,
+		part_cke		=> sd_cke
+	);
+   
+end architecture rtl;
+

lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd

@@ -0,0 +1,133 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Type definitions
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.sdram_config.all;
+
+package sdram_types is
+
+	-----------------------------------------------------------------------------------------
+	-- Table of Timing Parameters as a function of operation
+
+	-- Derived constants from sdram_config
+
+	constant DDR_DQS_WIDTH  	: positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
+	constant DDR_DM_WIDTH   	: positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
+	constant SDR_DATA_WIDTH 	: positive := 2*DDR_DATA_WIDTH;  -- 
+	constant SDR_DM_WIDTH		: positive := 2*DDR_DM_WIDTH;  -- 
+
+	subtype user_cmd_t is unsigned(1 downto 0);
+	constant UCMD_NOP			: user_cmd_t := "00";
+	constant UCMD_READ			: user_cmd_t := "01";
+	constant UCMD_WRITE			: user_cmd_t := "10";
+	constant UCMD_LMR			: user_cmd_t := "11";
+
+	subtype sdr_cmd_t is natural range 0 to 9;
+	constant SD_DESELECT		: sdr_cmd_t := 0;
+	constant SD_NOP				: sdr_cmd_t := 1;
+	constant SD_LMR				: sdr_cmd_t := 2;
+	constant SD_ACT				: sdr_cmd_t := 3;
+	constant SD_READ			: sdr_cmd_t := 4;
+	constant SD_WRITE			: sdr_cmd_t := 5;
+	constant SD_PRE				: sdr_cmd_t := 6;
+	constant SD_BST				: sdr_cmd_t := 7;
+	constant SD_AR				: sdr_cmd_t := 8;
+	constant SD_SR				: sdr_cmd_t := 9;
+	
+	type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
+	subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
+	subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
+	subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
+	subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
+
+	subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
+	subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
+	subtype col_addr_t is unsigned(8 downto 0);
+	
+	subtype cycle_cnt_t is natural range 0 to 10;
+	
+	type phy_ctrl_t is
+	record
+		drive_en		: std_logic;
+		re				: std_logic;
+		we				: std_logic;
+		utag_we			: std_logic;
+	end record phy_ctrl_t;
+
+	type sdr_cmd_lines_t is
+	record
+         cs_n    : std_logic;
+         ras_n   : std_logic;
+         cas_n   : std_logic;
+         we_n    : std_logic;
+	end record sdr_cmd_lines_t;
+
+	type part_ctrl_t is
+	record
+		cmd		: sdr_cmd_lines_t;
+		ba	 	: unsigned(DDR_BANK_WIDTH-1 downto 0);
+		addr	: unsigned(DDR_ADDR_WIDTH-1 downto 0);
+		cke		: std_logic;
+	end record part_ctrl_t;
+	
+	type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
+	constant COMMAND : part_cmd_array_t :=
+	--	 command                 cs_n     ras_qn      cas_qn      we_qn
+	(	SD_DESELECT         =>   (   '1',      '1',        '1',        '1'),
+		SD_NOP              =>   (   '0',      '1',        '1',        '1'),
+		SD_LMR              =>   (   '0',      '0',        '0',        '0'),
+		SD_ACT              =>   (   '0',      '0',        '1',        '1'),
+		SD_READ             =>   (   '0',      '1',        '0',        '1'),
+		SD_WRITE            =>   (   '0',      '1',        '0',        '0'),
+		SD_PRE              =>   (   '0',      '0',        '1',        '0'),
+		SD_BST              =>   (   '0',      '1',        '1',        '0'),
+		SD_AR               =>   (   '0',      '0',        '0',        '1'),
+		SD_SR               =>   (   '0',      '0',        '0',        '1')
+	);
+
+	type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
+	constant TIMING : part_timing_array_t :=
+	--	 command                 cycle_cnt
+	(	SD_DESELECT         =>   (     0        ),
+		SD_NOP              =>   (     0        ),
+		SD_LMR              =>   (     TMRD-1   ),
+		SD_ACT              =>   (     TRCD-1   ),
+		SD_READ             =>   (     TCAS-1   ),
+		SD_WRITE            =>   (     TWR-1    ),
+		SD_PRE              =>   (     TRP-1    ),
+		SD_BST              =>   (     0        ),
+		SD_AR               =>   (     TRFC-1   ),
+		SD_SR               =>   (     TRFC-1   )
+	);
+
+	type init_seq_t is 
+	record
+		cmd			: sdr_cmd_t;
+		mode_word	: mode_word_t;
+		wait_cycle	: natural;
+	end record init_seq_t;	
+	
+end sdram_types;

lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd

@@ -0,0 +1,860 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity tb_sdram_ctrl_frontend64_wb is
+end;
+
+architecture struct of tb_sdram_ctrl_frontend64_wb is
+
+	-- Number of user data words for simulation
+	constant CLK_PERIOD		: time := 10 ns;
+	constant BURST_LEN		: natural := 2;
+
+	signal rst				: std_logic := '1';  
+	signal clk				: std_logic := '1';  
+	signal locked			: std_logic;  
+	signal error			: std_logic;  
+	signal clk_out			: std_logic;  
+	signal clk_fb			: std_logic;  
+	signal part_clk_p		: std_logic;  
+	signal part_clk_n		: std_logic;  
+	signal part_cke			: std_logic;  
+	signal part_cs_n		: std_logic;  
+	signal part_we_n		: std_logic;  
+	signal part_ras_n		: std_logic;  
+	signal part_cas_n		: std_logic;  
+	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+	signal CLK_O			: std_logic;
+	signal CLK270_O			: std_logic;
+	signal CLK270VAR_O		: std_logic;
+	signal RST_O			: std_logic;
+	signal CYC_O			: std_logic := '0';
+	signal STB_O			: std_logic := '0';
+	signal WE_O				: std_logic := '0';
+	signal SEL_O			: unsigned(SDR_DM_WIDTH-1 downto 0);
+	signal ACK_I			: std_logic;
+	signal MRDY_O			: std_logic := '1';
+	signal SRDY_I			: std_logic;
+	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+	signal DAT_O			: unsigned(SDR_DATA_WIDTH-1 downto 0);
+
+	signal dout_rst			: std_logic := '0';
+	signal dout_reg			: unsigned(31 downto 0);
+	signal dout_cnt			: natural range 0 to 255;
+
+	signal sddat			: unsigned(31 downto 0) := (others => '-');
+	signal sdsel			: unsigned(3 downto 0) := (others => '1');
+
+	type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
+	signal sd_cmd : sd_cmd_t;
+	
+begin 
+   
+	process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
+	variable cmd : unsigned (2 downto 0);
+
+	begin
+		cmd := part_ras_n & part_cas_n & part_we_n;
+		sd_cmd <= nop;
+		if part_cs_n = '0' then
+			case cmd is
+				when "000" =>
+					sd_cmd <= lmr;
+				when "001" =>
+					sd_cmd <= ar;
+				when "010" =>
+					sd_cmd <= pre;
+				when "011" =>
+					sd_cmd <= act;
+				when "100" =>
+					sd_cmd <= write;
+				when "101" =>
+					sd_cmd <= read;
+				when "110" =>
+					sd_cmd <= bst;
+				when "111" =>
+					sd_cmd <= nop;
+				
+				when others =>
+					sd_cmd <= nop;
+
+			end case;
+		end if;
+	end process;
+	
+inst_clockgen : entity work.clockgen
+	GENERIC MAP
+	(
+		sys1_phaseshift	=> 0,
+		frequency_hz	=> 100E6
+	)
+	PORT MAP 
+	(
+		-- Clocks and Reset
+		rst				=> rst,   -- external async reset, low active
+		clk_in			=> clk,   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		=> clk_fb,   -- feedback clock
+		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	=> CLK270VAR_O,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	=> CLK_O,  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	=> CLK270_O,  -- System clock #0, dcm#0 output 270°
+		locked_out		=> locked,  -- DCM locked status
+		error_out		=> error
+	);
+
+
+	clk_fb	<= part_clk_p after 1 ns;
+	RST_O	<= not locked;
+	DAT_O	<= X"DEADBEEF" & sddat;
+	SEL_O	<= "0000" & sdsel;
+	
+	-- DDR SDRAM Controller Core
+	sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
+	GENERIC MAP
+	(
+		BL 				=> BURST_LEN,
+		f_sysclk 		=> 100E6,
+		fifo_depth		=> 3
+	)
+	PORT MAP
+	(
+		RST_I		=> RST_O,
+		CLK_I		=> CLK_O,
+		CLK270_I	=> CLK270_O,
+		CLK270VAR_I	=> CLK270VAR_O,
+		
+		CYC_I		=> CYC_O,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_I,
+		SRDY_O		=> SRDY_I,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_I,
+
+		-- SDRAM signals
+		sd_clk_p	=> part_clk_p,
+		sd_clk_n	=> part_clk_n,
+		sd_cke		=> part_cke,
+		sd_cs_n		=> part_cs_n,
+		sd_cas_n	=> part_cas_n,
+		sd_ras_n	=> part_ras_n,
+		sd_we_n		=> part_we_n,
+		sd_addr		=> part_addr,
+		sd_ba		=> part_ba,
+		sd_dm		=> part_dm,
+		sd_dqs		=> part_dqs,
+		sd_data		=> part_data
+		
+	);
+   
+   -- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_0 : entity work.mt46v16m16 
+      port map
+      (
+         dq    => std_logic_vector(part_data(15 downto 0)),
+         dqs   => std_logic_vector(part_dqs(1 downto 0)),
+         addr  => std_logic_vector(part_addr),
+         ba    => std_logic_vector(part_ba),
+         clk   => part_clk_p,
+         clk_n => part_clk_n,
+         cke   => part_cke,
+         cs_n  => part_cs_n,
+         ras_n => part_ras_n,
+         cas_n => part_cas_n,
+         we_n  => part_we_n,
+         dm    => std_logic_vector(part_dm(1 downto 0))
+	);
+
+   -- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_1 : entity work.mt46v16m16 
+      port map
+      (
+         dq    => std_logic_vector(part_data(31 downto 16)),
+         dqs   => std_logic_vector(part_dqs(3 downto 2)),
+         addr  => std_logic_vector(part_addr),
+         ba    => std_logic_vector(part_ba),
+         clk   => part_clk_p,
+         clk_n => part_clk_n,
+         cke   => part_cke,
+         cs_n  => part_cs_n,
+         ras_n => part_ras_n,
+         cas_n => part_cas_n,
+         we_n  => part_we_n,
+         dm    => std_logic_vector(part_dm(3 downto 2))
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+read_register:
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if dout_rst = '1' then
+				dout_cnt <= 0;
+			elsif ACK_I = '1' and WE_O = '0' then
+				dout_reg	<= DAT_I(31 downto 0);
+				dout_cnt 	<= dout_cnt + 1;
+			end if;
+		end if;
+	end process;
+		
+------------------------------------------------------------------------------------------
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		
+		wait until RST_O = '0';
+		-- 8 single cycles
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		sddat	<= X"1234_0000";
+		ADDR_O	<= X"0000_0000";
+		
+		for i in 0 to 8192 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			sddat	<= sddat + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+	
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O);
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+		
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		sdsel	<= "0011";
+		ADDR_O	<= X"0000_0080";
+		sddat	<= X"DEADBEEF";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O);
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0080";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+		
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+
+		for k in 0 to 3 loop
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+
+		for k in 0 to 3 loop
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			sdsel	<= "1111";
+			sddat	<= X"1111_0000";
+			ADDR_O	<= X"0000_0000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				sddat	<= sddat + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			sdsel	<= "1111";
+			sddat	<= X"2222_0000";
+			ADDR_O	<= X"0000_0400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				sddat	<= sddat + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			sdsel	<= "1111";
+			sddat	<= X"3333_0000";
+			ADDR_O	<= X"0000_0800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				sddat	<= sddat + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			sdsel	<= "1111";
+			sddat	<= X"4444_0000";
+			ADDR_O	<= X"0000_0C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				sddat	<= sddat + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			sdsel	<= "1111";
+			sddat	<= X"1111_0000";
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				sddat	<= sddat + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			sdsel	<= "1111";
+			sddat	<= X"2222_0000";
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				sddat	<= sddat + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			sdsel	<= "1111";
+			sddat	<= X"3333_0000";
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				sddat	<= sddat + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			sdsel	<= "1111";
+			sddat	<= X"4444_0000";
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				sddat	<= sddat + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
+		wait; 
+	
+	end process;
+	
+end architecture struct;

lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd

@@ -0,0 +1,855 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity tb_sdram_ctrl_frontend_wb is
+end;
+
+architecture struct of tb_sdram_ctrl_frontend_wb is
+
+	-- Number of user data words for simulation
+	constant CLK_PERIOD		: time := 10 ns;
+	constant BURST_LEN		: natural := 2;
+
+	signal rst				: std_logic := '1';  
+	signal clk				: std_logic := '1';  
+	signal locked			: std_logic;  
+	signal error			: std_logic;  
+	signal clk_out			: std_logic;  
+	signal clk_fb			: std_logic;  
+	signal part_clk_p		: std_logic;  
+	signal part_clk_n		: std_logic;  
+	signal part_cke			: std_logic;  
+	signal part_cs_n		: std_logic;  
+	signal part_we_n		: std_logic;  
+	signal part_ras_n		: std_logic;  
+	signal part_cas_n		: std_logic;  
+	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+	signal CLK_O			: std_logic;
+	signal CLK270_O			: std_logic;
+	signal CLK270VAR_O		: std_logic;
+	signal RST_O			: std_logic;
+	signal CYC_O			: std_logic := '0';
+	signal STB_O			: std_logic := '0';
+	signal WE_O				: std_logic := '0';
+	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I			: std_logic;
+	signal MRDY_O			: std_logic := '1';
+	signal SRDY_I			: std_logic;
+	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I			: unsigned(31 downto 0);
+	signal DAT_O			: unsigned(31 downto 0) := (others => '-');
+
+	signal dout_rst			: std_logic := '0';
+	signal dout_reg			: unsigned(31 downto 0);
+	signal dout_cnt			: natural range 0 to 255;
+
+	type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
+	signal sd_cmd : sd_cmd_t;
+	
+begin 
+   
+	process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
+	variable cmd : unsigned (2 downto 0);
+
+	begin
+		cmd := part_ras_n & part_cas_n & part_we_n;
+		sd_cmd <= nop;
+		if part_cs_n = '0' then
+			case cmd is
+				when "000" =>
+					sd_cmd <= lmr;
+				when "001" =>
+					sd_cmd <= ar;
+				when "010" =>
+					sd_cmd <= pre;
+				when "011" =>
+					sd_cmd <= act;
+				when "100" =>
+					sd_cmd <= write;
+				when "101" =>
+					sd_cmd <= read;
+				when "110" =>
+					sd_cmd <= bst;
+				when "111" =>
+					sd_cmd <= nop;
+				
+				when others =>
+					sd_cmd <= nop;
+
+			end case;
+		end if;
+	end process;
+	
+inst_clockgen : entity work.clockgen
+	GENERIC MAP
+	(
+		sys1_phaseshift	=> 0,
+		frequency_hz	=> 100E6
+	)
+	PORT MAP 
+	(
+		-- Clocks and Reset
+		rst				=> rst,   -- external async reset, low active
+		clk_in			=> clk,   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		=> clk_fb,   -- feedback clock
+		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	=> CLK270VAR_O,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	=> CLK_O,  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	=> CLK270_O,  -- System clock #0, dcm#0 output 270°
+		locked_out		=> locked,  -- DCM locked status
+		error_out		=> error
+	);
+
+
+	clk_fb	<= part_clk_p after 1 ns;
+	RST_O	<= not locked;
+	
+	-- DDR SDRAM Controller Core
+	sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
+	GENERIC MAP
+	(
+		BL 				=> BURST_LEN,
+		f_sysclk 		=> 100E6,
+		fifo_depth		=> 3
+	)
+	PORT MAP
+	(
+		RST_I		=> RST_O,
+		CLK_I		=> CLK_O,
+		CLK270_I	=> CLK270_O,
+		CLK270VAR_I	=> CLK270VAR_O,
+		
+		CYC_I		=> CYC_O,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_I,
+		SRDY_O		=> SRDY_I,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_I,
+
+		-- SDRAM signals
+		sd_clk_p	=> part_clk_p,
+		sd_clk_n	=> part_clk_n,
+		sd_cke		=> part_cke,
+		sd_cs_n		=> part_cs_n,
+		sd_cas_n	=> part_cas_n,
+		sd_ras_n	=> part_ras_n,
+		sd_we_n		=> part_we_n,
+		sd_addr		=> part_addr,
+		sd_ba		=> part_ba,
+		sd_dm		=> part_dm,
+		sd_dqs		=> part_dqs,
+		sd_data		=> part_data
+		
+	);
+   
+   -- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_0 : entity work.mt46v16m16 
+      port map
+      (
+         dq    => std_logic_vector(part_data(15 downto 0)),
+         dqs   => std_logic_vector(part_dqs(1 downto 0)),
+         addr  => std_logic_vector(part_addr),
+         ba    => std_logic_vector(part_ba),
+         clk   => part_clk_p,
+         clk_n => part_clk_n,
+         cke   => part_cke,
+         cs_n  => part_cs_n,
+         ras_n => part_ras_n,
+         cas_n => part_cas_n,
+         we_n  => part_we_n,
+         dm    => std_logic_vector(part_dm(1 downto 0))
+	);
+
+   -- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_1 : entity work.mt46v16m16 
+      port map
+      (
+         dq    => std_logic_vector(part_data(31 downto 16)),
+         dqs   => std_logic_vector(part_dqs(3 downto 2)),
+         addr  => std_logic_vector(part_addr),
+         ba    => std_logic_vector(part_ba),
+         clk   => part_clk_p,
+         clk_n => part_clk_n,
+         cke   => part_cke,
+         cs_n  => part_cs_n,
+         ras_n => part_ras_n,
+         cas_n => part_cas_n,
+         we_n  => part_we_n,
+         dm    => std_logic_vector(part_dm(3 downto 2))
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+read_register:
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if dout_rst = '1' then
+				dout_cnt <= 0;
+			elsif ACK_I = '1' and WE_O = '0' then
+				dout_reg	<= DAT_I;
+				dout_cnt 	<= dout_cnt + 1;
+			end if;
+		end if;
+	end process;
+		
+------------------------------------------------------------------------------------------
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		
+		wait until RST_O = '0';
+		-- 8 single cycles
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		DAT_O	<= X"1234_0000";
+		ADDR_O	<= X"0000_0000";
+		
+		for i in 0 to 8192 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+	
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O);
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+		
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "0011";
+		ADDR_O	<= X"0000_0080";
+		DAT_O	<= X"DEADBEEF";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O);
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0080";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+		
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+
+		for k in 0 to 3 loop
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+
+		for k in 0 to 3 loop
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SEL_O	<= "1111";
+			DAT_O	<= X"1111_0000";
+			ADDR_O	<= X"0000_0000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SEL_O	<= "1111";
+			DAT_O	<= X"2222_0000";
+			ADDR_O	<= X"0000_0400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SEL_O	<= "1111";
+			DAT_O	<= X"3333_0000";
+			ADDR_O	<= X"0000_0800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SEL_O	<= "1111";
+			DAT_O	<= X"4444_0000";
+			ADDR_O	<= X"0000_0C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SEL_O	<= "1111";
+			DAT_O	<= X"1111_0000";
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SEL_O	<= "1111";
+			DAT_O	<= X"2222_0000";
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SEL_O	<= "1111";
+			DAT_O	<= X"3333_0000";
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SEL_O	<= "1111";
+			DAT_O	<= X"4444_0000";
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
+		wait; 
+	
+	end process;
+	
+end architecture struct;

lib/SSRAM/sim/tb_ssram_frontend_wb.fdo

@@ -0,0 +1,17 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+# Top and TB
+vcom -explicit  -93 "../src/package_utility.vhd"
+vcom -explicit  -93 "../src/CY7C1354B.vhd"
+vcom -explicit  -93 "../src/ssram_frontend_wb.vhd"
+vcom -explicit  -93 "../src/tb_ssram_frontend_wb.vhd"
+
+vsim -t 1ps   -lib work tb_ssram_frontend_wb
+do {tb_ssram_frontend_wb.wdo}
+view wave
+view structure
+view signals
+run 6us
+			 

lib/SSRAM/sim/tb_ssram_frontend_wb.wdo

@@ -0,0 +1,47 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/clk_o
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/rst_o
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/cyc_o
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/stb_o
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/we_o
+add wave -noupdate -format Literal /tb_ssram_frontend_wb/sel_o
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ack_i
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/mrdy_o
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_d
+add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_dp
+add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_a
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_cke_n
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_adv
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_mode
+add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_bw_n
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_we_n
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_oe_n
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_ce_n
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_zz
+add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dout_reg
+add wave -noupdate -format Literal -radix unsigned /tb_ssram_frontend_wb/dout_cnt
+add wave -noupdate -format Literal /tb_ssram_frontend_wb/inst_ssram_frontend_wb/vld_pipe
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk_fb
+add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1343191 ps} 0} {{Cursor 2} {178651436 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {6300 ns}

lib/SSRAM/src/CY7C1354B.vhd

@@ -0,0 +1,388 @@
+-----------------------------------------------------------------------------------------
+--
+--     File Name:  CY7C1354B.VHD
+--       Version:  2.0
+--          Date:  Nov 22nd, 2004
+--         Model:  BUS Functional
+--     
+-- 
+--        Author:  RKF 
+--       Company:  Cypress Semiconductor
+--         Model:  CY7C1354B (256k x 36)
+--          Mode:  Pipelined
+--
+--   Description:  NoBL SRAM VHDL Model
+--
+--    Limitation:  None
+--
+--          Note:  - BSDL Model available separately
+--                 - Set simulator resolution to "ps" timescale
+--
+--    Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
+--                 WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
+--                 IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+--                 A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+--                 Copyright (c) 2004 Cypress Semiconductor 
+--                 All rights reserved
+--
+--     Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor
+--
+--  Rev  Author          Date        Changes
+--  ---  --------       -------     ----------  
+--  2.0  RKF 		11/22/2004  - Second Release
+--				    - Fully Tested with New Test Bench and Test Vectors	
+-----------------------------------------------------------------------------------------
+
+LIBRARY ieee,work;
+	USE ieee.std_logic_1164.all;
+	USE ieee.std_logic_unsigned.all;
+	Use IEEE.Std_Logic_Arith.all;
+--	Use work.all;   
+	USE work.package_utility.all;   
+
+ENTITY cy7c1354 IS
+
+    GENERIC (
+
+        -- Constant parameters
+	addr_bits : INTEGER := 18;
+	data_bits : INTEGER := 32;
+	par_bits : INTEGER := 4;
+
+        -- Timing parameters for -5 (225 Mhz)
+--         tCYC	: TIME    := 4.4 ns;
+--         tCH	: TIME    :=  1.8 ns;
+--         tCL	: TIME    :=  1.8 ns;
+--         tCO	: TIME    :=  2.8 ns;
+--         tAS	: TIME    :=  1.4 ns;
+--         tCENS	: TIME    :=  1.4 ns;
+--         tWES	: TIME    :=  1.4 ns;
+--         tDS	: TIME    :=  1.4 ns;
+--         tAH	: TIME    :=  0.4 ns;
+--         tCENH	: TIME    :=  0.4 ns;
+--         tWEH	: TIME    :=  0.4 ns;
+--         tDH	: TIME    :=  0.4 ns
+
+
+     
+        -- Timing parameters for -6 (200 Mhz)
+        --tCYC	: TIME    := 5.0 ns;
+        --tCH	: TIME    :=  2.0 ns;
+        --tCL	: TIME    :=  2.0 ns;
+        --tCO	: TIME    :=  3.2 ns;
+        --tAS	: TIME    :=  1.5 ns;
+        --tCENS	: TIME    :=  1.5 ns;
+        --tWES	: TIME    :=  1.5 ns;
+        --tDS	: TIME    :=  1.5 ns;
+        --tAH	: TIME    :=  0.5 ns;
+        --tCENH	: TIME    :=  0.5 ns;
+        --tWEH	: TIME    :=  0.5 ns;
+        --tDH	: TIME    :=  0.5 ns
+         
+
+        -- Timing parameters for -7 (166 Mhz)
+        tCYC	: TIME    := 6.0 ns;
+        tCH	: TIME    :=  2.4 ns;
+        tCL	: TIME    :=  2.4 ns;
+        tCO	: TIME    :=  3.5 ns;
+        tAS	: TIME    :=  1.5 ns;
+        tCENS	: TIME    :=  1.5 ns;
+        tWES	: TIME    :=  1.5 ns;
+        tDS	: TIME    :=  1.5 ns;
+        tAH	: TIME    :=  0.5 ns;
+        tCENH	: TIME    :=  0.5 ns;
+        tWEH	: TIME    :=  0.5 ns;
+        tDH	: TIME    :=  0.5 ns
+
+       
+
+         );
+
+    -- Port Declarations
+    PORT (
+	Dq	: INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0);   	-- Data I/O
+	Dpq	: INOUT STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0);   	-- Data parity I/O
+	Addr	: IN	STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0);   	-- Address
+	Mode	: IN	STD_LOGIC	:= '1'; 			-- Burst Mode
+	Clk	: IN	STD_LOGIC;                                   -- Clk
+	CEN_n	: IN	STD_LOGIC;                                   -- CEN#
+	AdvLd_n	: IN	STD_LOGIC;                                   -- Adv/Ld#
+	Bwa_n	: IN	STD_LOGIC;                                   -- Bwa#
+	Bwb_n	: IN	STD_LOGIC;                                   -- BWb#
+	Bwc_n	: IN	STD_LOGIC;                                   -- Bwc#
+	Bwd_n	: IN	STD_LOGIC;                                   -- BWd#
+	Rw_n	: IN	STD_LOGIC;                                   -- RW#
+	Oe_n	: IN	STD_LOGIC;                                   -- OE#
+	Ce1_n	: IN	STD_LOGIC;                                   -- CE1#
+	Ce2	: IN	STD_LOGIC;                                   -- CE2
+	Ce3_n	: IN	STD_LOGIC;                                   -- CE3#
+	Zz	: IN	STD_LOGIC                                    -- Snooze Mode
+    );
+END cy7c1354;
+
+ARCHITECTURE behave OF cy7c1354 IS
+    SIGNAL ce : STD_LOGIC := '0';
+    SIGNAL doe : STD_LOGIC := '0';
+    SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
+    SIGNAL dout_p : STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
+    SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
+
+BEGIN
+
+
+    ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2;
+
+    doe <= NOT(Oe_n) AND NOT(Zz);
+
+    -- Output Buffers
+    WITH doe SELECT
+        Dq <= TRANSPORT dout            AFTER (tCO) WHEN '1',
+                        (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
+    
+    WITH doe SELECT
+        Dpq <= TRANSPORT dout_p            AFTER (tCO) WHEN '1',
+                        (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
+                           
+ 
+    -- Check for Clock Timing Violation
+    clk_check : PROCESS
+        VARIABLE clk_high, clk_low : TIME := 0 ns;
+    BEGIN
+        WAIT ON Clk;
+            IF Clk = '1' AND NOW >= tCYC THEN
+                ASSERT (NOW - clk_low >= tCH)
+                    REPORT "Clk width low - tCH violation"
+                    SEVERITY ERROR;
+                ASSERT (NOW - clk_high >= tCYC)
+                    REPORT "Clk period high - tCYC violation"
+                    SEVERITY ERROR;
+                clk_high := NOW;
+            ELSIF Clk = '0' AND NOW /= 0 ns THEN
+                ASSERT (NOW - clk_high >= tCL)
+                    REPORT "Clk width high - tCL violation"
+                    SEVERITY ERROR;
+                ASSERT (NOW - clk_low >= tCYC)
+                    REPORT "Clk period low - tCYC violation"
+                    SEVERITY ERROR;
+                clk_low := NOW;
+            END IF;
+    END PROCESS;
+
+    -- Check for Setup Timing Violation
+    setup_check : PROCESS
+    BEGIN
+        WAIT ON Clk;
+        IF Clk = '1' and (Ce1_n = '0' and Ce2 = '1' and Ce3_n = '0') THEN
+           	ASSERT (Addr'LAST_EVENT >= tAS)
+           	    REPORT "Addr - tAS violation"
+           	    SEVERITY ERROR;
+            ASSERT (CEN_n'LAST_EVENT >= tCENS)
+                REPORT "CKE# - tCENS violation"
+                SEVERITY ERROR;
+            ASSERT (Ce1_n'LAST_EVENT >= tWES)
+                REPORT "CE1# - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (Ce2'LAST_EVENT >= tWES)
+                REPORT "CE2 - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (Ce3_n'LAST_EVENT >= tWES)
+                REPORT "CE3# - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (AdvLd_n'LAST_EVENT >= tWES)
+                REPORT "ADV/LD# - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (Rw_n'LAST_EVENT >= tWES)
+                REPORT "RW# - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (Bwa_n'LAST_EVENT >= tWES)
+                REPORT "BWa# - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (Bwb_n'LAST_EVENT >= tWES)
+                REPORT "BWb# - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (Bwc_n'LAST_EVENT >= tWES)
+                REPORT "BWc# - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (Bwd_n'LAST_EVENT >= tWES)
+                REPORT "BWd# - tWES violation"
+                SEVERITY ERROR;
+            ASSERT (Dq'LAST_EVENT >= tDS)
+                REPORT "Dq - tDS violation"
+                SEVERITY ERROR;
+        END IF;
+    END PROCESS;
+
+    -- Check for Hold Timing Violation
+    hold_check : PROCESS
+    BEGIN
+        WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH);
+        IF Clk'DELAYED(tAH) = '1' THEN
+            ASSERT (Addr'LAST_EVENT > tAH)
+                REPORT "Addr - tAH violation"
+                SEVERITY ERROR;
+        END IF;
+        IF Clk'DELAYED(tCENH) = '1' THEN
+            ASSERT (CEN_n'LAST_EVENT > tCENH)
+                REPORT "CKE# - tCENH violation"
+                SEVERITY ERROR;
+        END IF;
+        IF Clk'DELAYED(tDH) = '1' THEN
+            ASSERT (Dq'LAST_EVENT > tDH)
+                REPORT "Dq - tDH violation"
+                SEVERITY ERROR;
+        END IF;
+        IF Clk'DELAYED(tWEH) = '1' THEN
+            ASSERT (Ce1_n'LAST_EVENT > tWEH)
+                REPORT "CE1# - tWEH violation"
+                SEVERITY ERROR;
+            ASSERT (Ce2'LAST_EVENT > tWEH)
+                REPORT "CE2 - tWEH violation"
+                SEVERITY ERROR;
+            ASSERT (Ce3_n'LAST_EVENT > tWEH)
+                REPORT "CE3 - tWEH violation"
+                SEVERITY ERROR;
+            ASSERT (AdvLd_n'LAST_EVENT > tWEH)
+                REPORT "ADV/LD# - tWEH violation"
+                SEVERITY ERROR;
+            ASSERT (Rw_n'LAST_EVENT > tWEH)
+                        REPORT "RW# - tWEH violation"
+                SEVERITY ERROR;
+            ASSERT (Bwa_n'LAST_EVENT > tWEH)
+                REPORT "BWa# - tWEH violation"
+                SEVERITY ERROR;
+            ASSERT (Bwb_n'LAST_EVENT > tWEH)
+                REPORT "BWb# - tWEH violation"
+                SEVERITY ERROR;
+            ASSERT (Bwc_n'LAST_EVENT > tWEH)
+                REPORT "BWc# - tWEH violation"
+                SEVERITY ERROR;
+            ASSERT (Bwd_n'LAST_EVENT > tWEH)
+                REPORT "BWd# - tWEH violation"
+                SEVERITY ERROR;
+        END IF;
+        
+    END PROCESS;
+
+   -- Main Program
+    main : PROCESS 
+
+    TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (((data_bits+par_bits) / 4) - 1 DOWNTO 0);
+       
+        VARIABLE Addr_in 	: STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
+        VARIABLE first_Addr 	: STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Addr_read 	: STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Addr_write 	: STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
+        VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0';
+        VARIABLE bank0 		: memory_array;
+        VARIABLE bank1 		: memory_array;
+        VARIABLE bank2 		: memory_array;
+        VARIABLE bank3 		: memory_array;
+
+        VARIABLE ce_in 		: STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE rw_in 		: STD_LOGIC_VECTOR (2 DOWNTO 0) := "111";
+        VARIABLE bwa_in 	: STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
+        VARIABLE bwb_in 	: STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
+        VARIABLE bwc_in 	: STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
+        VARIABLE bwd_in 	: STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
+        VARIABLE bcnt 		: STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+
+    BEGIN
+        WAIT ON Clk;
+        IF Clk'EVENT AND Clk = '1' THEN
+            IF CEN_n = '0' AND Zz = '0' THEN
+                -- Write Address Register
+                Addr_write := Addr_read;
+
+                -- Read Address Register
+                Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0;
+
+                -- Address Register
+                IF AdvLd_n = '0' and ce = '1' THEN
+                  Addr_in := Addr;
+                  first_Addr := Addr(1 DOWNTO 0);
+                  bcnt := Addr(1 DOWNTO 0);
+              END IF;
+
+
+                -- Burst Logic
+              IF Mode = '0' AND AdvLd_n = '1' THEN
+                  bcnt := bcnt + 1;
+              ELSIF Mode = '1' AND AdvLd_n = '1' THEN
+			IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN
+                  		bcnt := bcnt + 1;
+			ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN
+                  		bcnt := bcnt - 1;
+              		END IF;
+              END IF;
+				
+
+                  bAddr1 := bcnt (1);
+                  bAddr0 := bcnt (0);
+
+                -- Read Logic
+                ce_in (0) := ce_in (1);
+
+                IF AdvLd_n = '0' THEN
+                    ce_in (1) := ce;
+                END IF;
+
+                rw_in (0) := rw_in (1);
+                rw_in (1) := rw_in (2);
+
+                IF AdvLd_n = '0' THEN
+                    rw_in (2) := NOT(ce AND NOT(Rw_n));
+                END IF;
+
+                -- Write Registry and Data Coherency Control Logic
+                bwa_in (0) := bwa_in (1);
+                bwb_in (0) := bwb_in (1);
+                bwc_in (0) := bwc_in (1);
+                bwd_in (0) := bwd_in (1);
+                bwa_in (1) := bwa_in (2);
+                bwb_in (1) := bwb_in (2);
+                bwc_in (1) := bwc_in (2);
+                bwd_in (1) := bwd_in (2);
+                bwa_in (2) := Bwa_n;
+                bwb_in (2) := Bwb_n;
+                bwc_in (2) := Bwc_n;
+                bwd_in (2) := Bwd_n;
+
+                -- Write Data to Memory
+                IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN
+                    bank0 (CONV_INTEGER1 (Addr_write)) := Dpq(0) & Dq ( (data_bits / 4) - 1 DOWNTO  0);
+                END IF;
+                IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN
+                    bank1 (CONV_INTEGER1 (Addr_write)) := Dpq(1) & Dq ((data_bits / 2 - 1) DOWNTO  (data_bits / 4));
+                END IF;
+                IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN
+                    bank2 (CONV_INTEGER1 (Addr_write)) := Dpq(2) & Dq ((3 * (data_bits / 4)) - 1 DOWNTO  (data_bits / 2));
+                END IF;
+                IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN
+                    bank3 (CONV_INTEGER1 (Addr_write)) := Dpq(3) & Dq (data_bits - 1 DOWNTO  (3 * (data_bits / 4)));
+                END IF;
+            END IF;
+
+		Addr_read_sig	<= Addr_read;
+
+            -- Read Data from Memory Array
+            IF ce_in (0) = '1' AND rw_in (1) = '1' THEN
+                dout ((data_bits / 4) - 1 DOWNTO  0) <= bank0 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO  0);
+                dout ((data_bits / 2 - 1) DOWNTO  (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO  0);
+                dout ((3 * (data_bits / 4)) - 1 DOWNTO  (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO  0);
+                dout (data_bits - 1 DOWNTO  (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO  0);
+                dout_p(0)	<= bank0 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
+                dout_p(1)	<= bank1 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
+                dout_p(2)	<= bank2 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
+                dout_p(3)	<= bank3 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
+            ELSE
+                dout <= (OTHERS => 'Z');
+                dout_p <= (OTHERS => 'Z');
+            END IF;
+       END IF;
+    END PROCESS;
+
+END behave;
+
+
+

lib/SSRAM/src/package_utility.vhd

@@ -0,0 +1,73 @@
+--****************************************************************
+--**    MODEL   :     package_utility                           **
+--**    COMPANY :     Cypress Semiconductor			**
+--**    REVISION:     1.0 Created new package utility model     **
+--**                                                            **
+--****************************************************************
+Library ieee,work; 
+   Use ieee.std_logic_1164.all;
+   Use IEEE.Std_Logic_Arith.all;
+   Use IEEE.std_logic_TextIO.all;
+   --- Use work.package_timing.all;
+
+Library Std;
+   Use STD.TextIO.all;
+
+Package package_utility is
+
+FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR;
+FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER;
+
+End; -- package package_utility
+
+Package body package_utility is  
+
+
+------------------------------------------------------------------------------------------------
+--Converts string into std_logic_vector 
+------------------------------------------------------------------------------------------------
+
+FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS
+	VARIABLE result : STD_LOGIC_VECTOR(S'RANGE);
+		BEGIN
+			FOR i	IN S'RANGE LOOP
+				IF 	S(i) = '0' THEN
+					result(i) := '0'; 
+				ELSIF S(i) = '1' THEN 
+					result(i) := '1';
+				ELSIF S(i) = 'X' THEN
+					result(i) := 'X';
+				ELSE
+					result(i) := 'Z';
+				END IF;
+			END LOOP;
+		RETURN result;
+END convert_string;
+
+------------------------------------------------------------------------------------------------
+--Converts std_logic_vector into integer
+------------------------------------------------------------------------------------------------
+
+FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS
+		VARIABLE result : INTEGER := 0;
+		BEGIN
+			FOR i IN S'RANGE LOOP
+				IF S(i) = '1' THEN
+					result := result + (2**i);
+				ELSIF S(i) = '0' THEN
+					result := result;
+				ELSE
+					result := 0;
+				END IF;
+			END LOOP;
+			RETURN result;
+		END CONV_INTEGER1;	
+
+
+
+
+end package_utility;   
+
+
+
+

lib/SSRAM/src/ssram_frontend_wb.vhd

@@ -0,0 +1,181 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+ENTITY ssram_frontend_wb IS
+	Generic
+	(
+		latency			: natural := 2;		-- clock cycles
+		addr_width		: natural := 20;
+		data_width		: natural := 32;
+		parity_width	: natural := 4
+	);
+	Port
+	(
+		-- J-Bus domain
+		CLK_I			: in  STD_LOGIC;
+		RST_I			: in  STD_LOGIC;
+		CYC_I			: in  STD_LOGIC;
+		STB_I			: in  STD_LOGIC;
+		SEL_I			: in  unsigned(3 downto 0);
+		WE_I			: in  STD_LOGIC;
+		ACK_O			: out STD_LOGIC;
+		SRDY_O			: out STD_LOGIC;
+		MRDY_I			: in  STD_LOGIC;
+		ADDR_I			: in  unsigned(31 downto 0);
+		DAT_I			: in  unsigned(31 downto 0);
+		DAT_O			: out unsigned(31 downto 0);
+		
+		-- Sync SRAM domain
+		ssram_clk_o		: out std_logic;
+		ssram_clk_fb	: in  std_logic;
+		ssram_cke_n		: out std_logic;
+		ssram_ce_n		: out std_logic;
+		ssram_oe_n		: out std_logic;
+		ssram_we_n		: out std_logic;
+		ssram_adv		: out std_logic;
+		ssram_mode		: out std_logic;
+		ssram_zz		: out std_logic;
+		ssram_a			: out unsigned(addr_width-1 downto 0);
+		ssram_d			: inout unsigned(data_width-1 downto 0);
+		ssram_dp		: inout unsigned(parity_width-1 downto 0);
+		ssram_bw_n		: out unsigned(3 downto 0)
+	);
+END ssram_frontend_wb;
+
+ARCHITECTURE behavior OF ssram_frontend_wb IS
+
+	constant topad	: time := 3 ns;
+	subtype ssram_d_t is unsigned(data_width+parity_width-1 downto 0);
+	type data_pipe_t is array (latency downto 0) of ssram_d_t;
+
+	signal ssram_clk	: std_logic;
+	signal dcm_locked	: std_logic;
+	signal dcm_clk0		: std_logic;
+	signal dcm_clk1		: std_logic;
+	signal data_en		: std_logic;
+	signal drive		: std_logic;
+	signal vld_pipe		: unsigned(latency downto 0);
+	signal drive_pipe	: unsigned(latency downto 0);
+	signal data_pipe	: data_pipe_t;
+	signal ssram_dout	: ssram_d_t;
+	
+begin
+
+	SRDY_O							<= CYC_I and dcm_locked;
+	ACK_O							<= vld_pipe(vld_pipe'left);
+	DAT_O(data_width-1 downto 0)	<= ssram_d;
+
+	data_en							<= CYC_I and STB_I;
+	ssram_dout						<= "0000" & DAT_I(data_width-1 downto 0);
+	drive							<= drive_pipe(drive_pipe'left);
+	
+	ssram_clk_o						<= ssram_clk after topad;
+	ssram_cke_n						<= not dcm_locked after topad;
+	ssram_oe_n						<= not vld_pipe(vld_pipe'left-1) after topad;
+	
+inst_clock_out : ODDR
+	generic map
+	(
+		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
+		INIT => '0',						-- Initial value for Q port ('1' or '0')
+		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
+	) 										
+	port map (
+		Q	=> ssram_clk,	-- 1-bit DDR output
+		C	=> dcm_clk1,	-- 1-bit clock input
+		CE	=> '1',			-- 1-bit clock enable input
+		D1	=> '1',			-- 1-bit data input (positive edge)
+		D2	=> '0',			-- 1-bit data input (negative edge)
+		R	=> '0',			-- 1-bit reset input
+		S	=> '0' 			-- 1-bit set input
+	);
+
+ssram_bufg: bufg
+	port map
+	(
+		o  => dcm_clk1,  
+		i  => dcm_clk0
+	);
+
+inst_DCM_BASE_0 : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+									 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => dcm_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => open,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => open,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => dcm_locked,     -- DCM LOCK status output
+		CLKFB => ssram_clk_fb,       -- DCM clock feedback
+		CLKIN => CLK_I,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => RST_I            -- DCM asynchronous reset input
+	);
+
+
+data_valid_pipeline:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				vld_pipe	<= (others => '0');
+			else
+				vld_pipe	<= vld_pipe(vld_pipe'left-1 downto 0) & (data_en and MRDY_I and not WE_I);
+			end if;
+		end if;
+	end process;
+
+data_out_pipeline:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ssram_ce_n	<= '1' after topad;
+				ssram_we_n	<= '1' after topad;
+				ssram_adv	<= '0' after topad;
+				ssram_mode	<= '0' after topad;
+				ssram_zz	<= '1' after topad;
+				drive_pipe	<= (others => '0');
+			elsif dcm_locked = '1' then
+				ssram_ce_n	<= not data_en after topad;
+				ssram_we_n	<= not (WE_I and data_en) after topad;
+				ssram_adv	<= '0' after topad;
+				ssram_mode	<= '0' after topad;
+				ssram_zz	<= '0' after topad;
+				ssram_a		<= ADDR_I(addr_width-1 downto 0) after topad;
+				ssram_bw_n	<= not SEL_I after topad;		
+				drive_pipe	<= drive_pipe(drive_pipe'left-1 downto 0) & (data_en and WE_I);
+				data_pipe	<= data_pipe(data_pipe'left-1 downto 0) & ssram_dout;
+			end if;	
+		end if;
+	end process;
+	
+	ssram_d		<= data_pipe(data_pipe'left)(data_width-1 downto 0) after topad when drive = '1' else (others => 'Z') after topad;
+	ssram_dp	<= data_pipe(data_pipe'left)(data_width+parity_width-1 downto data_width) after topad when drive = '1' else (others => 'Z') after topad;
+	
+end behavior;

lib/SSRAM/src/tb_ssram_frontend_wb.vhd

@@ -0,0 +1,457 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.package_utility.all;   
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+ENTITY tb_ssram_frontend_wb IS
+END tb_ssram_frontend_wb;
+
+ARCHITECTURE behavior OF tb_ssram_frontend_wb IS 
+
+	constant CLK_PERIOD : time := 10 ns;
+	signal CLK_O	: std_logic := '1';
+	signal RST_O	: std_logic := '1';
+	signal CYC_O	: std_logic := '0';
+	signal STB_O	: std_logic := '0';
+	signal WE_O		: std_logic := '0';
+	signal SEL_O	: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I	: std_logic;
+	signal MRDY_O	: std_logic := '1';
+	signal SRDY_I	: std_logic;
+	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I	: unsigned(31 downto 0);
+	signal DAT_O	: unsigned(31 downto 0) := (others => '-');
+
+    SIGNAL ssram_d		: unsigned (32 - 1 DOWNTO 0) := (OTHERS => 'Z');
+    SIGNAL ssram_dp		: unsigned (4 - 1 DOWNTO 0) := (OTHERS => 'Z');
+    SIGNAL ssram_a		: unsigned (20 - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL ssram_clk	: STD_LOGIC := '0';
+    SIGNAL ssram_cke_n	: STD_LOGIC;
+    SIGNAL ssram_adv	: STD_LOGIC;
+    SIGNAL ssram_mode	: STD_LOGIC;
+    SIGNAL ssram_bw_n	: unsigned(3 downto 0);
+    SIGNAL ssram_we_n	: STD_LOGIC;
+    SIGNAL ssram_oe_n	: STD_LOGIC;
+    SIGNAL ssram_ce_n	: STD_LOGIC;
+    SIGNAL ssram_zz		: STD_LOGIC;
+
+    SIGNAL ssram_clk_fb	: STD_LOGIC;
+
+	signal dout_rst		: std_logic := '0';
+	signal dout_reg		: unsigned(31 downto 0);
+	signal dout_cnt		: natural range 0 to 255;
+
+BEGIN
+
+	ssram_clk_fb	<= ssram_clk after 0.5 ns;
+
+inst_ssram_frontend_wb : entity work.ssram_frontend_wb
+	GENERIC MAP
+	(
+		addr_width		=> 20,
+		data_width		=> 32,
+		parity_width	=> 4
+	)
+	PORT MAP
+	(
+		-- J-Bus domain
+		RST_I		=> RST_O,
+		CLK_I		=> CLK_O,
+		CYC_I		=> CYC_O,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_I,
+		SRDY_O		=> SRDY_I,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_I,
+		
+		-- Sync SRAM domain
+		ssram_clk_o		=> ssram_clk,
+		ssram_clk_fb	=> ssram_clk_fb,
+		ssram_cke_n		=> ssram_cke_n,
+		ssram_ce_n		=> ssram_ce_n,
+		ssram_oe_n		=> ssram_oe_n,
+		ssram_we_n		=> ssram_we_n,
+		ssram_adv		=> ssram_adv,
+		ssram_mode		=> ssram_mode,
+		ssram_zz		=> ssram_zz,
+		ssram_a			=> ssram_a,
+		ssram_d			=> ssram_d,
+		ssram_dp		=> ssram_dp,
+		ssram_bw_n		=> ssram_bw_n
+	);
+	
+inst_ssram : entity work.cy7c1354
+    -- PORT MAP Declarations
+    PORT MAP 
+    (
+		Dq		=> STD_LOGIC_VECTOR(ssram_d),   	-- Data I/O
+		Dpq		=> STD_LOGIC_VECTOR(ssram_dp),   	-- Data I/O
+		Addr	=> STD_LOGIC_VECTOR(ssram_a(19 downto 2)),   	-- Address
+		Mode	=> ssram_mode, 	-- Burst Mode
+		Clk		=> ssram_clk,      -- Clk
+		CEN_n	=> ssram_cke_n,                                   -- CEN#
+		AdvLd_n	=> ssram_adv,                                   -- Adv/Ld#
+		Bwa_n	=> ssram_bw_n(0),                                   -- Bwa#
+		Bwb_n	=> ssram_bw_n(1),                                   -- BWb#
+		Bwc_n	=> ssram_bw_n(2),                                   -- Bwc#
+		Bwd_n	=> ssram_bw_n(3),                                   -- BWd#
+		Rw_n	=> ssram_we_n,                                   -- RW#
+		Oe_n	=> ssram_oe_n,                                   -- OE#
+		Ce1_n	=> ssram_ce_n,                                   -- CE1#
+		Ce2		=> '1',                                   -- CE2
+		Ce3_n	=> '0',                                   -- CE3#
+		Zz		=> ssram_zz
+    );
+
+read_register:
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if dout_rst = '1' then
+				dout_cnt <= 0;
+			elsif ACK_I = '1' and WE_O = '0' then
+				dout_reg	<= DAT_I;
+				dout_cnt 	<= dout_cnt + 1;
+			end if;
+		end if;
+	end process;
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 5*CLK_PERIOD;
+		RST_O <= '0';
+		
+		wait until rising_edge(CLK_O);
+		-- 8 single cycles
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		DAT_O	<= X"1234_0000";
+		ADDR_O	<= X"0000_0000";
+		
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+	
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O);
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+		
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "0011";
+		ADDR_O	<= X"0000_0010";
+		DAT_O	<= X"DEADBEEF";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O);
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0010";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+		
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		CYC_O	<= '0';
+
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "1111";
+		DAT_O	<= X"1111_0000";
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		CYC_O	<= '0';
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "1111";
+		DAT_O	<= X"2222_0000";
+		ADDR_O	<= X"0000_0400";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0400";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		CYC_O	<= '0';
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "1111";
+		DAT_O	<= X"3333_0000";
+		ADDR_O	<= X"0000_0800";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0800";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		CYC_O	<= '0';
+
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "1111";
+		DAT_O	<= X"4444_0000";
+		ADDR_O	<= X"0000_0C00";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0C00";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		CYC_O	<= '0';
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		-- 8-word burst cycle
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		ADDR_O	<= X"0000_0400";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+
+		ADDR_O	<= X"0000_0800";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+
+		ADDR_O	<= X"0000_0C00";
+
+		for i in 0 to 7 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
+		CYC_O	<= '0';
+		
+		wait; 
+	
+	end process;
+	
+END;

lib/VGA_ctrl/sim/tb_vga_frontend.fdo

@@ -0,0 +1,25 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../FIFO/src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
+vcom -explicit  -93 "../src/fonts/char_rom_c64.vhd"
+vcom -explicit  -93 "../src/vga_types.vhd"
+vcom -explicit  -93 "../src/clkgen_virtex4.vhd"
+vcom -explicit  -93 "../src/char_gen.vhd"
+vcom -explicit  -93 "../src/vga_sync.vhd"
+vcom -explicit  -93 "../src/vga_timing.vhd"
+vcom -explicit  -93 "../src/vga_backend.vhd"
+vcom -explicit  -93 "../src/vga_frontend.vhd"
+vcom -explicit  -93 "../src/tb_vga_frontend.vhd"
+vsim -t 1ps   -lib work tb_vga_frontend
+view wave
+do {tb_vga_frontend.wdo}
+view structure
+view signals
+
+run 20ms

lib/VGA_ctrl/sim/tb_vga_frontend.wdo

@@ -0,0 +1,65 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_vga_frontend/clk_o
+add wave -noupdate -format Logic /tb_vga_frontend/rst_o
+add wave -noupdate -divider Master
+add wave -noupdate -format Logic /tb_vga_frontend/cyc_o
+add wave -noupdate -format Logic /tb_vga_frontend/stb_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_o
+add wave -noupdate -format Literal /tb_vga_frontend/sel_o
+add wave -noupdate -format Logic /tb_vga_frontend/we_o
+add wave -noupdate -format Logic /tb_vga_frontend/ack_i
+add wave -noupdate -format Logic /tb_vga_frontend/mrdy_o
+add wave -noupdate -format Logic /tb_vga_frontend/srdy_i
+add wave -noupdate -divider Slave
+add wave -noupdate -format Logic /tb_vga_frontend/cyc_i
+add wave -noupdate -format Logic /tb_vga_frontend/stb_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_i
+add wave -noupdate -format Literal /tb_vga_frontend/sel_i
+add wave -noupdate -format Logic /tb_vga_frontend/we_i
+add wave -noupdate -format Logic /tb_vga_frontend/ack_o
+add wave -noupdate -format Logic /tb_vga_frontend/mrdy_i
+add wave -noupdate -format Logic /tb_vga_frontend/srdy_o
+add wave -noupdate -divider VGA
+add wave -noupdate -format Logic /tb_vga_frontend/vga_clk_out
+add wave -noupdate -format Logic /tb_vga_frontend/vga_blank_n
+add wave -noupdate -format Logic /tb_vga_frontend/vga_sync_n
+add wave -noupdate -format Logic /tb_vga_frontend/vga_hsync
+add wave -noupdate -format Logic /tb_vga_frontend/vga_vsync
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_red
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_green
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_blue
+add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/s
+add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/request_cnt
+add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/read_cnt
+add wave -noupdate -divider Backend
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/ctrl_scan_en
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/sys_rst
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_vga_rdy
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_scan
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/scan_enable
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/is_scan
+add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_hpos
+add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_vpos
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/rst
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/dcm_locked
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_draw
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_en
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/hready
+add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/vready
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1420398899 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {1382189057 ps} {1476673938 ps}

lib/VGA_ctrl/sim/tb_vga_frontend64.fdo

@@ -0,0 +1,25 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../FIFO/src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
+vcom -explicit  -93 "../src/fonts/char_rom_c64.vhd"
+vcom -explicit  -93 "../src/vga_types.vhd"
+vcom -explicit  -93 "../src/clkgen_virtex4.vhd"
+vcom -explicit  -93 "../src/char_gen.vhd"
+vcom -explicit  -93 "../src/vga_sync.vhd"
+vcom -explicit  -93 "../src/vga_timing.vhd"
+vcom -explicit  -93 "../src/vga_backend.vhd"
+vcom -explicit  -93 "../src/vga_frontend64.vhd"
+vcom -explicit  -93 "../src/tb_vga_frontend64.vhd"
+vsim -t 1ps   -lib work tb_vga_frontend64
+view wave
+do {tb_vga_frontend64.wdo}
+view structure
+view signals
+
+run 20ms

lib/VGA_ctrl/sim/tb_vga_frontend64.wdo

@@ -0,0 +1,65 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
+add wave -noupdate -format Logic /tb_vga_frontend64/rst_o
+add wave -noupdate -divider Master
+add wave -noupdate -format Logic /tb_vga_frontend64/cyc_o
+add wave -noupdate -format Logic /tb_vga_frontend64/stb_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/addr_o
+add wave -noupdate -format Literal /tb_vga_frontend64/sel_o
+add wave -noupdate -format Logic /tb_vga_frontend64/we_o
+add wave -noupdate -format Logic /tb_vga_frontend64/ack_i
+add wave -noupdate -format Logic /tb_vga_frontend64/mrdy_o
+add wave -noupdate -format Logic /tb_vga_frontend64/srdy_i
+add wave -noupdate -divider Slave
+add wave -noupdate -format Logic /tb_vga_frontend64/cyc_i
+add wave -noupdate -format Logic /tb_vga_frontend64/stb_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/addr_i
+add wave -noupdate -format Literal /tb_vga_frontend64/sel_i
+add wave -noupdate -format Logic /tb_vga_frontend64/we_i
+add wave -noupdate -format Logic /tb_vga_frontend64/ack_o
+add wave -noupdate -format Logic /tb_vga_frontend64/mrdy_i
+add wave -noupdate -format Logic /tb_vga_frontend64/srdy_o
+add wave -noupdate -divider VGA
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_clk_out
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_blank_n
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_sync_n
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_hsync
+add wave -noupdate -format Logic /tb_vga_frontend64/vga_vsync
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_red
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_green
+add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_blue
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/request_cnt
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/read_cnt
+add wave -noupdate -divider Backend
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/ctrl_scan_en
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/sys_rst
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_vga_rdy
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_scan
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/scan_enable
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/is_scan
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_hpos
+add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_vpos
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/rst
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/dcm_locked
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_draw
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_en
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/hready
+add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/vready
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1420398899 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {1382189057 ps} {1476673938 ps}

lib/VGA_ctrl/src/char_gen.vhd

@@ -206,7 +206,7 @@ begin
 	    DATA        => char_rom_data
     );
 
-	inst_ascii_ram: entity work.dpram
+	inst_ascii_ram: entity work.dpram_1w1r
 	GENERIC MAP (
 		addr_width	=> A_RAM_ADDR_WIDTH,
 		data_width	=> A_RAM_DATA_WIDTH

lib/VGA_ctrl/src/dpram.vhd

@@ -1,79 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram is
-	Generic
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram;
-
-architecture Behavioral of dpram is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-process (clka)
-	begin
-	if clka'event and clka = '1' then
-		if en_a = '1' then
-			if we_a = '1' then
-				RAM(to_integer(addr_a)) <= din_a;
-			end if;
-		end if;
-	end if;
-end process;
-
-process (clkb)
-	begin
-	if clkb'event and clkb = '1' then
-		if en_b = '1' then
-			dout_b <= RAM(to_integer(addr_b));
-		end if;
-	end if;
-end process;
-
-
-end Behavioral;
-

lib/VGA_ctrl/src/tb_vga_frontend.vhd

@@ -0,0 +1,201 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+use work.vga_types.all;
+
+ENTITY tb_vga_frontend IS
+END tb_vga_frontend;
+
+ARCHITECTURE behavior OF tb_vga_frontend IS 
+
+	constant CLK_PERIOD		: time := 10 ns;
+	signal CLK_O			: std_logic := '1';
+	signal RST_O			: std_logic := '1';
+
+	-- Master
+	signal CYC_O			: std_logic;
+	signal STB_O			: std_logic;
+	signal WE_O				: std_logic;
+	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I			: std_logic := '0';
+	signal MRDY_O			: std_logic := '1';
+	signal SRDY_I			: std_logic := '0';
+	signal ADDR_O			: unsigned(31 downto 0);
+	signal MDAT_I			: unsigned(31 downto 0);
+	signal MDAT_O			: unsigned(31 downto 0);
+
+	-- Slave
+	signal CYC_I			: std_logic := '0';
+	signal STB_I			: std_logic := '0';
+	signal WE_I				: std_logic := '0';
+	signal SEL_I			: unsigned(3 downto 0);
+	signal ACK_O			: std_logic;
+	signal MRDY_I			: std_logic;
+	signal SRDY_O			: std_logic;
+	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
+	signal SDAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal SDAT_O			: unsigned(31 downto 0);
+
+	-- VGA signals
+	signal vga_clk_out		: std_logic;
+	signal vga_red			: unsigned(7 downto 0);
+	signal vga_green		: unsigned(7 downto 0);
+	signal vga_blue			: unsigned(7 downto 0);
+	signal vga_blank_n		: std_logic;
+	signal vga_sync_n		: std_logic;
+	signal vga_hsync		: std_logic;
+	signal vga_vsync		: std_logic;
+
+BEGIN
+
+inst_vga_frontend : entity work.vga_frontend
+	GENERIC MAP
+	(
+		sys_freq					=> 100E6,
+		fifo_depth					=> 2048,
+		fifo_almost_full_thresh		=> 2000,
+		fifo_almost_empty_thresh	=> 48,
+		tsvga						=> ts_vga_800_600_72
+	)
+	PORT MAP
+	(
+		-- System signals
+		RST_I			=> RST_O,
+		CLK_I			=> CLK_O,
+
+		-- JBUS Master signals
+		CYC_O			=> CYC_I,
+		STB_O			=> STB_I,
+		WE_O			=> WE_I,
+		SEL_O			=> SEL_I,
+		ACK_I			=> ACK_O,
+		SRDY_I			=> SRDY_O,
+		MRDY_O			=> MRDY_I,
+		ADDR_O			=> ADDR_I,
+		MDAT_I			=> MDAT_O,
+		MDAT_O			=> MDAT_I,
+
+		-- JBUS Slave signals
+		CYC_I			=> CYC_O,
+		STB_I			=> STB_O,
+		WE_I			=> WE_O,
+		SEL_I			=> SEL_O,
+		ACK_O			=> ACK_I,
+		SRDY_O			=> SRDY_I,
+		MRDY_I			=> MRDY_O,
+		ADDR_I			=> ADDR_O,
+		SDAT_I			=> SDAT_O,
+		SDAT_O			=> SDAT_I,
+		
+		-- VGA signals
+		vga_clk_out		=> vga_clk_out,
+		vga_red			=> vga_red,
+		vga_green		=> vga_green,
+		vga_blue		=> vga_blue,
+		vga_blank_n		=> vga_blank_n,
+		vga_sync_n		=> vga_sync_n,
+		vga_hsync		=> vga_hsync,
+		vga_vsync		=> vga_vsync
+	);
+
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+-- Slave
+	SRDY_O	<= CYC_I;
+	
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if RST_O = '1' then
+				MDAT_O	<= X"00000000";
+			elsif (CYC_I and STB_I) = '1' then
+				MDAT_O	<= MDAT_O + 1;
+				ACK_O	<= '1';
+			else
+				ACK_O	<= '0';
+			end if;
+		end if;
+	end process;
+
+-- Master
+STIMULUS: process
+
+	begin
+
+		wait for 6*CLK_PERIOD;
+		RST_O <= '0';
+
+		-- 8 single cycles
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_I	<= X"0000_0000";
+		ADDR_O	<= X"0000_0008";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_I	<= X"0000_0000";
+		ADDR_O	<= X"0000_0010";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_I	<= X"0000_0035";
+		ADDR_O	<= X"0000_0004";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_I	<= X"0000_0035";
+		ADDR_O	<= X"0000_0020";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		wait until rising_edge(CLK_O);
+		CYC_O	<= '0';
+
+		
+
+		wait; 
+	
+	end process;
+	
+END;

lib/VGA_ctrl/src/tb_vga_frontend64.vhd

@@ -0,0 +1,201 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+use work.vga_types.all;
+
+ENTITY tb_vga_frontend64 IS
+END tb_vga_frontend64;
+
+ARCHITECTURE behavior OF tb_vga_frontend64 IS 
+
+	constant CLK_PERIOD		: time := 10 ns;
+	signal CLK_O			: std_logic := '1';
+	signal RST_O			: std_logic := '1';
+
+	-- Master
+	signal CYC_O			: std_logic;
+	signal STB_O			: std_logic;
+	signal WE_O				: std_logic;
+	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I			: std_logic := '0';
+	signal MRDY_O			: std_logic := '1';
+	signal SRDY_I			: std_logic := '0';
+	signal ADDR_O			: unsigned(31 downto 0);
+	signal MDAT_I			: unsigned(63 downto 0);
+	signal MDAT_O			: unsigned(63 downto 0);
+
+	-- Slave
+	signal CYC_I			: std_logic := '0';
+	signal STB_I			: std_logic := '0';
+	signal WE_I				: std_logic := '0';
+	signal SEL_I			: unsigned(7 downto 0);
+	signal ACK_O			: std_logic;
+	signal MRDY_I			: std_logic;
+	signal SRDY_O			: std_logic;
+	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
+	signal SDAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal SDAT_O			: unsigned(31 downto 0);
+
+	-- VGA signals
+	signal vga_clk_out		: std_logic;
+	signal vga_red			: unsigned(7 downto 0);
+	signal vga_green		: unsigned(7 downto 0);
+	signal vga_blue			: unsigned(7 downto 0);
+	signal vga_blank_n		: std_logic;
+	signal vga_sync_n		: std_logic;
+	signal vga_hsync		: std_logic;
+	signal vga_vsync		: std_logic;
+
+BEGIN
+
+inst_vga_frontend64 : entity work.vga_frontend64
+	GENERIC MAP
+	(
+		sys_freq					=> 100E6,
+		fifo_depth					=> 2048,
+		fifo_almost_full_thresh		=> 2000,
+		fifo_almost_empty_thresh	=> 48,
+		tsvga						=> ts_vga_800_600_72
+	)
+	PORT MAP
+	(
+		-- System signals
+		RST_I			=> RST_O,
+		CLK_I			=> CLK_O,
+
+		-- JBUS Master signals
+		CYC_O			=> CYC_I,
+		STB_O			=> STB_I,
+		WE_O			=> WE_I,
+		SEL_O			=> SEL_I,
+		ACK_I			=> ACK_O,
+		SRDY_I			=> SRDY_O,
+		MRDY_O			=> MRDY_I,
+		ADDR_O			=> ADDR_I,
+		MDAT_I			=> MDAT_O,
+		MDAT_O			=> MDAT_I,
+
+		-- JBUS Slave signals
+		CYC_I			=> CYC_O,
+		STB_I			=> STB_O,
+		WE_I			=> WE_O,
+		SEL_I			=> SEL_O,
+		ACK_O			=> ACK_I,
+		SRDY_O			=> SRDY_I,
+		MRDY_I			=> MRDY_O,
+		ADDR_I			=> ADDR_O,
+		SDAT_I			=> SDAT_O,
+		SDAT_O			=> SDAT_I,
+		
+		-- VGA signals
+		vga_clk_out		=> vga_clk_out,
+		vga_red			=> vga_red,
+		vga_green		=> vga_green,
+		vga_blue		=> vga_blue,
+		vga_blank_n		=> vga_blank_n,
+		vga_sync_n		=> vga_sync_n,
+		vga_hsync		=> vga_hsync,
+		vga_vsync		=> vga_vsync
+	);
+
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+-- Slave
+	SRDY_O	<= CYC_I;
+	
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if RST_O = '1' then
+				MDAT_O	<= X"00000000_00000000";
+			elsif (CYC_I and STB_I) = '1' then
+				MDAT_O	<= MDAT_O + 1;
+				ACK_O	<= '1';
+			else
+				ACK_O	<= '0';
+			end if;
+		end if;
+	end process;
+
+-- Master
+STIMULUS: process
+
+	begin
+
+		wait for 6*CLK_PERIOD;
+		RST_O <= '0';
+
+		-- 8 single cycles
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_I	<= X"0000_0000";
+		ADDR_O	<= X"0000_0008";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_I	<= X"0000_0000";
+		ADDR_O	<= X"0000_0010";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_I	<= X"0000_0035";
+		ADDR_O	<= X"0000_0004";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_I	<= X"0000_0035";
+		ADDR_O	<= X"0000_0020";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		wait until rising_edge(CLK_O);
+		CYC_O	<= '0';
+
+		
+
+		wait; 
+	
+	end process;
+	
+END;

lib/VGA_ctrl/src/vga_backend.vhd

@@ -27,9 +27,6 @@ entity vga_backend is
 	Generic
 	(
 		sys_freq					: integer    		:= 100E6;
-		fifo_depth					: integer    		:= 2048;
-		fifo_almost_full_thresh		: natural 			:= 2000;
-		fifo_almost_empty_thresh	: natural 			:= 48;
 		tsvga						: vga_timespec_t	:= ts_vga_800_600_72
 	);
 	Port
@@ -37,19 +34,18 @@ entity vga_backend is
 		-- System signals
 		sys_rst				: in std_logic;
 		sys_clk				: in std_logic;
-		vga_ready			: out std_logic;
 		
-		-- Buffered channel (Graphics plane)
-		color_in			: in color_t;
-		color_fifo_we		: in std_logic;
-		color_fifo_full		: out std_logic;
-		color_fifo_afull	: out std_logic;
+		-- Color channels
+		color_in			: in color_array_t;
+		color_op			: in color_op_t;
+		color_en			: unsigned (VGA_NUM_CH-1 downto 0);
+
+		-- Control signals
+		ctrl_scan_en		: in std_logic;
 
-		-- Direct channel (Character plane)
-		direct_color_in		: in color_t;
-		direct_draw_en		: in std_logic;
-		
 		-- Status signals
+		stat_vga_rdy		: out std_logic;
+		stat_scan			: out std_logic;
 		stat_hsync			: out std_logic;
 		stat_vsync			: out std_logic;
 		stat_hready			: out std_logic;
@@ -61,7 +57,9 @@ entity vga_backend is
 		
 		-- VGA domain signals
 		vga_clk_out			: out std_logic;
-		vga_color_out		: out color_t;
+		vga_red				: out unsigned(7 downto 0);
+		vga_green			: out unsigned(7 downto 0);
+		vga_blue			: out unsigned(7 downto 0);
 		vga_blank_n			: out std_logic;
 		vga_sync_n			: out std_logic;
 		vga_hsync			: out std_logic;
@@ -72,10 +70,6 @@ end vga_backend;
 architecture Behavioral of vga_backend is
 
 	signal scan_enable			: std_logic;
-	signal fifo_full			: std_logic;
-	signal fifo_empty			: std_logic;
-	signal fifo_almost_empty	: std_logic;
-	signal fifo_almost_full		: std_logic;
 	signal is_scan				: std_logic;
 	signal is_hscan				: std_logic;
 	signal is_vscan				: std_logic;
@@ -83,7 +77,6 @@ architecture Behavioral of vga_backend is
 	signal vsync				: std_logic;
 	signal hready				: std_logic;
 	signal vready				: std_logic;
-	signal color				: color_t;
 	signal vga_clk				: std_logic;
 	signal dcm_locked			: std_logic;
 	signal rst					: std_logic;
@@ -91,9 +84,8 @@ architecture Behavioral of vga_backend is
 begin
 
 	vga_clk_out			<= vga_clk;
-	vga_ready			<= dcm_locked;
 	
-	inst_clkgen: entity work.clkgen
+inst_clkgen: entity work.clkgen
 	GENERIC MAP
 	(
 		sys_freq	=> sys_freq,
@@ -107,7 +99,7 @@ begin
 		dcm_locked	=> dcm_locked
 	);
 
-	inst_vga_timing: entity work.vga_timing 
+inst_vga_timing: entity work.vga_timing 
 	GENERIC MAP
 	(
 		tsvga => tsvga
@@ -127,44 +119,21 @@ begin
 		scan_rdy_v	=> vready
 	);
 
-	inst_linefifo: entity work.linefifo
-	GENERIC MAP 
-	(
-		depth				=> fifo_depth,
-		almost_full_thresh	=> fifo_almost_full_thresh,
-		almost_empty_thresh	=> fifo_almost_empty_thresh
-	)
-	PORT MAP(
-		rst			=> sys_rst,
-		clk_w		=> sys_clk,
-		clk_r		=> vga_clk,
-		we_w		=> color_fifo_we,
-		re_r		=> is_scan,
-		color_w		=> color_in,
-		color_r		=> color,
-		fifo_full	=> fifo_full,
-		fifo_empty	=> fifo_empty,
-		fifo_afull	=> fifo_almost_full,
-		fifo_aempty	=> fifo_almost_empty
-		
-	);
-
 	---------------------------------------------------------------------------------------------
 	rst					<= not dcm_locked;
+	stat_vga_rdy		<= dcm_locked;
 	stat_hsync			<= hsync;
 	stat_vsync			<= vsync;
 	stat_hscan			<= is_hscan;
 	stat_vscan			<= is_vscan;
 	stat_hready			<= hready;
 	stat_vready			<= vready;
+	stat_scan			<= is_scan;
 	
 	vga_blank_n			<= '1';
 	vga_sync_n			<= '0';
 	is_scan				<= is_hscan and is_vscan and scan_enable;
 	
-	color_fifo_full 	<= fifo_full;
-	color_fifo_afull 	<= fifo_almost_full;
-
 	---------------------------------------------------------------------------------------------
 	proc_vga_start:
 	process (rst, vga_clk)
@@ -173,7 +142,7 @@ begin
 			scan_enable <= '0';
 		elsif rising_edge(vga_clk) then
 			if vsync = '1' then
-				if fifo_empty = '0' then
+				if ctrl_scan_en = '1' then
 					scan_enable <= '1';
 				else
 					scan_enable <= '0';
@@ -185,17 +154,23 @@ begin
 	proc_vga_color_out:
 	process (rst, vga_clk)
 	variable do_scan : std_logic;
+	variable color : color_t;
 	begin
 		if rst = '1' then
 			do_scan := '0';
 		elsif rising_edge(vga_clk) then
-			vga_color_out <= (X"00", X"00", X"00");
+			vga_red		<= X"00";
+			vga_green	<= X"00";
+			vga_blue	<= X"00";
 			if do_scan = '1' then
-				if direct_draw_en = '1' then
-					vga_color_out <= direct_color_in;
-				else
-					vga_color_out <= color;
-				end if;	
+				for i in 0 to VGA_NUM_CH-1 loop
+					color := 	color_in(i);		
+					if color_en(i) = '1' then
+						vga_red		<= color(r);	-- ToDo: color_op over channels
+						vga_green	<= color(g);	-- ToDo: color_op over channels
+						vga_blue	<= color(b);	-- ToDo: color_op over channels
+					end if;
+				end loop;
 			end if;
 			do_scan := is_scan;
 		end if;

lib/VGA_ctrl/src/vga_frontend.vhd

@@ -0,0 +1,422 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    11:25:45 10/15/05
+-- Design Name:    
+-- Module Name:    vga_backend - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity vga_frontend is
+	Generic
+	(
+		sys_freq					: integer    		:= 100E6;
+		fifo_depth					: integer    		:= 2048;
+		fifo_almost_full_thresh		: natural 			:= 2000;
+		fifo_almost_empty_thresh	: natural 			:= 48;
+		tsvga						: vga_timespec_t	:= ts_vga_800_600_72
+	);
+	Port
+	(
+		-- System signals
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+
+		-- JBUS Master signals
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		ADDR_O			: out unsigned(31 downto 0);
+		MDAT_I			: in  unsigned(31 downto 0);
+		MDAT_O			: out unsigned(31 downto 0);
+		
+		-- JBUS Slave signals
+		CYC_I			: in  STD_LOGIC;
+		STB_I			: in  STD_LOGIC;
+		WE_I			: in  STD_LOGIC;
+		SEL_I			: in  unsigned(3 downto 0);
+		ACK_O			: out STD_LOGIC;
+		SRDY_O			: out STD_LOGIC;
+		MRDY_I			: in  STD_LOGIC;
+		ADDR_I			: in  unsigned(31 downto 0);
+		SDAT_I			: in  unsigned(31 downto 0);
+		SDAT_O			: out unsigned(31 downto 0);
+		
+		-- VGA signals
+		vga_clk_out		: out std_logic;
+		vga_red			: out unsigned(7 downto 0);
+		vga_green		: out unsigned(7 downto 0);
+		vga_blue		: out unsigned(7 downto 0);
+		vga_blank_n		: out std_logic;
+		vga_sync_n		: out std_logic;
+		vga_hsync		: out std_logic;
+		vga_vsync		: out std_logic
+	);
+end vga_frontend;
+
+architecture Behavioral of vga_frontend is
+
+	signal vga_clk				: std_logic;
+
+	-- Color FIFO signals
+	signal fifo_full			: std_logic;
+	signal fifo_empty			: std_logic;
+	signal fifo_almost_empty	: std_logic;
+	signal fifo_almost_full		: std_logic;
+	signal fifo_color_re		: std_logic;
+	signal fifo_color_we		: std_logic;
+	signal fifo_color_out		: unsigned(31 downto 0);
+	signal fifo_color_in		: unsigned(31 downto 0);
+
+	--	Backend signals
+	signal scan_rdy				: std_logic;
+	signal ctrl_scan_en			: std_logic;
+	signal color_in				: color_array_t;
+	signal color_op				: color_op_t;
+	signal color_en				: unsigned (VGA_NUM_CH-1 downto 0);
+
+	signal stat_vga_rdy			: std_logic;
+	signal stat_hready			: std_logic;
+	signal stat_vready			: std_logic;
+	signal stat_scan			: std_logic;
+	signal stat_hscan			: std_logic;
+	signal stat_vscan			: std_logic;
+	signal stat_hsync			: std_logic;
+	signal stat_vsync			: std_logic;
+	signal stat_hpos			: natural range 0 to tsvga.ts_h.ncyc_scan-1;
+	signal stat_vpos			: natural range 0 to tsvga.ts_v.ncyc_scan-1;
+
+	--	CG signals
+	signal cg_en				: std_logic;
+	signal cg_rdy				: std_logic;
+	signal cg_draw				: std_logic;
+	signal cg_clr_screen		: std_logic;
+	signal cg_clr_line			: std_logic;
+	signal cg_ascii_data		: unsigned(7 downto 0);
+	signal cg_ascii_data_we		: std_logic;
+	signal cg_ascii_posy_we		: std_logic;
+	signal cg_ascii_posx_we		: std_logic;
+
+	-- Bus master signals
+	constant MAX_REQUEST_CNT	: natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
+
+	signal vga_mem_offset		: unsigned(31 downto 0);
+	signal vga_scan_rdy			: std_logic;
+	signal vga_master_en		: std_logic;
+	signal request_cnt_rst		: std_logic;
+	signal request_cnt_en		: std_logic;
+	signal pixel_cnt_rst		: std_logic;
+	signal read_bus_en			: std_logic;
+	signal request_cnt			: natural range 0 to MAX_REQUEST_CNT-1;
+	signal read_cnt				: natural range 0 to MAX_REQUEST_CNT-1;
+
+	type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
+	signal s, sn : vm_state_t;
+
+begin
+
+	vga_clk_out		<= vga_clk;
+	
+inst_vga_backend : entity work.vga_backend
+	GENERIC MAP
+	(
+		sys_freq					=> sys_freq,
+		tsvga						=> tsvga
+	)
+	PORT MAP
+	(
+		-- System signals
+		sys_rst			=> RST_I,
+		sys_clk			=> CLK_I,
+		
+		-- Color channels
+		color_in		=> color_in,
+		color_op		=> color_op,
+		color_en		=> color_en,
+
+		-- Control signals
+		ctrl_scan_en	=> ctrl_scan_en,
+
+		-- Status signals
+		stat_vga_rdy	=> stat_vga_rdy,
+		stat_scan		=> stat_scan,
+		stat_hsync		=> stat_hsync,
+		stat_vsync		=> stat_vsync,
+		stat_hready		=> stat_hready,
+		stat_vready		=> stat_vready,
+		stat_hscan		=> stat_hscan,
+		stat_vscan		=> stat_vscan,
+		stat_hpos		=> stat_hpos,
+		stat_vpos		=> stat_vpos,
+		
+		-- VGA domain signals
+		vga_clk_out		=> vga_clk,
+		vga_red			=> vga_red,
+		vga_green		=> vga_green,
+		vga_blue		=> vga_blue,
+		vga_blank_n		=> vga_blank_n,
+		vga_sync_n		=> vga_sync_n,
+		vga_hsync		=> vga_hsync,
+		vga_vsync		=> vga_vsync
+	);
+
+	ctrl_scan_en	<= '1';
+	color_en(0)		<= not fifo_empty;
+	color_en(1)		<= cg_draw;
+	color_in(0)		<= to_color_t(fifo_color_out);
+	color_in(1)		<= (X"FF", X"FF", X"FF", X"FF");	-- white opaque
+	color_op		<= op_over;
+	vga_scan_rdy	<= stat_hready and stat_vready;
+	
+inst_linefifo: entity work.fifo_async
+	GENERIC MAP 
+	(
+		addr_width			=> NextExpBaseTwo(fifo_depth),
+		data_width			=> 32,
+		almost_full_thresh	=> fifo_almost_full_thresh,
+		almost_empty_thresh	=> fifo_almost_empty_thresh
+	)
+	PORT MAP
+	(
+		rst				=> RST_I,
+		clk_w			=> CLK_I,
+		clk_r			=> vga_clk,
+		we_w			=> fifo_color_we,
+		re_r			=> fifo_color_re,
+		data_w			=> fifo_color_in,
+		data_r			=> fifo_color_out,
+		fifo_full		=> fifo_full,
+		fifo_empty		=> fifo_empty,
+		fifo_afull		=> fifo_almost_full,
+		fifo_aempty		=> fifo_almost_empty
+		
+	);
+
+	fifo_color_in		<= MDAT_I;
+	fifo_color_re		<= stat_scan;
+	fifo_color_we		<= ACK_I and read_bus_en;		-- TODO:
+	MRDY_O				<= not fifo_full;
+	SEL_O				<= (others => '0');
+	WE_O				<= '0';
+	
+vga_master_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				s	<= init;
+			else
+				s	<= sn;
+			end if;
+		end if;
+	end process;	
+
+vga_master:
+	process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
+	begin
+	
+	CYC_O			<= '0';
+	STB_O			<= '0';
+	pixel_cnt_rst	<= '0';
+	request_cnt_rst	<= '0';
+	request_cnt_en	<= '0';
+	read_bus_en		<= '0';
+	sn				<= s;
+	
+	case s is
+		when init =>
+		if stat_vga_rdy = '1' then
+			sn	<= idle;
+		end if;
+		
+		when idle =>
+		pixel_cnt_rst	<= '1';
+		if vga_master_en = '1' and vga_scan_rdy = '1' then
+			sn	<= rdy;
+		end if;
+		
+		when rdy =>
+--		pixel_cnt_rst	<= '1';
+		if fifo_almost_empty = '1' then
+			sn	<= bus_request;
+		end if;
+		
+		when bus_request =>
+			CYC_O			<= '1';
+			request_cnt_rst	<= '1';
+			if SRDY_I = '1' then
+				sn	<= bus_access;
+			end if;
+			
+		when bus_access =>
+			CYC_O			<= '1';
+			STB_O			<= '1';
+			request_cnt_en	<= '1';
+			read_bus_en		<= '1';
+			if fifo_almost_full = '1' then
+				sn <= bus_data;
+			end if;	
+		when bus_data =>
+			CYC_O		<= '1';
+			read_bus_en	<= '1';
+			if read_cnt = request_cnt then
+				sn	<= rdy;
+				if vga_master_en = '0' then
+					sn	<= idle;
+				end if;	
+			end if;	
+		when others =>
+			sn	<= idle;
+		
+		end case;
+	end process;
+	
+request_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if request_cnt_rst = '1' then
+				request_cnt	<= 0;
+			elsif request_cnt_en = '1' and SRDY_I = '1' then
+				if request_cnt /= MAX_REQUEST_CNT-1 then
+					request_cnt <= request_cnt + 1;
+				end if;
+			end if;	
+		end if;
+	end process;	
+		
+read_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if request_cnt_rst = '1' then
+				read_cnt	<= 0;
+			elsif read_bus_en = '1' and ACK_I = '1' then
+				if read_cnt /= MAX_REQUEST_CNT-1 then
+					read_cnt <= read_cnt + 1;
+				end if;
+			end if;	
+		end if;
+	end process;	
+
+pixel_counter:
+	process(CLK_I)
+	variable pixel_cntx	: natural range 0 to tsvga.ts_h.ncyc_scan-1;
+	variable pixel_cnty	: natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+	begin
+		if rising_edge(CLK_I) then
+			if pixel_cnt_rst = '1' then
+				pixel_cntx	:= 0;
+				pixel_cnty	:= tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+			elsif request_cnt_en = '1' and SRDY_I = '1' then
+				if pixel_cntx /= tsvga.ts_h.ncyc_scan-1 then
+					pixel_cntx 	:= pixel_cntx + 1;
+				else
+					pixel_cntx	:= 0;
+					if pixel_cnty /= 0 then
+						pixel_cnty 	:= pixel_cnty - tsvga.ts_h.ncyc_scan;
+					else
+						pixel_cnty	:= tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+					end if;
+				end if;
+			end if;	
+			ADDR_O	<= vga_mem_offset + (to_unsigned(pixel_cntx, 30) & "00") + (to_unsigned(pixel_cnty, 30) & "00");
+		end if;
+	end process;	
+	
+inst_char_gen : entity work.char_gen
+	GENERIC MAP
+	(
+		tsvga				=> tsvga,
+		CHARACTER_SCALE		=> 1,
+		CHAR_ROM_SIZE_X		=> 8,	-- Pixels
+		CHAR_ROM_SIZE_Y		=> 16,	-- Pixels
+		CHAR_ROM_DEPTH		=> 256,	-- Chars
+		MAX_CHAR_PER_LINE	=> 80,	-- Chars
+		MAX_LINE_PER_FRAME	=> 32,	-- Chars
+		CHAR_SPACING_X		=> 0, 	-- Pixels
+		CHAR_SPACING_Y		=> 0,	-- Pixels
+		SCREEN_OFFSET_X		=> 16,	-- Pixels
+		SCREEN_OFFSET_Y		=> 16	-- Pixels
+	)		
+	PORT MAP
+	(
+	    rst				=> RST_I,
+	    sys_clk			=> CLK_I,
+	    vga_clk			=> vga_clk,
+	    ce				=> cg_en,
+	    frame_pulse		=> scan_rdy,
+	    clr_screen		=> cg_clr_screen,
+	    clr_line		=> cg_clr_line,
+	    ascii_data		=> cg_ascii_data,
+	    ascii_data_we	=> cg_ascii_data_we,
+	    ascii_posy_we	=> cg_ascii_posy_we,
+	    ascii_posx_we	=> cg_ascii_posx_we,
+	    ready			=> cg_rdy,
+	    pos_x			=> stat_hpos,
+	    pos_y			=> stat_vpos,
+	    char_draw_en	=> cg_draw
+    );
+	SRDY_O				<= CYC_I; -- and cg_rdy;
+	cg_ascii_data		<= SDAT_I(7 downto 0);
+	cg_ascii_data_we	<= ADDR_I(2) and CYC_I and STB_I and WE_I;
+	cg_ascii_posy_we	<= ADDR_I(3) and CYC_I and STB_I and WE_I;
+	cg_ascii_posx_we	<= ADDR_I(4) and CYC_I and STB_I and WE_I;
+	cg_clr_screen		<= ADDR_I(5) and CYC_I and STB_I and WE_I;
+	cg_clr_line			<= ADDR_I(6) and CYC_I and STB_I and WE_I;
+	SDAT_O				<= X"0000000" & "000" & cg_rdy;
+	scan_rdy			<= stat_hready and stat_vready;
+	cg_en				<= stat_scan;
+	
+data_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O	<= '0';
+			else
+				ACK_O	<= CYC_I and STB_I and not WE_I;
+			end if;
+		end if;
+	end process;
+
+data_valid_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				vga_master_en	<= '0';
+				vga_mem_offset	<= X"40000000";
+			elsif (CYC_I and STB_I and WE_I) = '1' then
+				if ADDR_I(8) = '1' then
+					vga_master_en	<= SDAT_I(0);
+				elsif ADDR_I(9) = '1' then
+					vga_mem_offset	<= SDAT_I(31 downto 2) & "00";
+				end if;
+			end if;
+		end if;
+	end process;
+	
+	---------------------------------------------------------------------------------------------
+
+end Behavioral;

lib/VGA_ctrl/src/vga_frontend64.vhd

@@ -0,0 +1,426 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    11:25:45 10/15/05
+-- Design Name:    
+-- Module Name:    vga_backend - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity vga_frontend64 is
+	Generic
+	(
+		sys_freq					: integer    		:= 100E6;
+		fifo_depth					: integer    		:= 2048;
+		fifo_almost_full_thresh		: natural 			:= 2000;
+		fifo_almost_empty_thresh	: natural 			:= 48;
+		tsvga						: vga_timespec_t	:= ts_vga_800_600_72
+	);
+	Port
+	(
+		-- System signals
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+
+		-- JBUS Master signals
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(7 downto 0);
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		ADDR_O			: out unsigned(31 downto 0);
+		MDAT_I			: in  unsigned(63 downto 0);
+		MDAT_O			: out unsigned(63 downto 0);
+		
+		-- JBUS Slave signals
+		CYC_I			: in  STD_LOGIC;
+		STB_I			: in  STD_LOGIC;
+		WE_I			: in  STD_LOGIC;
+		SEL_I			: in  unsigned(3 downto 0);
+		ACK_O			: out STD_LOGIC;
+		SRDY_O			: out STD_LOGIC;
+		MRDY_I			: in  STD_LOGIC;
+		ADDR_I			: in  unsigned(31 downto 0);
+		SDAT_I			: in  unsigned(31 downto 0);
+		SDAT_O			: out unsigned(31 downto 0);
+		
+		-- VGA signals
+		vga_clk_out		: out std_logic;
+		vga_red			: out unsigned(7 downto 0);
+		vga_green		: out unsigned(7 downto 0);
+		vga_blue		: out unsigned(7 downto 0);
+		vga_blank_n		: out std_logic;
+		vga_sync_n		: out std_logic;
+		vga_hsync		: out std_logic;
+		vga_vsync		: out std_logic
+	);
+end vga_frontend64;
+
+architecture Behavioral of vga_frontend64 is
+
+	
+	signal vga_clk				: std_logic;
+
+	-- Color FIFO signals
+	signal fifo_full			: std_logic;
+	signal fifo_empty			: std_logic;
+	signal fifo_almost_empty	: std_logic;
+	signal fifo_almost_full		: std_logic;
+	signal fifo_color_re		: std_logic;
+	signal fifo_color_we		: std_logic;
+	signal fifo_color_out		: unsigned(63 downto 0);
+	signal fifo_color_in		: unsigned(63 downto 0);
+
+	--	Backend signals
+	signal scan_rdy				: std_logic;
+	signal ctrl_scan_en			: std_logic;
+	signal color_in				: color_array_t;
+	signal color_op				: color_op_t;
+	signal color_en				: unsigned (VGA_NUM_CH-1 downto 0);
+
+	signal stat_vga_rdy			: std_logic;
+	signal stat_hready			: std_logic;
+	signal stat_vready			: std_logic;
+	signal stat_scan			: std_logic;
+	signal stat_hscan			: std_logic;
+	signal stat_vscan			: std_logic;
+	signal stat_hsync			: std_logic;
+	signal stat_vsync			: std_logic;
+	signal stat_hpos			: natural range 0 to tsvga.ts_h.ncyc_scan-1;
+	signal stat_vpos			: natural range 0 to tsvga.ts_v.ncyc_scan-1;
+
+	--	CG signals
+	signal cg_en				: std_logic;
+	signal cg_rdy				: std_logic;
+	signal cg_draw				: std_logic;
+	signal cg_clr_screen		: std_logic;
+	signal cg_clr_line			: std_logic;
+	signal cg_ascii_data		: unsigned(7 downto 0);
+	signal cg_ascii_data_we		: std_logic;
+	signal cg_ascii_posy_we		: std_logic;
+	signal cg_ascii_posx_we		: std_logic;
+
+	-- Bus master signals
+	constant MAX_REQUEST_CNT	: natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
+
+	signal vga_mem_offset		: unsigned(31 downto 0);
+	signal vga_scan_rdy			: std_logic;
+	signal vga_master_en		: std_logic;
+	signal request_cnt_rst		: std_logic;
+	signal request_cnt_en		: std_logic;
+	signal pixel_cnt_rst		: std_logic;
+	signal read_bus_en			: std_logic;
+	signal request_cnt			: natural range 0 to MAX_REQUEST_CNT-1;
+	signal read_cnt				: natural range 0 to MAX_REQUEST_CNT-1;
+	
+	signal odd_pixel			: unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
+	
+	type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
+	signal s, sn : vm_state_t;
+
+begin
+
+	vga_clk_out		<= vga_clk;
+	
+inst_vga_backend : entity work.vga_backend
+	GENERIC MAP
+	(
+		sys_freq					=> sys_freq,
+		tsvga						=> tsvga
+	)
+	PORT MAP
+	(
+		-- System signals
+		sys_rst			=> RST_I,
+		sys_clk			=> CLK_I,
+		
+		-- Color channels
+		color_in		=> color_in,
+		color_op		=> color_op,
+		color_en		=> color_en,
+
+		-- Control signals
+		ctrl_scan_en	=> ctrl_scan_en,
+
+		-- Status signals
+		stat_vga_rdy	=> stat_vga_rdy,
+		stat_scan		=> stat_scan,
+		stat_hsync		=> stat_hsync,
+		stat_vsync		=> stat_vsync,
+		stat_hready		=> stat_hready,
+		stat_vready		=> stat_vready,
+		stat_hscan		=> stat_hscan,
+		stat_vscan		=> stat_vscan,
+		stat_hpos		=> stat_hpos,
+		stat_vpos		=> stat_vpos,
+		
+		-- VGA domain signals
+		vga_clk_out		=> vga_clk,
+		vga_red			=> vga_red,
+		vga_green		=> vga_green,
+		vga_blue		=> vga_blue,
+		vga_blank_n		=> vga_blank_n,
+		vga_sync_n		=> vga_sync_n,
+		vga_hsync		=> vga_hsync,
+		vga_vsync		=> vga_vsync
+	);
+	
+	odd_pixel		<= to_unsigned(stat_hpos, odd_pixel'length);
+	ctrl_scan_en	<= '1';
+	color_en(0)		<= not fifo_empty;
+	color_en(1)		<= cg_draw;
+	color_in(0)		<= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32));
+	color_in(1)		<= (X"FF", X"FF", X"FF", X"FF");	-- white opaque
+	color_op		<= op_over;
+	vga_scan_rdy	<= stat_hready and stat_vready;
+	
+inst_linefifo: entity work.fifo_async
+	GENERIC MAP 
+	(
+		addr_width			=> NextExpBaseTwo(fifo_depth),
+		data_width			=> 64,
+		almost_full_thresh	=> fifo_almost_full_thresh,
+		almost_empty_thresh	=> fifo_almost_empty_thresh
+	)
+	PORT MAP
+	(
+		rst				=> RST_I,
+		clk_w			=> CLK_I,
+		clk_r			=> vga_clk,
+		we_w			=> fifo_color_we,
+		re_r			=> fifo_color_re,
+		data_w			=> fifo_color_in,
+		data_r			=> fifo_color_out,
+		fifo_full		=> fifo_full,
+		fifo_empty		=> fifo_empty,
+		fifo_afull		=> fifo_almost_full,
+		fifo_aempty		=> fifo_almost_empty
+		
+	);
+
+	fifo_color_in		<= MDAT_I;
+	fifo_color_re		<= stat_scan and odd_pixel(0);
+	fifo_color_we		<= ACK_I and read_bus_en;		-- TODO:
+	MRDY_O				<= not fifo_full;
+	SEL_O				<= (others => '0');
+	WE_O				<= '0';
+	
+vga_master_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				s	<= init;
+			else
+				s	<= sn;
+			end if;
+		end if;
+	end process;	
+
+vga_master:
+	process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
+	begin
+	
+	CYC_O			<= '0';
+	STB_O			<= '0';
+	pixel_cnt_rst	<= '0';
+	request_cnt_rst	<= '0';
+	request_cnt_en	<= '0';
+	read_bus_en		<= '0';
+	sn				<= s;
+	
+	case s is
+		when init =>
+		if stat_vga_rdy = '1' then
+			sn	<= idle;
+		end if;
+		
+		when idle =>
+		pixel_cnt_rst	<= '1';
+		if vga_master_en = '1' and vga_scan_rdy = '1' then
+			sn	<= rdy;
+		end if;
+		
+		when rdy =>
+--		pixel_cnt_rst	<= '1';
+		if fifo_almost_empty = '1' then
+			sn	<= bus_request;
+		end if;
+		
+		when bus_request =>
+			CYC_O			<= '1';
+			request_cnt_rst	<= '1';
+			if SRDY_I = '1' then
+				sn	<= bus_access;
+			end if;
+			
+		when bus_access =>
+			CYC_O			<= '1';
+			STB_O			<= '1';
+			request_cnt_en	<= '1';
+			read_bus_en		<= '1';
+			if fifo_almost_full = '1' then
+				sn <= bus_data;
+			end if;	
+		when bus_data =>
+			CYC_O		<= '1';
+			read_bus_en	<= '1';
+			if read_cnt = request_cnt then
+				sn	<= rdy;
+				if vga_master_en = '0' then
+					sn	<= idle;
+				end if;	
+			end if;	
+		when others =>
+			sn	<= idle;
+		
+		end case;
+	end process;
+	
+request_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if request_cnt_rst = '1' then
+				request_cnt	<= 0;
+			elsif request_cnt_en = '1' and SRDY_I = '1' then
+				if request_cnt /= MAX_REQUEST_CNT-1 then
+					request_cnt <= request_cnt + 1;
+				end if;
+			end if;	
+		end if;
+	end process;	
+		
+read_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if request_cnt_rst = '1' then
+				read_cnt	<= 0;
+			elsif read_bus_en = '1' and ACK_I = '1' then
+				if read_cnt /= MAX_REQUEST_CNT-1 then
+					read_cnt <= read_cnt + 1;
+				end if;
+			end if;	
+		end if;
+	end process;	
+
+pixel_counter:
+	process(CLK_I)
+	variable pixel_cntx	: natural range 0 to tsvga.ts_h.ncyc_scan/2-1;
+	variable pixel_cnty	: natural range 0 to tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+	begin
+		if rising_edge(CLK_I) then
+			if pixel_cnt_rst = '1' then
+				pixel_cntx	:= 0;
+				pixel_cnty	:= tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+			elsif request_cnt_en = '1' and SRDY_I = '1' then
+				if pixel_cntx /= tsvga.ts_h.ncyc_scan/2-1 then
+					pixel_cntx 	:= pixel_cntx + 1;
+				else
+					pixel_cntx	:= 0;
+					if pixel_cnty /= 0 then
+						pixel_cnty 	:= pixel_cnty - tsvga.ts_h.ncyc_scan;
+					else
+						pixel_cnty	:= tsvga.ts_h.ncyc_scan*(tsvga.ts_v.ncyc_scan-1);
+					end if;
+				end if;
+			end if;	
+			ADDR_O	<= vga_mem_offset + (to_unsigned(pixel_cntx, 29) & "000") + (to_unsigned(pixel_cnty, 30) & "00");
+		end if;
+	end process;	
+	
+inst_char_gen : entity work.char_gen
+	GENERIC MAP
+	(
+		tsvga				=> tsvga,
+		CHARACTER_SCALE		=> 1,
+		CHAR_ROM_SIZE_X		=> 8,	-- Pixels
+		CHAR_ROM_SIZE_Y		=> 16,	-- Pixels
+		CHAR_ROM_DEPTH		=> 256,	-- Chars
+		MAX_CHAR_PER_LINE	=> 80,	-- Chars
+		MAX_LINE_PER_FRAME	=> 32,	-- Chars
+		CHAR_SPACING_X		=> 0, 	-- Pixels
+		CHAR_SPACING_Y		=> 0,	-- Pixels
+		SCREEN_OFFSET_X		=> 16,	-- Pixels
+		SCREEN_OFFSET_Y		=> 16	-- Pixels
+	)		
+	PORT MAP
+	(
+	    rst				=> RST_I,
+	    sys_clk			=> CLK_I,
+	    vga_clk			=> vga_clk,
+	    ce				=> cg_en,
+	    frame_pulse		=> scan_rdy,
+	    clr_screen		=> cg_clr_screen,
+	    clr_line		=> cg_clr_line,
+	    ascii_data		=> cg_ascii_data,
+	    ascii_data_we	=> cg_ascii_data_we,
+	    ascii_posy_we	=> cg_ascii_posy_we,
+	    ascii_posx_we	=> cg_ascii_posx_we,
+	    ready			=> cg_rdy,
+	    pos_x			=> stat_hpos,
+	    pos_y			=> stat_vpos,
+	    char_draw_en	=> cg_draw
+    );
+	SRDY_O				<= CYC_I; -- and cg_rdy;
+	cg_ascii_data		<= SDAT_I(7 downto 0);
+	cg_ascii_data_we	<= ADDR_I(2) and CYC_I and STB_I and WE_I;
+	cg_ascii_posy_we	<= ADDR_I(3) and CYC_I and STB_I and WE_I;
+	cg_ascii_posx_we	<= ADDR_I(4) and CYC_I and STB_I and WE_I;
+	cg_clr_screen		<= ADDR_I(5) and CYC_I and STB_I and WE_I;
+	cg_clr_line			<= ADDR_I(6) and CYC_I and STB_I and WE_I;
+	SDAT_O				<= X"0000000" & "000" & cg_rdy;
+	scan_rdy			<= stat_hready and stat_vready;
+	cg_en				<= stat_scan;
+	
+data_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O	<= '0';
+			else
+				ACK_O	<= CYC_I and STB_I and not WE_I;
+			end if;
+		end if;
+	end process;
+
+data_valid_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				vga_master_en	<= '0';
+				vga_mem_offset	<= X"40000000";
+			elsif (CYC_I and STB_I and WE_I) = '1' then
+				if ADDR_I(8) = '1' then
+					vga_master_en	<= SDAT_I(0);
+				elsif ADDR_I(9) = '1' then
+					vga_mem_offset	<= SDAT_I(31 downto 2) & "00";
+				end if;
+			end if;
+		end if;
+	end process;
+	
+	---------------------------------------------------------------------------------------------
+
+end Behavioral;

lib/VGA_ctrl/src/vga_types.vhd

@@ -12,10 +12,14 @@ use IEEE.MATH_REAL.ALL;
 package vga_types is
 	
 	-- Constants
-
+	constant	VGA_NUM_CH		: natural := 2;
+	
 	-- Types
-	type color_range_t is (r, g, b);
+	type color_range_t is (r, g, b, a);
 	type color_t is array (color_range_t) of unsigned(7 downto 0);
+	type color_array_t is array (0 to VGA_NUM_CH-1) of color_t;
+
+	type color_op_t is (op_over, op_xor, op_alpha);
 	
 	type scan_timespec_t is
 	record
@@ -42,8 +46,8 @@ package vga_types is
 	(
 		f_pxl_clk              => 100E6,
 		nfps                   => 6,
-		ts_h                   => (8,5,2,3,'0'),
-		ts_v                   => (6,4,2,3,'0')
+		ts_h                   => (80,5,2,3,'0'),
+		ts_v                   => (60,4,2,3,'0')
 	);
 
 	-- 640 x 480 @ 60 Hz (not recommended)
@@ -127,6 +131,9 @@ package vga_types is
 	function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural;
 	function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural;
 	
+	function to_color_t(x : unsigned) return color_t;
+	function to_unsigned(x : color_t) return unsigned;
+	
 end vga_types;
 
 
@@ -207,7 +214,28 @@ package body vga_types is
 
 	end DCM_PERIOD;	
 	
+	function to_color_t(x : unsigned) return color_t is
+	variable result : color_t;
+	begin
+		result(r)	:= x(x'right+7 downto x'right+0);
+		result(g)	:= x(x'right+15 downto x'right+8);
+		result(b)	:= x(x'right+23 downto x'right+16);
+		result(a)	:= x(x'right+31 downto x'right+24);
+		
+		return result;
+	end to_color_t;
 	
+	function to_unsigned(x : color_t) return unsigned is
+	variable result : unsigned(31 downto 0);
+	begin
+		result(7 downto 0)		:= x(r);
+		result(15 downto 8)		:= x(g);
+		result(23 downto 16)	:= x(b);
+		result(31 downto 24)	:= x(a);
+
+		return result;
+	end to_unsigned;
+
 end vga_types;
 
 

lib/misc/async_port_wb.vhd

@@ -0,0 +1,290 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.3 2008-10-12 14:12:14 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.sys_types.all;
+
+	------------------------------------------------------------------
+entity async_port_wb is
+	Generic
+	(
+		addr_width		: natural := 32;
+		data_width		: natural := 32;
+		async_timespec	: async_timespec_t
+	);
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		async_a		: out unsigned(addr_width-1 downto 0);
+		async_d		: inout unsigned(data_width-1 downto 0);
+		async_cs	: out std_logic;
+		async_wr	: out std_logic;
+		async_rd	: out std_logic;
+		async_rst	: out std_logic
+	);
+end async_port_wb;
+
+architecture Behavioral of async_port_wb is
+
+	type async_t is record
+		cs		: std_logic;
+		wr		: std_logic;
+		rd		: std_logic;
+		rst		: std_logic;
+		drive_d	: std_logic;
+	end record;
+	
+	type async_state_t is (start, reset, idle, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
+	
+	signal s, sn		: async_state_t;
+	signal as			: async_t;
+	signal ack			: std_logic;
+	signal cc_rst		: std_logic;
+	signal cycle_cnt	: natural range 0 to 15;
+	signal cycle_reload	: natural range 0 to 15;
+	signal rdy			: std_logic;
+	signal rdyo			: std_logic;
+	signal en			: std_logic;
+	signal data_reg		: unsigned(data_width-1 downto 0);
+
+	------------------------------------------------------------------
+	begin
+
+	SRDY_O	<= CYC_I and rdyo;
+	en		<= CYC_I and STB_I;
+	
+	proc_cycle_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if cc_rst = '1' then
+				cycle_cnt <= cycle_reload;
+			elsif cycle_cnt /= 0 then
+				cycle_cnt <= cycle_cnt - 1;
+			end if;
+		end if;
+	end process;
+	
+	------------------------------------------------------------------
+	proc_state_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				s <= start;
+			else
+				s <= sn;
+			end if;
+		end if;
+	end process;
+	
+	proc_state:
+	process(s, cycle_cnt, en, WE_I)
+	begin
+		
+		cycle_reload	<= async_timespec.ncyc_pulse_rst;
+		cc_rst			<= '0';
+		as.rst			<= '0';
+		as.cs			<= '0';
+		as.wr			<= '0';
+		as.rd			<= '0';
+		as.drive_d		<= '0';
+		ack				<= '0';
+		rdy				<= '0';
+		
+		sn	<= s;
+		case s is
+		
+		when start =>
+			cc_rst	<= '1';
+			sn		<= reset;
+		when reset =>
+			as.rst	<= '1';
+			if cycle_cnt = 0 then
+				sn	<= idle;
+			end if;
+		when idle =>
+			rdy			<= '1';
+			if en = '1' then
+				as.cs			<= '1';
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_access-1;
+				if WE_I = '0' then
+					sn				<= leadin_rd;
+				else
+					sn				<= leadin_wr;
+				end if;
+			end if;
+
+		when leadin_rd =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_pulse_rd-1;
+				as.rd			<= '1';
+				sn				<= read;
+			end if;
+
+		when leadin_wr =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_pulse_wr-1;
+				as.wr			<= '1';
+				as.drive_d		<= '1';
+				sn				<= write;
+			end if;
+	
+		when read =>
+			as.cs		<= '1';
+			as.rd		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_cs_hold-1;
+--				as.rd			<= '0';
+				sn				<= leadout_rd;
+				ack				<= '1';
+			end if;
+				
+		when write =>
+			as.drive_d	<= '1';
+			as.cs		<= '1';
+			as.wr		<= '1';
+			if cycle_cnt = 0 then
+				as.wr			<= '0';
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_cs_hold-1;
+				sn				<= leadout_wr;
+--				ack				<= '1';
+			end if;
+
+		when leadout_rd =>
+			as.cs		<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_release-1;
+				sn				<= release;
+				as.cs			<= '0';
+			end if;
+
+		when leadout_wr =>
+			as.cs		<= '1';
+			as.drive_d	<= '1';
+			if cycle_cnt = 0 then
+				cc_rst			<= '1';
+				cycle_reload	<= async_timespec.ncyc_release-1;
+				sn				<= release;
+				as.cs			<= '0';
+			end if;
+
+		when release =>
+			if cycle_cnt = 0 then
+				sn				<= idle;
+			end if;
+
+		when others =>
+			sn <= idle;
+			
+		end case;		
+	end process;
+
+	------------------------------------------------------------------
+	output_ctrl:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			async_cs	<= (not async_timespec.pol_cs) xor as.cs;
+			async_wr	<= (not async_timespec.pol_we) xor as.wr;
+			async_rd	<= (not async_timespec.pol_oe) xor as.rd;
+			async_rst	<= (not async_timespec.pol_rst) xor as.rst;
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	din_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if as.rd = '1' then
+				DAT_O(data_width-1 downto 0) 	<= async_d;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_addr:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				async_a		<= (others => '0');
+			elsif en = '1' and rdy = '1' then
+				async_a 	<= ADDR_I(addr_width-1 downto 0);
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	data_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if en = '1' and rdy = '1' then
+				data_reg 	<= DAT_I(data_width-1 downto 0);
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_SRDY:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				rdyo 	<= '1';
+			elsif en = '1' then
+				rdyo 	<= rdy and not rdyo;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_ACK:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O 	<= '0';
+			else
+				ACK_O 	<= ack;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+	output_data:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			async_d 	<= (others => 'Z');
+			if as.drive_d = '1' then
+				async_d 	<= data_reg;
+			end if;	
+		end if;
+	end process;
+
+	------------------------------------------------------------------
+
+end Behavioral;

lib/misc/bbfifo.vhd

@@ -0,0 +1,123 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity bbfifo is
+	Generic 
+	(
+		depth	   : integer := 2;
+		data_width : integer := 8
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		re			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		ready		: out STD_LOGIC;
+		avail		: out STD_LOGIC;
+		din			: in  unsigned(data_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+end bbfifo;
+
+architecture Behavioral of bbfifo is
+
+	type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
+	signal req : unsigned(0 to depth);
+	signal rdy : unsigned(1 to depth+1);
+	signal bucket_array : bucket_array_t; 
+	signal ce_in : unsigned(1 to depth);
+	signal ce_out : unsigned(1 to depth);
+	
+begin
+	
+	req(0)			<= we;
+	rdy(depth+1)	<= re;
+	ready			<= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
+	avail			<= req(depth);
+	bucket_array(0)	<= din;
+	dout			<= bucket_array(depth);
+	
+gen_ce:
+	for i in 1 to depth generate
+	begin
+		process (rdy, req)
+		begin
+			ce_in(i) <= not req(i) and req(i-1);
+		end process;
+	end generate;
+
+gen_rdy:
+	for i in 1 to depth generate
+	begin
+		process (clk)
+		begin
+			if rising_edge(clk) then
+				if rst = '1' then
+					rdy(i) <= '1';
+				elsif req(i-1) = '1' then
+					rdy(i) <= rdy(i+1);
+				end if;
+			end if;
+		end process;
+	end generate;
+
+gen_req:
+	for i in 1 to depth generate
+	begin
+		process (clk)
+		begin
+			if rising_edge(clk) then
+				if rst = '1' then
+					req(i) <= '0';
+				elsif rdy(i+1) = '1' then
+					req(i) <= req(i-1);
+				end if;
+			end if;
+		end process;
+	end generate;
+
+gen_data:
+	for i in 1 to depth generate
+	begin
+		process (clk)
+		begin
+			if rising_edge(clk) then
+				if rst = '1' then
+					bucket_array(i) <= (others => '0');
+				elsif req(i-1) = '1' then
+					bucket_array(i) <= bucket_array(i-1);
+				end if;
+			end if;
+		end process;
+	end generate;
+
+end Behavioral;
+

lib/misc/clockgen_virtex4.vhd

@@ -0,0 +1,236 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Clock generator (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library ieee, work;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clockgen is
+	generic
+	(
+		sys1_phaseshift : integer := 0;
+		frequency_hz : integer := 100E6
+	);
+	port 
+	(
+		-- Clocks and Reset
+		rst				: in std_logic;   -- external async reset, low active
+		clk_in			: in std_logic;   -- system clock (e.g. 100MHz), from board
+		clk_fb_in		: in std_logic;   -- feedback clock
+		sys1_clk0_out	: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
+		sys1_clk270_out	: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
+		sys0_clk0_out	: out std_logic;  -- System clock #0, dcm#0 output 0°
+		sys0_clk270_out	: out std_logic;  -- System clock #0, dcm#0 output 270°
+		locked_out		: out std_logic;  -- DCM locked status
+		error_out		: out std_logic   -- indicates DCM Errors
+	);
+end;
+
+architecture tech of clockgen is
+
+	constant CLKIN_PER 				: real := real(1000E6/frequency_hz);
+
+	signal locked					: unsigned(1 downto 0);
+	signal dcm_rst					: unsigned(1 downto 0);
+	signal sys1_clk0				: std_logic;
+	signal sys1_clk270				: std_logic;
+	signal sys1_clk0_bufg			: std_logic;
+	signal sys1_clk270_bufg			: std_logic;
+	signal sys0_clk0					: std_logic;
+	signal sys0_clk270				: std_logic;
+	signal sys0_clk0_bufg			: std_logic;
+	signal sys0_clk270_bufg			: std_logic;
+	signal dcm1_locked, dcm2_locked	: unsigned(2 downto 0);
+	signal cnt_q 					: unsigned(4 downto 0);
+
+	type STATE_TYPE is (s0, s1, s2, s3, s4);
+	signal state_q : STATE_TYPE;
+
+begin 
+
+	sys1_clk0_out	<= sys1_clk0_bufg;
+	sys1_clk270_out	<= sys1_clk270_bufg;
+	sys0_clk0_out	<= sys0_clk0_bufg;
+	sys0_clk270_out	<= sys0_clk270_bufg;
+
+bufg11: bufg
+	port map
+	(
+		o  => sys0_clk0_bufg,  
+		i  => sys0_clk0
+	);
+
+bufg12: bufg
+	port map (
+		o  => sys0_clk270_bufg,  
+		i  => sys0_clk270
+	);
+
+bufg13: bufg
+	port map
+	(
+		o  => sys1_clk0_bufg,  
+		i  => sys1_clk0
+	);
+
+bufg14: bufg
+	port map (
+		o  => sys1_clk270_bufg,  
+		i  => sys1_clk270
+	);
+
+	-------------------------------------------------------------------------------------------------------
+	-- Clock generation
+	-------------------------------------------------------------------------------------------------------
+   
+inst_DCM_BASE_0 : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+									 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => sys0_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => sys0_clk270,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => open,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => locked(0),     -- DCM LOCK status output
+		CLKFB => clk_fb_in,       -- DCM clock feedback
+		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => dcm_rst(0)            -- DCM asynchronous reset input
+	);
+
+	inst_DCM_BASE_1 : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+									 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => sys1_phaseshift, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => sys1_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => sys1_clk270,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => open,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => locked(1),     -- DCM LOCK status output
+		CLKFB => sys1_clk0_bufg,       -- DCM clock feedback
+		CLKIN => clk_fb_in,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => dcm_rst(1)            -- DCM asynchronous reset input
+	);
+
+	dcm_rst(1) <= not locked(0);
+	
+dcm_fsm:
+	process(rst, clk_in)
+	begin
+		if rst = '1' then
+			state_q <= s0;
+			dcm_rst(0) <= '0';
+			cnt_q <= "11111";
+			error_out <= '0';
+			locked_out <= '0';
+			dcm1_locked <= (others => '0');
+			dcm2_locked <= (others => '0');
+		elsif rising_edge(clk_in) then
+			case state_q is
+			when s0 =>
+				state_q <= s1;
+
+			when s1 =>
+			cnt_q <= cnt_q - 1;
+				if cnt_q = 0 then
+					dcm_rst(0) <= '1';
+					state_q <= s2;
+				end if;
+
+			when s2 =>
+				cnt_q <= cnt_q - 1;
+				if cnt_q = 0 then
+					dcm_rst(0) <= '0';
+					state_q <= s3;
+				end if;
+
+			when s3 =>
+				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
+					state_q <= s4;
+					error_out <= '0';
+				end if;
+
+			when s4 =>
+				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
+					locked_out <= '1';
+				else
+					error_out <= '1';
+				end if;
+			end case;
+
+			-- synchronize 'dcm1_locked'
+			dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
+			dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
+
+		end if;
+	end process;
+
+end architecture tech;
+
+

lib/misc/gpio_wb.vhd

@@ -0,0 +1,211 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY gpio_wb IS
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+
+		sys_gpo0	: out unsigned(31 downto 0);
+		sys_gpo1	: out unsigned(31 downto 0);
+		sys_gpi0	: in  unsigned(31 downto 0);
+		sys_gpi1	: in  unsigned(31 downto 0)
+
+	);
+END gpio_wb;
+
+ARCHITECTURE behavior OF gpio_wb IS
+
+	signal gpo0_reg		: unsigned(31 downto 0);
+	signal gpo1_reg		: unsigned(31 downto 0);
+	signal gpi0_reg		: unsigned(31 downto 0);
+	signal gpi1_reg		: unsigned(31 downto 0);
+	-- Signals to form an timer generating an interrupt every microsecond
+	subtype tick_usec_t	is natural range 0 to 99;
+	signal tick_usec		: tick_usec_t;
+	signal cnt_usec			: unsigned(31 downto 0);
+	signal cnt_sec			: unsigned(31 downto 0);
+	signal cnt_usec_preset	: unsigned(31 downto 0);
+	signal cnt_sec_preset	: unsigned(31 downto 0);
+	signal cnt_usec_en		: std_logic;
+	signal cnt_usec_we		: std_logic;
+	signal cnt_sec_en		: std_logic;
+	signal cnt_sec_we		: std_logic;
+
+begin
+
+	SRDY_O	<= CYC_I;
+	
+------------------------------------------------------------------
+led_out:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			sys_gpo0	<= gpo0_reg;
+			sys_gpo1	<= gpo1_reg;
+		end if;
+	end process;	
+		
+------------------------------------------------------------------
+btn_ps2_in:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			gpi0_reg	<= sys_gpi0;
+			gpi1_reg	<= sys_gpi1;
+		end if;
+	end process;	
+		
+------------------------------------------------------------------
+registers_write: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			cnt_usec_we		<= '0';
+			cnt_sec_we		<= '0';
+			if RST_I = '1' then
+				gpo0_reg	<= (others => '0');
+				gpo1_reg	<= (others => '0');
+			elsif (STB_I and CYC_I and WE_I) = '1' then
+				case ADDR_I(5 downto 2) is
+				
+				when "0000" =>
+					if SEL_I(0) = '1' then
+						gpo0_reg(7 downto 0) <= DAT_I(7 downto 0);
+					end if;	
+					if SEL_I(1) = '1' then
+						gpo0_reg(15 downto 8) <= DAT_I(15 downto 8);
+					end if;	
+					if SEL_I(2) = '1' then
+						gpo0_reg(23 downto 16) <= DAT_I(23 downto 16);
+					end if;	
+					if SEL_I(3) = '1' then
+						gpo0_reg(31 downto 24) <= DAT_I(31 downto 24);
+					end if;	
+					
+				when "0001" =>
+					if SEL_I(0) = '1' then
+						gpo1_reg(7 downto 0) <= DAT_I(7 downto 0);
+					end if;	
+					if SEL_I(1) = '1' then
+						gpo1_reg(15 downto 8) <= DAT_I(15 downto 8);
+					end if;	
+					if SEL_I(2) = '1' then
+						gpo1_reg(23 downto 16) <= DAT_I(23 downto 16);
+					end if;	
+					if SEL_I(3) = '1' then
+						gpo1_reg(31 downto 24) <= DAT_I(31 downto 24);
+					end if;	
+					
+				when "0010" =>
+					if SEL_I(3) = '1' then
+						cnt_usec_we		<= '1';
+						cnt_usec_preset	<= DAT_I;
+					end if;	
+
+				when "0011" =>
+					if SEL_I(3) = '1' then
+						cnt_sec_we		<= '1';
+						cnt_sec_preset	<= DAT_I;
+					end if;	
+					
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+registers_read: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			ACK_O			<= '0';
+			if (STB_I and CYC_I) = '1' then
+				ACK_O		<= not WE_I;
+				DAT_O		<= (others => '0');
+				case ADDR_I(5 downto 2) is
+
+				when "0000" =>
+					DAT_O	<= gpi0_reg;
+
+				when "0001" =>
+					DAT_O	<= gpi1_reg;
+
+				when "0010" =>
+					DAT_O	<= cnt_usec;
+
+				when "0011" =>
+					DAT_O	<= cnt_sec;
+
+				when others => null;
+				end case;
+			end if;
+		end if;	
+	end process;
+
+tick_usec_timer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			cnt_usec_en		<= '0';
+			if RST_I = '1' then
+				tick_usec	<= 0;
+				cnt_usec_en	<= '0';
+			elsif tick_usec = tick_usec_t'high then
+				tick_usec		<= 0;
+				cnt_usec_en		<= '1';
+			else
+				tick_usec		<= tick_usec + 1;
+			end if;
+		end if;
+	end process;
+
+cnt_usec_timer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			cnt_sec_en		<= '0';
+			if RST_I = '1' then
+				cnt_usec	<= (others => '0');
+				cnt_sec_en	<= '0';
+			elsif cnt_usec_we = '1' then
+				cnt_usec		<= cnt_usec_preset;
+			elsif cnt_usec_en = '1' then
+				if cnt_usec = to_unsigned(1E6 - 1, 32) then
+					cnt_usec		<= (others => '0');
+					cnt_sec_en		<= '1';
+				else
+					cnt_usec		<= cnt_usec + 1;
+				end if;
+			end if;	
+		end if;
+	end process;
+
+cnt_sec_timer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cnt_sec		<= (others => '0');
+			elsif cnt_sec_we = '1' then
+				cnt_sec		<= cnt_sec_preset;
+			elsif cnt_sec_en = '1' then
+				cnt_sec		<= cnt_sec + 1;
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------------
+end behavior;

lib/misc/ram_sim.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY ram IS
+	Generic 
+	(
+		word_addr_width 	: integer := 6
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	constant depth : natural := 2**word_addr_width;
+	
+	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
+
+	function sram_clear return sram_t is
+
+	variable result : sram_t;
+	begin
+		for i in 0 to sram_t'length-1 loop
+			result(i) := (others => '0');
+		end loop;
+		return result;
+	end sram_clear;
+
+	signal sram : sram_t := sram_clear;
+	
+BEGIN
+
+
+SRAM_RW:
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(0) = '1' then
+				sram(index)(7 downto 0)		<= din(7 downto 0);
+			end if;	
+			if we(1) = '1' then
+				sram(index)(15 downto 8)	<= din(15 downto 8);
+			end if;	
+			if we(2) = '1' then
+				sram(index)(23 downto 16)	<= din(23 downto 16);
+			end if;	
+			if we(3) = '1' then
+				sram(index)(31 downto 24)	<= din(31 downto 24);
+			end if;	
+			dout <= sram(index);
+		end if;	
+	end process;
+	
+end behavior;

lib/misc/ram_wb.vhd

@@ -0,0 +1,80 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY ram_wb IS
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+END ram_wb;
+
+ARCHITECTURE behavior OF ram_wb IS
+
+	COMPONENT ram
+	GENERIC 
+	(
+		word_addr_width 	: integer
+	);
+	PORT 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	signal data_en : std_logic;
+	signal we : unsigned(3 downto 0);
+
+begin
+
+	we <= SEL_I and (3 downto 0 => WE_I);
+	
+	data_en	<= CYC_I and STB_I and MRDY_I;
+	SRDY_O	<= CYC_I;
+	
+data_valid_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O	<= '0';
+			else
+				ACK_O	<= data_en and not WE_I;
+			end if;
+		end if;
+	end process;
+
+inst_ram : ram
+	GENERIC MAP 
+	(
+		word_addr_width	=> 6
+	)
+	PORT MAP 
+	(
+		clk		=> CLK_I,
+		ce		=> data_en,
+		we		=> we,
+		addr	=> ADDR_I,
+		din		=> DAT_I,
+		dout	=> DAT_O
+	);
+
+
+
+end behavior;

lib/misc/rom_wb.vhd

@@ -0,0 +1,61 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY rom_wb IS
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0)
+	);
+END rom_wb;
+
+ARCHITECTURE behavior OF rom_wb IS
+
+	COMPONENT rom
+	PORT
+	(
+		clk		: in  STD_LOGIC;
+		ce		: in  STD_LOGIC;
+		addr	: in  unsigned(31 downto 0);
+		dout	: out unsigned(31 downto 0)
+	);
+	END COMPONENT;
+
+	signal data_en : std_logic;
+
+begin
+
+	data_en	<= CYC_I and STB_I and MRDY_I;
+	SRDY_O	<= CYC_I;
+	
+data_valid_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				ACK_O	<= '0';
+			else
+				ACK_O	<= data_en; -- and not WE_I;
+			end if;
+		end if;
+	end process;
+
+inst_rom : rom
+	PORT MAP
+	(
+		clk		=> CLK_I,
+		ce		=> data_en,
+		addr	=> ADDR_I,
+		dout	=> DAT_O
+	);
+
+
+end behavior;

lib/misc/sim/tb_bbfifo.fdo

@@ -0,0 +1,14 @@
+## NOTE:  Do not edit this file.
+##
+
+vlib work
+vcom -explicit  -93 "../bbfifo.vhd"
+vcom -explicit  -93 "../tb_bbfifo.vhd"
+
+#restart -force
+vsim -t 1ps   -lib work tb_bbfifo
+do {tb_bbfifo.wdo}
+view wave
+view structure
+view signals
+run 1us

lib/misc/sim/tb_bbfifo.wdo

@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_bbfifo/rst
+add wave -noupdate -format Logic /tb_bbfifo/clk
+add wave -noupdate -format Logic /tb_bbfifo/re
+add wave -noupdate -format Logic /tb_bbfifo/we
+add wave -noupdate -format Logic /tb_bbfifo/ready
+add wave -noupdate -format Logic /tb_bbfifo/avail
+add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
+add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/req
+add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/rdy
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_bbfifo/inst_bbfifo/bucket_array
+add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_in
+add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_out
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {170000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {76738 ps} {299465 ps}

lib/misc/sim/tb_ram_wb.fdo

@@ -0,0 +1,16 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+# Top and TB
+vcom -explicit  -93 "../ram_sim.vhd"
+vcom -explicit  -93 "../ram_wb.vhd"
+vcom -explicit  -93 "../tb_ram_wb.vhd"
+
+vsim -t 1ps   -lib work tb_ram_wb
+do {tb_ram_wb.wdo}
+view wave
+view structure
+view signals
+run 1.5us
+			 

lib/misc/sim/tb_ram_wb.wdo

@@ -0,0 +1,32 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_ram_wb/clk_o
+add wave -noupdate -format Logic /tb_ram_wb/rst_o
+add wave -noupdate -format Logic /tb_ram_wb/cyc_o
+add wave -noupdate -format Logic /tb_ram_wb/stb_o
+add wave -noupdate -format Logic /tb_ram_wb/we_o
+add wave -noupdate -format Literal /tb_ram_wb/sel_o
+add wave -noupdate -format Logic /tb_ram_wb/ack_i
+add wave -noupdate -format Logic /tb_ram_wb/mrdy_o
+add wave -noupdate -format Logic /tb_ram_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg
+add wave -noupdate -format Literal /tb_ram_wb/dout_cnt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {950000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {1575 ns}

lib/misc/sim/tb_rom_wb.fdo

@@ -0,0 +1,16 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+# Top and TB
+vcom -explicit  -93 "../rom_sim.vhd"
+vcom -explicit  -93 "../rom_wb.vhd"
+vcom -explicit  -93 "../tb_rom_wb.vhd"
+
+vsim -t 1ps   -lib work tb_rom_wb
+do {tb_rom_wb.wdo}
+view wave
+view structure
+view signals
+run 1us
+			 

lib/misc/sim/tb_rom_wb.wdo

@@ -0,0 +1,29 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_rom_wb/clk_o
+add wave -noupdate -format Logic /tb_rom_wb/rst_o
+add wave -noupdate -format Logic /tb_rom_wb/cyc_o
+add wave -noupdate -format Logic /tb_rom_wb/stb_o
+add wave -noupdate -format Logic /tb_rom_wb/ack_i
+add wave -noupdate -format Logic /tb_rom_wb/mrdy_o
+add wave -noupdate -format Logic /tb_rom_wb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dout_reg
+add wave -noupdate -format Literal /tb_rom_wb/dout_cnt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {796036 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {1050 ns}

lib/misc/tb_bbfifo.vhd

@@ -0,0 +1,136 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity tb_bbfifo is
+end;
+
+architecture behave of tb_bbfifo is
+
+	-- Number of user data words for simulation
+	constant CLK_PERIOD		: time := 10 ns;
+
+	signal rst				: std_logic := '1';  
+	signal clk				: std_logic := '1';  
+	signal re				: std_logic := '0';  
+	signal we				: std_logic := '0';  
+	signal ready			: std_logic;  
+	signal avail			: std_logic;  
+	signal din				: unsigned(7 downto 0) := (others => '0');
+	signal dout				: unsigned(7 downto 0);
+	signal dout_reg			: unsigned(7 downto 0);
+
+
+begin 
+   
+inst_bbfifo : entity work.bbfifo
+	GENERIC MAP 
+	(
+		depth		=> 4,
+		data_width	=> 8
+	)
+	PORT MAP
+	(
+		rst		=> rst,
+		clk		=> clk,
+		re		=> re,
+		we		=> we,
+		ready	=> ready,
+		avail	=> avail,
+		din		=> din,
+		dout	=> dout
+	);
+
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+RE_GEN: process
+	begin
+		wait for 2*CLK_PERIOD;
+		wait until rising_edge(clk) and avail = '1';
+		re <= '0';
+		dout_reg <= dout;
+		wait until rising_edge(clk);
+		re <= '0';
+	end process;
+
+------------------------------------------------------------------------------------------
+
+STIMULUS: process
+
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		din <= X"10";
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		wait until rising_edge(clk) and ready = '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '0';
+		wait until rising_edge(clk) and ready = '1';
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '0';
+		wait until rising_edge(clk) and ready = '1';
+		wait until rising_edge(clk) and ready = '1';
+		wait until rising_edge(clk) and ready = '1';
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		we <= '1';
+		din <= din + 1;
+		wait until rising_edge(clk) and ready = '1';
+		
+
+		wait; 
+	
+	end process;
+	
+end architecture behave;

lib/misc/tb_ram_wb.vhd

@@ -0,0 +1,408 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+ENTITY tb_ram_wb IS
+END tb_ram_wb;
+
+ARCHITECTURE behavior OF tb_ram_wb IS 
+
+	constant CLK_PERIOD : time := 10 ns;
+	signal CLK_O	: std_logic := '1';
+	signal RST_O	: std_logic := '1';
+	signal CYC_O	: std_logic := '0';
+	signal STB_O	: std_logic := '0';
+	signal WE_O		: std_logic := '0';
+	signal SEL_O	: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I	: std_logic;
+	signal MRDY_O	: std_logic := '1';
+	signal SRDY_I	: std_logic;
+	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I	: unsigned(31 downto 0);
+	signal DAT_O	: unsigned(31 downto 0) := (others => '-');
+
+	signal dout_rst			: std_logic := '0';
+	signal dout_reg			: unsigned(31 downto 0);
+	signal dout_cnt			: natural range 0 to 255;
+
+BEGIN
+
+inst_ram_wb : entity work.ram_wb
+	PORT MAP
+	(
+		RST_I		=> RST_O,
+		CLK_I		=> CLK_O,
+		CYC_I		=> CYC_O,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_I,
+		SRDY_O		=> SRDY_I,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> DAT_O,
+		DAT_O		=> DAT_I
+	);
+
+read_register:
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if dout_rst = '1' then
+				dout_cnt <= 0;
+			elsif ACK_I = '1' and WE_O = '0' then
+				dout_reg	<= DAT_I;
+				dout_cnt 	<= dout_cnt + 1;
+			end if;
+		end if;
+	end process;
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		RST_O <= '0';
+
+		-- 8 single cycles
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		DAT_O	<= X"1234_0000";
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		DAT_O	<= DAT_O + 1;
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		
+		-- 8-word burst cycle
+		wait for 3*CLK_PERIOD;
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		CYC_O	<= '0';
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SEL_O	<= "0011";
+		ADDR_O	<= X"0000_0080";
+		DAT_O	<= X"DEADBEEF";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(CLK_O);
+		-- 1-word burst cycle
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0080";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		-- 8-word burst cycle
+		wait for 3*CLK_PERIOD;
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		MRDY_O	<= '0';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		MRDY_O	<= '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and dout_cnt = 54;
+		CYC_O	<= '0';
+
+		wait; 
+	
+	end process;
+	
+END;

lib/misc/tb_rom_wb.vhd

@@ -0,0 +1,223 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+ENTITY tb_rom_wb IS
+END tb_rom_wb;
+
+ARCHITECTURE behavior OF tb_rom_wb IS 
+
+	constant CLK_PERIOD : time := 10 ns;
+	signal CLK_O	: std_logic := '1';
+	signal RST_O	: std_logic := '1';
+	signal CYC_O	: std_logic := '0';
+	signal STB_O	: std_logic := '0';
+	signal ACK_I	: std_logic;
+	signal MRDY_O	: std_logic := '1';
+	signal SRDY_I	: std_logic;
+	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I	: unsigned(31 downto 0);
+
+	signal dout_rst			: std_logic := '0';
+	signal dout_reg			: unsigned(31 downto 0);
+	signal dout_cnt			: natural range 0 to 255;
+
+BEGIN
+
+inst_rom_wb : entity work.rom_wb
+	PORT MAP
+	(
+		RST_I		=> RST_O,
+		CLK_I		=> CLK_O,
+		CYC_I		=> CYC_O,
+		STB_I		=> STB_O,
+		ACK_O		=> ACK_I,
+		SRDY_O		=> SRDY_I,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_O		=> DAT_I
+	);
+
+read_register:
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if dout_rst = '1' then
+				dout_cnt <= 0;
+			elsif ACK_I = '1' then
+				dout_reg	<= DAT_I;
+				dout_cnt 	<= dout_cnt + 1;
+			end if;
+		end if;
+	end process;
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		RST_O <= '0';
+
+		-- 8-word burst cycle
+		wait for 3*CLK_PERIOD;
+		dout_rst	<= '1';
+		wait until rising_edge(CLK_O);
+		dout_rst	<= '0';
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		ADDR_O	<= X"0000_0180";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		MRDY_O	<= '0';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		MRDY_O	<= '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		ADDR_O	<= ADDR_O + 4;
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		wait until rising_edge(CLK_O) and dout_cnt = 54;
+		CYC_O	<= '0';
+
+		wait; 
+	
+	end process;
+	
+END;

lib/uart/uart_wb.vhd

@@ -0,0 +1,186 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY uart_wb IS
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		INT_RX_O	: out STD_LOGIC;
+		INT_TX_O	: out STD_LOGIC;
+		ser_rx		: in std_logic;
+		ser_tx		: out std_logic
+	);
+END uart_wb;
+
+ARCHITECTURE behavior OF uart_wb IS
+
+	COMPONENT uart_tx
+    Port
+    (
+		data_in				: in std_logic_vector(7 downto 0);
+		write_buffer		: in std_logic;
+		reset_buffer		: in std_logic;
+		en_16_x_baud		: in std_logic;
+		serial_out			: out std_logic;
+		buffer_full			: out std_logic;
+		buffer_half_full	: out std_logic;
+		clk					: in std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT uart_rx
+	Port 
+	(
+		serial_in			: in std_logic;
+		data_out			: out std_logic_vector(7 downto 0);
+		read_buffer			: in std_logic;
+		reset_buffer		: in std_logic;
+		en_16_x_baud		: in std_logic;
+		buffer_data_present	: out std_logic;
+		buffer_full			: out std_logic;
+		buffer_half_full	: out std_logic;
+		clk					: in std_logic
+	);
+	END COMPONENT;
+
+	-- Signals for UART connections
+	signal baud_count		: unsigned(7 downto 0);
+	signal en_16_x_baud		: std_logic;
+	signal reg_we_uart_tx	: std_logic;
+	signal tx_full			: std_logic;
+	signal tx_half_full		: std_logic;
+	signal reg_re_uart_rx	: std_logic;
+	signal reg_uart_tx		: unsigned(7 downto 0);
+	signal reg_uart_rx		: std_logic_vector(7 downto 0);
+	signal rx_data_present	: std_logic;
+	signal rx_full			: std_logic;
+	signal rx_half_full		: std_logic;
+	signal uart_status_port	: unsigned(7 downto 0);
+	signal reg_uart_ctrl	: unsigned(7 downto 0);
+	signal reg_uart_baud	: unsigned(7 downto 0);
+
+begin
+
+	SRDY_O	<= CYC_I;
+	
+------------------------------------------------------------------
+registers_write: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			reg_we_uart_tx	<= '0';
+			if RST_I = '1' then
+				reg_uart_baud	<= to_unsigned(53, 8);
+				reg_uart_ctrl	<= to_unsigned(0, 8);
+			elsif (STB_I and CYC_I and WE_I) = '1' then
+				case ADDR_I(5 downto 2) is
+				
+				when "0000" =>
+					if SEL_I(0) = '1' then
+						reg_we_uart_tx	<= '1';
+						reg_uart_tx <= DAT_I(7 downto 0);
+					end if;	
+					
+				when "0001" =>
+					if SEL_I(0) = '1' then
+						reg_uart_ctrl	<= DAT_I(7 downto 0);
+					end if;	
+
+				when "0010" =>
+					if SEL_I(0) = '1' then
+						reg_uart_baud	<= DAT_I(7 downto 0);
+					end if;	
+
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+registers_read: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			reg_re_uart_rx	<= '0';
+			ACK_O			<= '0';
+			if (STB_I and CYC_I) = '1' then
+				ACK_O		<= not WE_I;
+				DAT_O		<= (others => '0');
+				case ADDR_I(5 downto 2) is
+
+				when "0000" =>
+					reg_re_uart_rx		<= not WE_I;
+					DAT_O(7 downto 0)	<= unsigned(reg_uart_rx);
+
+				when "0001" =>
+					DAT_O(7 downto 0)	<= uart_status_port;
+
+				when "0010" =>
+					DAT_O(7 downto 0)	<= reg_uart_baud;
+
+				when others => null;
+				end case;
+			end if;
+		end if;	
+	end process;
+
+baud_timer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				baud_count <= (others => '0');
+			elsif baud_count = reg_uart_baud then
+				baud_count <= (others => '0');
+				en_16_x_baud <= '1';
+			else
+				baud_count <= baud_count + 1;
+				en_16_x_baud <= '0';
+			end if;
+		end if;
+	end process;
+
+inst_uart_tx: uart_tx 
+	port map
+	(
+		data_in				=> std_logic_vector(reg_uart_tx), 
+		write_buffer		=> reg_we_uart_tx,
+		reset_buffer		=> RST_I,
+		en_16_x_baud		=> en_16_x_baud,
+		serial_out			=> ser_tx,
+		buffer_full			=> tx_full,
+		buffer_half_full	=> tx_half_full,
+		clk					=> CLK_I
+	);
+	
+inst_uart_rx: uart_rx
+	port map
+	(
+		serial_in			=> ser_rx,
+		data_out			=> reg_uart_rx,
+		read_buffer			=> reg_re_uart_rx,
+		reset_buffer		=> RST_I,
+		en_16_x_baud		=> en_16_x_baud,
+		buffer_data_present => rx_data_present,
+		buffer_full			=> rx_full,
+		buffer_half_full	=> rx_half_full,
+		clk					=> CLK_I
+	);  
+
+	uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
+	INT_RX_O		<= rx_data_present;
+	INT_TX_O		<= not tx_full;
+
+end behavior;

projects/mips_sys/ise101/mips_sys/mips_sys.prj

@@ -0,0 +1,42 @@
+vhdl work "../../src/sdram_config.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vhdl work "../../../../lib/misc/utils_pkg.vhd"
+vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
+vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
+vhdl work "../../../../lib/uart/kcuart_tx.vhd"
+vhdl work "../../../../lib/uart/kcuart_rx.vhd"
+vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
+vhdl work "../../src/sys_types.vhd"
+vhdl work "../../src/ram_ld.vhd"
+vhdl work "../../src/bootloader.ROM_ld.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
+vhdl work "../../../../lib/uart/uart_tx.vhd"
+vhdl work "../../../../lib/uart/uart_rx.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
+vhdl work "../../../../lib/uart/uart_wb.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
+vhdl work "../../../../lib/misc/rom_wb.vhd"
+vhdl work "../../../../lib/misc/ram_wb.vhd"
+vhdl work "../../../../lib/misc/lcd_port.vhd"
+vhdl work "../../../../lib/misc/gpio_wb.vhd"
+vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
+vhdl work "../../../../lib/misc/async_port_wb.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vhdl work "../../src/mips_sys.vhd"

projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj

@@ -0,0 +1,42 @@
+vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
+vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
+vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"

projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf

@@ -0,0 +1,503 @@
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+CONFIG STEPPING = "ES";
+
+# Bus clock nets
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
+
+NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
+#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
+TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
+
+NET "sys_clk_in" LOC = "AE14";
+NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET "sys_rst_n_in" LOC = "D6";
+NET sys_rst_n_in PULLUP;
+NET "sys_rst_n_in" TIG;
+NET "rst" TIG;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET sys_error<0> LOC = V6;
+NET sys_error<1> LOC = L24;
+NET sys_error<*> IOSTANDARD = LVCMOS33;
+NET sys_error<*> DRIVE = 2;
+NET sys_error<*> TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// RS-232
+////////////////////////////////////////////////////////////////////////////
+NET sys_rx LOC = W2;
+NET sys_rx IOSTANDARD = LVCMOS33;
+NET sys_rx TIG;
+NET "sys_tx" LOC = "W1";
+NET sys_tx IOSTANDARD = LVCMOS33;
+NET "sys_tx" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches
+////////////////////////////////////////////////////////////////////////////
+# GPLED 0-3
+NET "sys_led<0>" LOC = "G5"; #GPLED0
+NET "sys_led<1>" LOC = "G6"; #GPLED1
+NET "sys_led<2>" LOC = "A11"; #GPLED2
+NET "sys_led<3>" LOC = "A12"; #GPLED3
+# North-East-South-West-Center LEDs
+NET "sys_led<4>" LOC = "F9"; # W LED
+NET "sys_led<5>" LOC = "E2"; # N LED
+NET "sys_led<6>" LOC = "E10"; # E LED
+NET "sys_led<7>" LOC = "A5"; # S LED
+NET "sys_led<8>" LOC = "C6"; # C LED
+NET "sys_led<*>" TIG;
+NET "sys_led<*>" SLEW = SLOW;
+NET "sys_led<*>" DRIVE = 2;
+#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
+# North-East-South-West-Center Buttons
+NET "sys_btn<0>" LOC = "E9"; # W Button
+NET "sys_btn<1>" LOC = "E7"; # N Button
+NET "sys_btn<2>" LOC = "F10"; # E Button
+NET "sys_btn<3>" LOC = "A6"; # S Button
+NET "sys_btn<4>" LOC = "B6"; # C Button
+NET "sys_btn<*>" TIG;
+NET "sys_btn<*>" PULLDOWN;
+#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
+# Dip Switches 1-8
+NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
+NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
+NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
+NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
+NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
+NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
+NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
+NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
+NET "sys_dip<*>" PULLDOWN;
+NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
+NET "sys_dip<*>" TIG;
+////////////////////////////////////////////////////////////////////////////
+// LCD
+////////////////////////////////////////////////////////////////////////////
+NET sys_lcd_e LOC = AE13; # LCD_E
+NET sys_lcd_e IOSTANDARD = LVCMOS33;
+NET sys_lcd_e SLEW = SLOW;
+NET sys_lcd_e DRIVE = 2;
+NET sys_lcd_e TIG;
+NET sys_lcd_rs LOC = AC17; # LCD_RS
+NET sys_lcd_rs IOSTANDARD = LVCMOS33;
+NET sys_lcd_rs SLEW = SLOW;
+NET sys_lcd_rs DRIVE = 2;
+NET sys_lcd_rs TIG;
+NET sys_lcd_rw LOC = AB17; # LCD_RW
+NET sys_lcd_rw IOSTANDARD = LVCMOS33;
+NET sys_lcd_rw SLEW = SLOW;
+NET sys_lcd_rw DRIVE = 2;
+NET sys_lcd_rw TIG;
+NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
+NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
+NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
+NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
+NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
+NET sys_lcd_d<*> SLEW = SLOW;
+NET sys_lcd_d<*> DRIVE = 2;
+NET sys_lcd_d<*> PULLDOWN;
+NET sys_lcd_d<*> TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
+NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
+NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
+NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
+NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
+NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
+NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
+NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
+NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
+NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
+NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
+NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
+NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
+NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
+NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
+NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
+NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
+NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
+NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
+NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
+
+NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
+NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
+
+NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
+NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
+NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
+NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
+
+NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
+NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
+NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
+NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
+
+NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
+NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
+NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
+NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
+NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
+NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
+NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
+NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
+NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
+NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
+NET sys_sdr_data<10>	LOC = C23; # DDR_D10
+NET sys_sdr_data<11>	LOC = C24; # DDR_D11
+NET sys_sdr_data<12>	LOC = A20; # DDR_D12
+NET sys_sdr_data<13>	LOC = A21; # DDR_D13
+NET sys_sdr_data<14>	LOC = D24; # DDR_D14
+NET sys_sdr_data<15>	LOC = E18; # DDR_D15
+NET sys_sdr_data<16>	LOC = F18; # DDR_D16
+NET sys_sdr_data<17>	LOC = A19; # DDR_D17
+NET sys_sdr_data<18>	LOC = F19; # DDR_D18
+NET sys_sdr_data<19>	LOC = B23; # DDR_D19
+NET sys_sdr_data<20>	LOC = E21; # DDR_D20
+NET sys_sdr_data<21>	LOC = D22; # DDR_D21
+NET sys_sdr_data<22>	LOC = D23; # DDR_D22
+NET sys_sdr_data<23>	LOC = B24; # DDR_D23
+NET sys_sdr_data<24>	LOC = E22; # DDR_D24
+NET sys_sdr_data<25>	LOC = F20; # DDR_D25
+NET sys_sdr_data<26>	LOC = H23; # DDR_D26
+NET sys_sdr_data<27>	LOC = G25; # DDR_D27
+NET sys_sdr_data<28>	LOC = G26; # DDR_D28
+NET sys_sdr_data<29>	LOC = H25; # DDR_D29
+NET sys_sdr_data<30>	LOC = H24; # DDR_D30
+NET sys_sdr_data<31>	LOC = H21; # DDR_D31
+
+NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_a_q<*>	FAST; 
+
+NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ba_q<*>	FAST; 
+
+NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cke_q		FAST; 
+
+NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_p		FAST; 
+NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
+NET sys_sdr_clk_fb	IOBDELAY = NONE; 
+NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_n		FAST; 
+
+NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_cs_qn		FAST; 
+
+NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ras_qn	FAST; 
+
+NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_we_qn		FAST; 
+
+NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
+NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dqs_q<*>	FAST; 
+
+NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dm_q<*>	FAST; 
+
+NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_data<*>	IOBDELAY = NONE; 
+NET sys_sdr_data<*>	FAST; 
+
+#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
+
+NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
+NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
+
+# Timing Constraint for DDR Feedback Clock
+NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
+
+# USB
+NET sys_usb_a<0>   LOC        = Y10;
+NET sys_usb_a<1>   LOC        = AA10;
+NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
+
+NET sys_usb_d<0>   LOC        = AB7;
+NET sys_usb_d<1>   LOC        = AC9;
+NET sys_usb_d<2>   LOC        = AB9;
+NET sys_usb_d<3>   LOC        = AE6;
+NET sys_usb_d<4>   LOC        = AD6;
+NET sys_usb_d<5>   LOC        = AF9;
+NET sys_usb_d<6>   LOC        = AE9;
+NET sys_usb_d<7>   LOC        = AD8;
+NET sys_usb_d<8>   LOC        = AC8;
+NET sys_usb_d<9>   LOC        = AF4;
+NET sys_usb_d<10>  LOC        = AE4;
+NET sys_usb_d<11>  LOC        = AD3;
+NET sys_usb_d<12>  LOC        = AC3;
+NET sys_usb_d<13>  LOC        = AF6;
+NET sys_usb_d<14>  LOC        = AF5;
+NET sys_usb_d<15>  LOC        = AA7;
+NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
+NET sys_usb_d<*>   SLEW       = FAST;
+NET sys_usb_d<*>   DRIVE      = 8;
+NET sys_usb_d<*>   PULLDOWN;
+
+NET sys_usb_rdn    LOC        = AA8;
+NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
+NET sys_usb_rdn    SLEW       = FAST;
+NET sys_usb_rdn    DRIVE      = 8;
+
+NET sys_usb_wrn    LOC        = Y8;
+NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
+NET sys_usb_wrn    SLEW       = FAST;
+NET sys_usb_wrn    DRIVE      = 8;
+
+NET sys_usb_csn    LOC        = AF10;
+NET sys_usb_csn    IOSTANDARD = LVCMOS33;
+NET sys_usb_csn    SLEW       = FAST;
+NET sys_usb_csn    DRIVE      = 8;
+
+NET sys_usb_rstn   LOC        = A7;
+NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
+NET sys_usb_rstn   TIG;
+
+NET sys_usb_int    LOC        = V5;
+NET sys_usb_int    IOSTANDARD = LVCMOS33;
+NET sys_usb_int    PULLDOWN;
+NET sys_usb_int    TIG;
+
+# FLASH
+NET sys_flash_ssram_a<24> LOC = T21;
+NET sys_flash_ssram_a<23> LOC = U20;
+NET sys_flash_ssram_a<22> LOC = T19;
+NET sys_flash_ssram_a<21> LOC = AC5;
+NET sys_flash_ssram_a<20> LOC = AB5;
+NET sys_flash_ssram_a<19> LOC = AC4;
+NET sys_flash_ssram_a<18> LOC = AB4;
+NET sys_flash_ssram_a<17> LOC = AB3;
+NET sys_flash_ssram_a<16> LOC = AA4;
+NET sys_flash_ssram_a<15> LOC = AA3;
+NET sys_flash_ssram_a<14> LOC = W5;
+NET sys_flash_ssram_a<13> LOC = W6;
+NET sys_flash_ssram_a<12> LOC = W3;
+NET sys_flash_ssram_a<11> LOC = AF3;
+NET sys_flash_ssram_a<10>  LOC = AE3;
+NET sys_flash_ssram_a<9>  LOC = AD2;
+NET sys_flash_ssram_a<8>  LOC = AD1;
+NET sys_flash_ssram_a<7>  LOC = AC2;
+NET sys_flash_ssram_a<6>  LOC = AC1;
+NET sys_flash_ssram_a<5>  LOC = AB2;
+NET sys_flash_ssram_a<4>  LOC = AB1;
+NET sys_flash_ssram_a<3>  LOC = AA1;
+NET sys_flash_ssram_a<2>  LOC = Y2;
+NET sys_flash_ssram_a<1>  LOC = Y1;
+NET sys_flash_ssram_a<0>  LOC = T20;
+NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33;
+NET sys_flash_ssram_a<*>  SLEW = FAST;
+NET sys_flash_ssram_a<*>  DRIVE = 8;
+
+
+NET sys_flash_ssram_d<31> LOC = F14;
+NET sys_flash_ssram_d<30> LOC = F13;
+NET sys_flash_ssram_d<29> LOC = F12;
+NET sys_flash_ssram_d<28> LOC = F11;
+NET sys_flash_ssram_d<27> LOC = F16;
+NET sys_flash_ssram_d<26> LOC = F15;
+NET sys_flash_ssram_d<25> LOC = D14;
+NET sys_flash_ssram_d<24> LOC = D13;
+NET sys_flash_ssram_d<23> LOC = D15;
+NET sys_flash_ssram_d<22> LOC = E14;
+NET sys_flash_ssram_d<21> LOC = C11;
+NET sys_flash_ssram_d<20> LOC = D11;
+NET sys_flash_ssram_d<19> LOC = D16;
+NET sys_flash_ssram_d<18> LOC = C16;
+NET sys_flash_ssram_d<17> LOC = E13;
+NET sys_flash_ssram_d<16> LOC = D12;
+NET sys_flash_ssram_d<15> LOC = AA14;
+NET sys_flash_ssram_d<14> LOC = AB14;
+NET sys_flash_ssram_d<13> LOC = AC12;
+NET sys_flash_ssram_d<12> LOC = AC11;
+NET sys_flash_ssram_d<11> LOC = AA16;
+NET sys_flash_ssram_d<10> LOC = AA15;
+NET sys_flash_ssram_d<9>  LOC = AB13;
+NET sys_flash_ssram_d<8>  LOC = AA13;
+NET sys_flash_ssram_d<7>  LOC = AC14;
+NET sys_flash_ssram_d<6>  LOC = AD14;
+NET sys_flash_ssram_d<5>  LOC = AA12;
+NET sys_flash_ssram_d<4>  LOC = AA11;
+NET sys_flash_ssram_d<3>  LOC = AC16;
+NET sys_flash_ssram_d<2>  LOC = AC15;
+NET sys_flash_ssram_d<1>  LOC = AC13;
+NET sys_flash_ssram_d<0>  LOC = AD13;
+NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33;
+NET sys_flash_ssram_d<*> DRIVE = 12;
+NET sys_flash_ssram_d<*> SLEW = FAST;
+NET sys_flash_ssram_d<*> PULLDOWN;
+
+NET sys_flash_ssram_oe_n     LOC = AC6;
+NET sys_flash_ssram_oe_n    IOSTANDARD = LVDCI_33;
+NET sys_flash_ssram_oe_n SLEW = FAST;
+NET sys_flash_ssram_oe_n DRIVE = 8;
+
+NET sys_flash_ssram_we_n     LOC = AB6;
+NET sys_flash_ssram_we_n    IOSTANDARD = LVDCI_33;
+NET sys_flash_ssram_we_n SLEW = FAST;
+NET sys_flash_ssram_we_n DRIVE = 8;
+
+NET sys_flash_ce      LOC = W7;
+NET sys_flash_ce           IOSTANDARD = LVDCI_33;
+NET sys_flash_ce SLEW = FAST;
+NET sys_flash_ce DRIVE = 8;
+
+NET sys_flash_rstn    LOC = AD10;
+NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
+NET sys_flash_rstn    DRIVE = 8;
+NET sys_flash_rstn    SLEW = FAST;
+NET sys_flash_rstn           TIG;
+
+NET sys_flash_byten   LOC = N22;
+NET sys_flash_byten          IOSTANDARD = LVCMOS33;
+NET sys_flash_byten          DRIVE = 8;
+NET sys_flash_byten          SLEW = FAST;
+NET sys_flash_byten          TIG;
+
+# SSRAM
+NET sys_ssram_clk            LOC = AF7;
+NET sys_ssram_clk            IOSTANDARD = LVCMOS33;
+NET sys_ssram_clk            DRIVE = 16;
+NET sys_ssram_clk            SLEW = FAST;
+
+NET "sys_ssram_clk" TNM_NET = "ssram_clk";
+#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %;
+
+
+NET sys_ssram_clk_fb         LOC = AD17;
+NET sys_ssram_clk_fb         IOSTANDARD = LVCMOS33;
+
+# Timing Constraint for Feedback Clock
+NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk;
+
+NET sys_ssram_ce_n           LOC = V7;
+NET sys_ssram_ce_n           IOSTANDARD = LVDCI_33;
+NET sys_ssram_ce_n           SLEW = FAST;
+NET sys_ssram_ce_n           DRIVE = 8;
+
+NET sys_ssram_bw_n<3>        LOC = Y3; #Y4; 
+NET sys_ssram_bw_n<2>        LOC = Y4; #Y3;
+NET sys_ssram_bw_n<1>        LOC = Y5; #Y6;
+NET sys_ssram_bw_n<0>        LOC = Y6; #Y5;
+NET sys_ssram_bw_n<*>        IOSTANDARD = LVDCI_33;
+NET sys_ssram_bw_n<*>        SLEW = FAST;
+NET sys_ssram_bw_n<*>        DRIVE = 8;
+
+NET sys_ssram_adv            LOC = W4;
+NET sys_ssram_adv            IOSTANDARD = LVDCI_33;
+NET sys_ssram_adv            SLEW = FAST;
+NET sys_ssram_adv            DRIVE = 8;
+
+NET sys_ssram_mode           LOC = V26;
+NET sys_ssram_mode           IOSTANDARD = LVDCI_33;
+NET sys_ssram_mode           SLEW = FAST;
+NET sys_ssram_mode           DRIVE = 8;
+
+
+# VGA
+NET sys_vga_blue<0> LOC = M21; # VGA_B0
+NET sys_vga_blue<1> LOC = M26; # VGA_B1
+NET sys_vga_blue<2> LOC = L26; # VGA_B2
+NET sys_vga_blue<3> LOC = C5;  # VGA_B3
+NET sys_vga_blue<4> LOC = C7;  # VGA_B4
+NET sys_vga_blue<5> LOC = B7;  # VGA_B5
+NET sys_vga_blue<6> LOC = G8;  # VGA_B6
+NET sys_vga_blue<7> LOC = F8;  # VGA_B7
+NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<*> SLEW = FAST;
+NET sys_vga_blue<*> DRIVE = 8;
+
+NET sys_vga_clk  LOC = AF8;
+NET sys_vga_clk  IOSTANDARD = LVDCI_33;
+NET sys_vga_clk  SLEW = FAST;
+NET sys_vga_clk  DRIVE = 8;
+
+NET sys_vga_green<0> LOC = M22; # VGA_G0
+NET sys_vga_green<1> LOC = M23; # VGA_G1
+NET sys_vga_green<2> LOC = M20; # VGA_G2
+NET sys_vga_green<3> LOC = E4;  # VGA_G3
+NET sys_vga_green<4> LOC = D3;  # VGA_G4
+NET sys_vga_green<5> LOC = H7;  # VGA_G5
+NET sys_vga_green<6> LOC = H8;  # VGA_G6
+NET sys_vga_green<7> LOC = C1;  # VGA_G7
+NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<*> SLEW = FAST;
+NET sys_vga_green<*> DRIVE = 8;
+
+NET sys_vga_hsync LOC = C10;
+NET sys_vga_hsync SLEW = FAST;
+NET sys_vga_hsync DRIVE = 8;
+#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_red<0> LOC = N23; #VGA_R0
+NET sys_vga_red<1> LOC = N24; #VGA_R1
+NET sys_vga_red<2> LOC = N25; #VGA_R2
+NET sys_vga_red<3> LOC = C2;  #VGA_R3
+NET sys_vga_red<4> LOC = G7;  #VGA_R4
+NET sys_vga_red<5> LOC = F7;  #VGA_R5
+NET sys_vga_red<6> LOC = E5;  #VGA_R6
+NET sys_vga_red<7> LOC = E6;  #VGA_R7
+NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<*> SLEW = FAST;
+NET sys_vga_red<*> DRIVE = 8;
+
+NET sys_vga_vsync LOC = A8;
+NET sys_vga_vsync SLEW = FAST;
+NET sys_vga_vsync DRIVE = 8;
+#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_blank_n LOC = M24;
+NET sys_vga_blank_n SLEW = FAST;
+NET sys_vga_blank_n DRIVE = 8;
+NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
+
+NET sys_vga_sync_n LOC = L23;
+NET sys_vga_sync_n SLEW = FAST;
+NET sys_vga_sync_n DRIVE = 8;
+NET sys_vga_sync_n IOSTANDARD = LVCMOS33;

projects/mips_sys/ise101/mips_sys/ucf/systest.ucf

@@ -0,0 +1,484 @@
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+CONFIG STEPPING = "ES";
+
+# Bus clock nets
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
+
+NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
+#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
+TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
+
+NET "sys_clk_in" LOC = "AE14";
+NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET "sys_rst_n_in" LOC = "D6";
+NET sys_rst_n_in PULLUP;
+NET "sys_rst_n_in" TIG;
+NET "rst" TIG;
+
+NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
+PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+
+INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
+# GOOD 1
+#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
+#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
+
+# GOOD 2 (smaller)
+#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ;
+#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ;
+
+# GOOD 3 (even smaller)
+#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ;
+#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ;
+
+# GOOD 4 (even more smaller)
+AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
+AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET sys_error<0> LOC = V6;
+NET sys_error<1> LOC = L24;
+NET sys_error<*> IOSTANDARD = LVCMOS33;
+NET sys_error<*> DRIVE = 2;
+NET sys_error<*> TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// RS-232
+////////////////////////////////////////////////////////////////////////////
+NET sys_rx LOC = W2;
+NET sys_rx IOSTANDARD = LVCMOS33;
+NET sys_rx TIG;
+NET "sys_tx" LOC = "W1";
+NET sys_tx IOSTANDARD = LVCMOS33;
+NET "sys_tx" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches
+////////////////////////////////////////////////////////////////////////////
+# GPLED 0-3
+NET "sys_led<0>" LOC = "G5"; #GPLED0
+NET "sys_led<1>" LOC = "G6"; #GPLED1
+NET "sys_led<2>" LOC = "A11"; #GPLED2
+NET "sys_led<3>" LOC = "A12"; #GPLED3
+# North-East-South-West-Center LEDs
+NET "sys_led<4>" LOC = "F9"; # W LED
+NET "sys_led<5>" LOC = "E2"; # N LED
+NET "sys_led<6>" LOC = "E10"; # E LED
+NET "sys_led<7>" LOC = "A5"; # S LED
+NET "sys_led<8>" LOC = "C6"; # C LED
+NET "sys_led<*>" TIG;
+NET "sys_led<*>" SLEW = SLOW;
+NET "sys_led<*>" DRIVE = 2;
+#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
+# North-East-South-West-Center Buttons
+NET "sys_btn<0>" LOC = "E9"; # W Button
+NET "sys_btn<1>" LOC = "E7"; # N Button
+NET "sys_btn<2>" LOC = "F10"; # E Button
+NET "sys_btn<3>" LOC = "A6"; # S Button
+NET "sys_btn<4>" LOC = "B6"; # C Button
+NET "sys_btn<*>" TIG;
+NET "sys_btn<*>" PULLDOWN;
+#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
+# Dip Switches 1-8
+NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
+NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
+NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
+NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
+NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
+NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
+NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
+NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
+NET "sys_dip<*>" PULLDOWN;
+NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
+NET "sys_dip<*>" TIG;
+////////////////////////////////////////////////////////////////////////////
+// LCD
+////////////////////////////////////////////////////////////////////////////
+NET sys_lcd_e LOC = AE13; # LCD_E
+NET sys_lcd_e IOSTANDARD = LVCMOS33;
+NET sys_lcd_e SLEW = SLOW;
+NET sys_lcd_e DRIVE = 2;
+NET sys_lcd_e TIG;
+NET sys_lcd_rs LOC = AC17; # LCD_RS
+NET sys_lcd_rs IOSTANDARD = LVCMOS33;
+NET sys_lcd_rs SLEW = SLOW;
+NET sys_lcd_rs DRIVE = 2;
+NET sys_lcd_rs TIG;
+NET sys_lcd_rw LOC = AB17; # LCD_RW
+NET sys_lcd_rw IOSTANDARD = LVCMOS33;
+NET sys_lcd_rw SLEW = SLOW;
+NET sys_lcd_rw DRIVE = 2;
+NET sys_lcd_rw TIG;
+NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
+NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
+NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
+NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
+NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
+NET sys_lcd_d<*> SLEW = SLOW;
+NET sys_lcd_d<*> DRIVE = 2;
+NET sys_lcd_d<*> PULLDOWN;
+NET sys_lcd_d<*> TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
+NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
+NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
+NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
+NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
+NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
+NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
+NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
+NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
+NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
+NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
+NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
+NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
+NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
+NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
+NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
+NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
+NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
+NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
+NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
+
+NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
+NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
+
+NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
+NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
+NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
+NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
+
+NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
+NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
+NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
+NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
+
+NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
+NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
+NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
+NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
+NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
+NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
+NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
+NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
+NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
+NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
+NET sys_sdr_data<10>	LOC = C23; # DDR_D10
+NET sys_sdr_data<11>	LOC = C24; # DDR_D11
+NET sys_sdr_data<12>	LOC = A20; # DDR_D12
+NET sys_sdr_data<13>	LOC = A21; # DDR_D13
+NET sys_sdr_data<14>	LOC = D24; # DDR_D14
+NET sys_sdr_data<15>	LOC = E18; # DDR_D15
+NET sys_sdr_data<16>	LOC = F18; # DDR_D16
+NET sys_sdr_data<17>	LOC = A19; # DDR_D17
+NET sys_sdr_data<18>	LOC = F19; # DDR_D18
+NET sys_sdr_data<19>	LOC = B23; # DDR_D19
+NET sys_sdr_data<20>	LOC = E21; # DDR_D20
+NET sys_sdr_data<21>	LOC = D22; # DDR_D21
+NET sys_sdr_data<22>	LOC = D23; # DDR_D22
+NET sys_sdr_data<23>	LOC = B24; # DDR_D23
+NET sys_sdr_data<24>	LOC = E22; # DDR_D24
+NET sys_sdr_data<25>	LOC = F20; # DDR_D25
+NET sys_sdr_data<26>	LOC = H23; # DDR_D26
+NET sys_sdr_data<27>	LOC = G25; # DDR_D27
+NET sys_sdr_data<28>	LOC = G26; # DDR_D28
+NET sys_sdr_data<29>	LOC = H25; # DDR_D29
+NET sys_sdr_data<30>	LOC = H24; # DDR_D30
+NET sys_sdr_data<31>	LOC = H21; # DDR_D31
+
+NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_a_q<*>	FAST; 
+
+NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ba_q<*>	FAST; 
+
+NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cke_q		FAST; 
+
+NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_p		FAST; 
+NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
+NET sys_sdr_clk_fb	IOBDELAY = NONE; 
+NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_n		FAST; 
+
+NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_cs_qn		FAST; 
+
+NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ras_qn	FAST; 
+
+NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_we_qn		FAST; 
+
+NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
+NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dqs_q<*>	FAST; 
+
+NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dm_q<*>	FAST; 
+
+NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_data<*>	IOBDELAY = NONE; 
+NET sys_sdr_data<*>	FAST; 
+
+#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
+
+NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
+NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
+
+# Timing Constraint for DDR Feedback Clock
+NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
+
+# USB
+NET sys_usb_a<0>   LOC        = Y10;
+NET sys_usb_a<1>   LOC        = AA10;
+NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
+
+NET sys_usb_d<0>   LOC        = AB7;
+NET sys_usb_d<1>   LOC        = AC9;
+NET sys_usb_d<2>   LOC        = AB9;
+NET sys_usb_d<3>   LOC        = AE6;
+NET sys_usb_d<4>   LOC        = AD6;
+NET sys_usb_d<5>   LOC        = AF9;
+NET sys_usb_d<6>   LOC        = AE9;
+NET sys_usb_d<7>   LOC        = AD8;
+NET sys_usb_d<8>   LOC        = AC8;
+NET sys_usb_d<9>   LOC        = AF4;
+NET sys_usb_d<10>  LOC        = AE4;
+NET sys_usb_d<11>  LOC        = AD3;
+NET sys_usb_d<12>  LOC        = AC3;
+NET sys_usb_d<13>  LOC        = AF6;
+NET sys_usb_d<14>  LOC        = AF5;
+NET sys_usb_d<15>  LOC        = AA7;
+NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
+NET sys_usb_d<*>   SLEW       = FAST;
+NET sys_usb_d<*>   DRIVE      = 8;
+NET sys_usb_d<*>   PULLDOWN;
+
+NET sys_usb_rdn    LOC        = AA8;
+NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
+NET sys_usb_rdn    SLEW       = FAST;
+NET sys_usb_rdn    DRIVE      = 8;
+
+NET sys_usb_wrn    LOC        = Y8;
+NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
+NET sys_usb_wrn    SLEW       = FAST;
+NET sys_usb_wrn    DRIVE      = 8;
+
+NET sys_usb_csn    LOC        = AF10;
+NET sys_usb_csn    IOSTANDARD = LVCMOS33;
+NET sys_usb_csn    SLEW       = FAST;
+NET sys_usb_csn    DRIVE      = 8;
+
+NET sys_usb_rstn   LOC        = A7;
+NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
+NET sys_usb_rstn   TIG;
+
+NET sys_usb_int    LOC        = V5;
+NET sys_usb_int    IOSTANDARD = LVCMOS33;
+NET sys_usb_int    PULLDOWN;
+NET sys_usb_int    TIG;
+
+# FLASH
+NET sys_flash_a<24> LOC = T21;
+NET sys_flash_a<23> LOC = U20;
+NET sys_flash_a<22> LOC = T19;
+NET sys_flash_a<21> LOC = AC5;
+NET sys_flash_a<20> LOC = AB5;
+NET sys_flash_a<19> LOC = AC4;
+NET sys_flash_a<18> LOC = AB4;
+NET sys_flash_a<17> LOC = AB3;
+NET sys_flash_a<16> LOC = AA4;
+NET sys_flash_a<15> LOC = AA3;
+NET sys_flash_a<14> LOC = W5;
+NET sys_flash_a<13> LOC = W6;
+NET sys_flash_a<12> LOC = W3;
+NET sys_flash_a<11> LOC = AF3;
+NET sys_flash_a<10>  LOC = AE3;
+NET sys_flash_a<9>  LOC = AD2;
+NET sys_flash_a<8>  LOC = AD1;
+NET sys_flash_a<7>  LOC = AC2;
+NET sys_flash_a<6>  LOC = AC1;
+NET sys_flash_a<5>  LOC = AB2;
+NET sys_flash_a<4>  LOC = AB1;
+NET sys_flash_a<3>  LOC = AA1;
+NET sys_flash_a<2>  LOC = Y2;
+NET sys_flash_a<1>  LOC = Y1;
+NET sys_flash_a<0>  LOC = T20;
+
+NET sys_flash_d<31> LOC = F14;
+NET sys_flash_d<30> LOC = F13;
+NET sys_flash_d<29> LOC = F12;
+NET sys_flash_d<28> LOC = F11;
+NET sys_flash_d<27> LOC = F16;
+NET sys_flash_d<26> LOC = F15;
+NET sys_flash_d<25> LOC = D14;
+NET sys_flash_d<24> LOC = D13;
+NET sys_flash_d<23> LOC = D15;
+NET sys_flash_d<22> LOC = E14;
+NET sys_flash_d<21> LOC = C11;
+NET sys_flash_d<20> LOC = D11;
+NET sys_flash_d<19> LOC = D16;
+NET sys_flash_d<18> LOC = C16;
+NET sys_flash_d<17> LOC = E13;
+NET sys_flash_d<16> LOC = D12;
+NET sys_flash_d<15> LOC = AA14;
+NET sys_flash_d<14> LOC = AB14;
+NET sys_flash_d<13> LOC = AC12;
+NET sys_flash_d<12> LOC = AC11;
+NET sys_flash_d<11> LOC = AA16;
+NET sys_flash_d<10> LOC = AA15;
+NET sys_flash_d<9>  LOC = AB13;
+NET sys_flash_d<8>  LOC = AA13;
+NET sys_flash_d<7>  LOC = AC14;
+NET sys_flash_d<6>  LOC = AD14;
+NET sys_flash_d<5>  LOC = AA12;
+NET sys_flash_d<4>  LOC = AA11;
+NET sys_flash_d<3>  LOC = AC16;
+NET sys_flash_d<2>  LOC = AC15;
+NET sys_flash_d<1>  LOC = AC13;
+NET sys_flash_d<0>  LOC = AD13;
+NET sys_flash_rdn     LOC = AC6;
+NET sys_flash_wrn     LOC = AB6;
+NET sys_flash_ce      LOC = W7;
+NET sys_flash_rstn    LOC = AD10;
+NET sys_flash_byten   LOC = N22;
+
+NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
+NET sys_flash_a<*>  SLEW = FAST;
+NET sys_flash_a<*>  DRIVE = 8;
+
+NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
+NET sys_flash_d<*> DRIVE = 12;
+NET sys_flash_d<*> SLEW = FAST;
+NET sys_flash_d<*> PULLDOWN;
+
+NET sys_flash_rdn    IOSTANDARD = LVDCI_33;
+NET sys_flash_rdn SLEW = FAST;
+NET sys_flash_rdn DRIVE = 8;
+
+NET sys_flash_wrn    IOSTANDARD = LVDCI_33;
+NET sys_flash_wrn SLEW = FAST;
+NET sys_flash_wrn DRIVE = 8;
+
+NET sys_flash_ce           IOSTANDARD = LVDCI_33;
+NET sys_flash_ce SLEW = FAST;
+NET sys_flash_ce DRIVE = 8;
+
+NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
+NET sys_flash_rstn    DRIVE = 8;
+NET sys_flash_rstn    SLEW = FAST;
+NET sys_flash_rstn    TIG;
+
+NET sys_flash_byten    IOSTANDARD = LVCMOS33;
+NET sys_flash_byten    DRIVE = 8;
+NET sys_flash_byten    SLEW = FAST;
+NET sys_flash_byten    TIG;
+
+# VGA
+NET sys_vga_blue<0> LOC = M21; # VGA_B0
+NET sys_vga_blue<1> LOC = M26; # VGA_B1
+NET sys_vga_blue<2> LOC = L26; # VGA_B2
+NET sys_vga_blue<3> LOC = C5;  # VGA_B3
+NET sys_vga_blue<4> LOC = C7;  # VGA_B4
+NET sys_vga_blue<5> LOC = B7;  # VGA_B5
+NET sys_vga_blue<6> LOC = G8;  # VGA_B6
+NET sys_vga_blue<7> LOC = F8;  # VGA_B7
+NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<*> SLEW = FAST;
+NET sys_vga_blue<*> DRIVE = 8;
+
+NET sys_vga_clk  LOC = AF8;
+NET sys_vga_clk  IOSTANDARD = LVDCI_33;
+NET sys_vga_clk  SLEW = FAST;
+NET sys_vga_clk  DRIVE = 8;
+
+NET sys_vga_green<0> LOC = M22; # VGA_G0
+NET sys_vga_green<1> LOC = M23; # VGA_G1
+NET sys_vga_green<2> LOC = M20; # VGA_G2
+NET sys_vga_green<3> LOC = E4;  # VGA_G3
+NET sys_vga_green<4> LOC = D3;  # VGA_G4
+NET sys_vga_green<5> LOC = H7;  # VGA_G5
+NET sys_vga_green<6> LOC = H8;  # VGA_G6
+NET sys_vga_green<7> LOC = C1;  # VGA_G7
+NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<*> SLEW = FAST;
+NET sys_vga_green<*> DRIVE = 8;
+
+NET sys_vga_hsync LOC = C10;
+NET sys_vga_hsync SLEW = FAST;
+NET sys_vga_hsync DRIVE = 8;
+#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_red<0> LOC = N23; #VGA_R0
+NET sys_vga_red<1> LOC = N24; #VGA_R1
+NET sys_vga_red<2> LOC = N25; #VGA_R2
+NET sys_vga_red<3> LOC = C2;  #VGA_R3
+NET sys_vga_red<4> LOC = G7;  #VGA_R4
+NET sys_vga_red<5> LOC = F7;  #VGA_R5
+NET sys_vga_red<6> LOC = E5;  #VGA_R6
+NET sys_vga_red<7> LOC = E6;  #VGA_R7
+NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<*> SLEW = FAST;
+NET sys_vga_red<*> DRIVE = 8;
+
+NET sys_vga_vsync LOC = A8;
+NET sys_vga_vsync SLEW = FAST;
+NET sys_vga_vsync DRIVE = 8;
+#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_blank_n LOC = M24;
+NET sys_vga_blank_n SLEW = FAST;
+NET sys_vga_blank_n DRIVE = 8;
+NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
+
+NET sys_vga_sync_n LOC = L23;
+NET sys_vga_sync_n SLEW = FAST;
+NET sys_vga_sync_n DRIVE = 8;
+NET sys_vga_sync_n IOSTANDARD = LVCMOS33;

projects/mips_sys/ise92/mips_sys/mips_sys.prj

@@ -0,0 +1,43 @@
+vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../src/sdram_config.vhd"
+vhdl work "../../../../lib/misc/utils_pkg.vhd"
+vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
+vhdl work "../../../../lib/uart/kcuart_tx.vhd"
+vhdl work "../../../../lib/uart/kcuart_rx.vhd"
+vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
+vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
+vhdl work "../../src/sys_types.vhd"
+vhdl work "../../src/ram_ld.vhd"
+vhdl work "../../src/bootloader.ROM_ld.vhd"
+vhdl work "../../../../lib/uart/uart_tx.vhd"
+vhdl work "../../../../lib/uart/uart_rx.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/linefifo.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vhdl work "../../../../lib/uart/uart_wb.vhd"
+vhdl work "../../../../lib/misc/rom_wb.vhd"
+vhdl work "../../../../lib/misc/ram_wb.vhd"
+vhdl work "../../../../lib/misc/lcd_port.vhd"
+vhdl work "../../../../lib/misc/gpio_wb.vhd"
+vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
+vhdl work "../../../../lib/misc/async_port_wb.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
+vhdl work "../../src/mips_sys.vhd"

projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj

@@ -0,0 +1,43 @@
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
+vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
+vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\linefifo.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
+vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
+vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"

projects/mips_sys/ise92/mips_sys/ucf/systest.ucf

@@ -0,0 +1,469 @@
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+CONFIG STEPPING = "ES";
+
+# Bus clock nets
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
+
+NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
+#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
+TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
+
+NET "sys_clk_in" LOC = "AE14";
+NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET "sys_rst_n_in" LOC = "D6";
+NET sys_rst_n_in PULLUP;
+NET "sys_rst_n_in" TIG;
+NET "rst" TIG;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
+#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+
+# GOOD
+INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
+AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
+AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET sys_error<0> LOC = V6;
+NET sys_error<1> LOC = L24;
+NET sys_error<*> IOSTANDARD = LVCMOS33;
+NET sys_error<*> DRIVE = 2;
+NET sys_error<*> TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// RS-232
+////////////////////////////////////////////////////////////////////////////
+NET sys_rx LOC = W2;
+NET sys_rx IOSTANDARD = LVCMOS33;
+NET sys_rx TIG;
+NET "sys_tx" LOC = "W1";
+NET sys_tx IOSTANDARD = LVCMOS33;
+NET "sys_tx" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches
+////////////////////////////////////////////////////////////////////////////
+# GPLED 0-3
+NET "sys_led<0>" LOC = "G5"; #GPLED0
+NET "sys_led<1>" LOC = "G6"; #GPLED1
+NET "sys_led<2>" LOC = "A11"; #GPLED2
+NET "sys_led<3>" LOC = "A12"; #GPLED3
+# North-East-South-West-Center LEDs
+NET "sys_led<4>" LOC = "F9"; # W LED
+NET "sys_led<5>" LOC = "E2"; # N LED
+NET "sys_led<6>" LOC = "E10"; # E LED
+NET "sys_led<7>" LOC = "A5"; # S LED
+NET "sys_led<8>" LOC = "C6"; # C LED
+NET "sys_led<*>" TIG;
+NET "sys_led<*>" SLEW = SLOW;
+NET "sys_led<*>" DRIVE = 2;
+#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
+# North-East-South-West-Center Buttons
+NET "sys_btn<0>" LOC = "E9"; # W Button
+NET "sys_btn<1>" LOC = "E7"; # N Button
+NET "sys_btn<2>" LOC = "F10"; # E Button
+NET "sys_btn<3>" LOC = "A6"; # S Button
+NET "sys_btn<4>" LOC = "B6"; # C Button
+NET "sys_btn<*>" TIG;
+NET "sys_btn<*>" PULLDOWN;
+#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
+# Dip Switches 1-8
+NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
+NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
+NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
+NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
+NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
+NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
+NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
+NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
+NET "sys_dip<*>" PULLDOWN;
+NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
+NET "sys_dip<*>" TIG;
+////////////////////////////////////////////////////////////////////////////
+// LCD
+////////////////////////////////////////////////////////////////////////////
+NET sys_lcd_e LOC = AE13; # LCD_E
+NET sys_lcd_e IOSTANDARD = LVCMOS33;
+NET sys_lcd_e SLEW = SLOW;
+NET sys_lcd_e DRIVE = 2;
+NET sys_lcd_e TIG;
+NET sys_lcd_rs LOC = AC17; # LCD_RS
+NET sys_lcd_rs IOSTANDARD = LVCMOS33;
+NET sys_lcd_rs SLEW = SLOW;
+NET sys_lcd_rs DRIVE = 2;
+NET sys_lcd_rs TIG;
+NET sys_lcd_rw LOC = AB17; # LCD_RW
+NET sys_lcd_rw IOSTANDARD = LVCMOS33;
+NET sys_lcd_rw SLEW = SLOW;
+NET sys_lcd_rw DRIVE = 2;
+NET sys_lcd_rw TIG;
+NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
+NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
+NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
+NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
+NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
+NET sys_lcd_d<*> SLEW = SLOW;
+NET sys_lcd_d<*> DRIVE = 2;
+NET sys_lcd_d<*> PULLDOWN;
+NET sys_lcd_d<*> TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
+NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
+NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
+NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
+NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
+NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
+NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
+NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
+NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
+NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
+NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
+NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
+NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
+NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
+NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
+NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
+NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
+NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
+NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
+NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
+
+NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
+NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
+
+NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
+NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
+NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
+NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
+
+NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
+NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
+NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
+NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
+
+NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
+NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
+NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
+NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
+NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
+NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
+NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
+NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
+NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
+NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
+NET sys_sdr_data<10>	LOC = C23; # DDR_D10
+NET sys_sdr_data<11>	LOC = C24; # DDR_D11
+NET sys_sdr_data<12>	LOC = A20; # DDR_D12
+NET sys_sdr_data<13>	LOC = A21; # DDR_D13
+NET sys_sdr_data<14>	LOC = D24; # DDR_D14
+NET sys_sdr_data<15>	LOC = E18; # DDR_D15
+NET sys_sdr_data<16>	LOC = F18; # DDR_D16
+NET sys_sdr_data<17>	LOC = A19; # DDR_D17
+NET sys_sdr_data<18>	LOC = F19; # DDR_D18
+NET sys_sdr_data<19>	LOC = B23; # DDR_D19
+NET sys_sdr_data<20>	LOC = E21; # DDR_D20
+NET sys_sdr_data<21>	LOC = D22; # DDR_D21
+NET sys_sdr_data<22>	LOC = D23; # DDR_D22
+NET sys_sdr_data<23>	LOC = B24; # DDR_D23
+NET sys_sdr_data<24>	LOC = E22; # DDR_D24
+NET sys_sdr_data<25>	LOC = F20; # DDR_D25
+NET sys_sdr_data<26>	LOC = H23; # DDR_D26
+NET sys_sdr_data<27>	LOC = G25; # DDR_D27
+NET sys_sdr_data<28>	LOC = G26; # DDR_D28
+NET sys_sdr_data<29>	LOC = H25; # DDR_D29
+NET sys_sdr_data<30>	LOC = H24; # DDR_D30
+NET sys_sdr_data<31>	LOC = H21; # DDR_D31
+
+NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_a_q<*>	FAST; 
+
+NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ba_q<*>	FAST; 
+
+NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cke_q		FAST; 
+
+NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_p		FAST; 
+NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
+NET sys_sdr_clk_fb	IOBDELAY = NONE; 
+NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
+NET sys_sdr_clk_n		FAST; 
+
+NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_cas_qn	FAST; 
+
+NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_cs_qn		FAST; 
+
+NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
+NET sys_sdr_ras_qn	FAST; 
+
+NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
+NET sys_sdr_we_qn		FAST; 
+
+NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
+NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dqs_q<*>	FAST; 
+
+NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
+NET sys_sdr_dm_q<*>	FAST; 
+
+NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
+NET sys_sdr_data<*>	IOBDELAY = NONE; 
+NET sys_sdr_data<*>	FAST; 
+
+#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
+
+NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
+NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
+
+# Timing Constraint for DDR Feedback Clock
+NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
+
+# USB
+NET sys_usb_a<0>   LOC        = Y10;
+NET sys_usb_a<1>   LOC        = AA10;
+NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
+
+NET sys_usb_d<0>   LOC        = AB7;
+NET sys_usb_d<1>   LOC        = AC9;
+NET sys_usb_d<2>   LOC        = AB9;
+NET sys_usb_d<3>   LOC        = AE6;
+NET sys_usb_d<4>   LOC        = AD6;
+NET sys_usb_d<5>   LOC        = AF9;
+NET sys_usb_d<6>   LOC        = AE9;
+NET sys_usb_d<7>   LOC        = AD8;
+NET sys_usb_d<8>   LOC        = AC8;
+NET sys_usb_d<9>   LOC        = AF4;
+NET sys_usb_d<10>  LOC        = AE4;
+NET sys_usb_d<11>  LOC        = AD3;
+NET sys_usb_d<12>  LOC        = AC3;
+NET sys_usb_d<13>  LOC        = AF6;
+NET sys_usb_d<14>  LOC        = AF5;
+NET sys_usb_d<15>  LOC        = AA7;
+NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
+NET sys_usb_d<*>   SLEW       = FAST;
+NET sys_usb_d<*>   DRIVE      = 8;
+NET sys_usb_d<*>   PULLDOWN;
+
+NET sys_usb_rdn    LOC        = AA8;
+NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
+NET sys_usb_rdn    SLEW       = FAST;
+NET sys_usb_rdn    DRIVE      = 8;
+
+NET sys_usb_wrn    LOC        = Y8;
+NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
+NET sys_usb_wrn    SLEW       = FAST;
+NET sys_usb_wrn    DRIVE      = 8;
+
+NET sys_usb_csn    LOC        = AF10;
+NET sys_usb_csn    IOSTANDARD = LVCMOS33;
+NET sys_usb_csn    SLEW       = FAST;
+NET sys_usb_csn    DRIVE      = 8;
+
+NET sys_usb_rstn   LOC        = A7;
+NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
+NET sys_usb_rstn   TIG;
+
+NET sys_usb_int    LOC        = V5;
+NET sys_usb_int    IOSTANDARD = LVCMOS33;
+NET sys_usb_int    PULLDOWN;
+NET sys_usb_int    TIG;
+
+# FLASH
+NET sys_flash_a<24> LOC = T21;
+NET sys_flash_a<23> LOC = U20;
+NET sys_flash_a<22> LOC = T19;
+NET sys_flash_a<21> LOC = AC5;
+NET sys_flash_a<20> LOC = AB5;
+NET sys_flash_a<19> LOC = AC4;
+NET sys_flash_a<18> LOC = AB4;
+NET sys_flash_a<17> LOC = AB3;
+NET sys_flash_a<16> LOC = AA4;
+NET sys_flash_a<15> LOC = AA3;
+NET sys_flash_a<14> LOC = W5;
+NET sys_flash_a<13> LOC = W6;
+NET sys_flash_a<12> LOC = W3;
+NET sys_flash_a<11> LOC = AF3;
+NET sys_flash_a<10>  LOC = AE3;
+NET sys_flash_a<9>  LOC = AD2;
+NET sys_flash_a<8>  LOC = AD1;
+NET sys_flash_a<7>  LOC = AC2;
+NET sys_flash_a<6>  LOC = AC1;
+NET sys_flash_a<5>  LOC = AB2;
+NET sys_flash_a<4>  LOC = AB1;
+NET sys_flash_a<3>  LOC = AA1;
+NET sys_flash_a<2>  LOC = Y2;
+NET sys_flash_a<1>  LOC = Y1;
+NET sys_flash_a<0>  LOC = T20;
+
+NET sys_flash_d<31> LOC = F14;
+NET sys_flash_d<30> LOC = F13;
+NET sys_flash_d<29> LOC = F12;
+NET sys_flash_d<28> LOC = F11;
+NET sys_flash_d<27> LOC = F16;
+NET sys_flash_d<26> LOC = F15;
+NET sys_flash_d<25> LOC = D14;
+NET sys_flash_d<24> LOC = D13;
+NET sys_flash_d<23> LOC = D15;
+NET sys_flash_d<22> LOC = E14;
+NET sys_flash_d<21> LOC = C11;
+NET sys_flash_d<20> LOC = D11;
+NET sys_flash_d<19> LOC = D16;
+NET sys_flash_d<18> LOC = C16;
+NET sys_flash_d<17> LOC = E13;
+NET sys_flash_d<16> LOC = D12;
+NET sys_flash_d<15> LOC = AA14;
+NET sys_flash_d<14> LOC = AB14;
+NET sys_flash_d<13> LOC = AC12;
+NET sys_flash_d<12> LOC = AC11;
+NET sys_flash_d<11> LOC = AA16;
+NET sys_flash_d<10> LOC = AA15;
+NET sys_flash_d<9>  LOC = AB13;
+NET sys_flash_d<8>  LOC = AA13;
+NET sys_flash_d<7>  LOC = AC14;
+NET sys_flash_d<6>  LOC = AD14;
+NET sys_flash_d<5>  LOC = AA12;
+NET sys_flash_d<4>  LOC = AA11;
+NET sys_flash_d<3>  LOC = AC16;
+NET sys_flash_d<2>  LOC = AC15;
+NET sys_flash_d<1>  LOC = AC13;
+NET sys_flash_d<0>  LOC = AD13;
+NET sys_flash_rdn     LOC = AC6;
+NET sys_flash_wrn     LOC = AB6;
+NET sys_flash_ce      LOC = W7;
+NET sys_flash_rstn    LOC = AD10;
+NET sys_flash_byten   LOC = N22;
+
+NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
+NET sys_flash_a<*>  SLEW = FAST;
+NET sys_flash_a<*>  DRIVE = 8;
+
+NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
+NET sys_flash_d<*> DRIVE = 12;
+NET sys_flash_d<*> SLEW = FAST;
+NET sys_flash_d<*> PULLDOWN;
+
+NET sys_flash_rdn    IOSTANDARD = LVDCI_33;
+NET sys_flash_rdn SLEW = FAST;
+NET sys_flash_rdn DRIVE = 8;
+
+NET sys_flash_wrn    IOSTANDARD = LVDCI_33;
+NET sys_flash_wrn SLEW = FAST;
+NET sys_flash_wrn DRIVE = 8;
+
+NET sys_flash_ce           IOSTANDARD = LVDCI_33;
+NET sys_flash_ce SLEW = FAST;
+NET sys_flash_ce DRIVE = 8;
+
+NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
+NET sys_flash_rstn    DRIVE = 8;
+NET sys_flash_rstn    SLEW = FAST;
+NET sys_flash_rstn    TIG;
+
+NET sys_flash_byten    IOSTANDARD = LVCMOS33;
+NET sys_flash_byten    DRIVE = 8;
+NET sys_flash_byten    SLEW = FAST;
+NET sys_flash_byten    TIG;
+
+# VGA
+NET sys_vga_blue<0> LOC = M21; # VGA_B0
+NET sys_vga_blue<1> LOC = M26; # VGA_B1
+NET sys_vga_blue<2> LOC = L26; # VGA_B2
+NET sys_vga_blue<3> LOC = C5;  # VGA_B3
+NET sys_vga_blue<4> LOC = C7;  # VGA_B4
+NET sys_vga_blue<5> LOC = B7;  # VGA_B5
+NET sys_vga_blue<6> LOC = G8;  # VGA_B6
+NET sys_vga_blue<7> LOC = F8;  # VGA_B7
+NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_blue<*> SLEW = FAST;
+NET sys_vga_blue<*> DRIVE = 8;
+
+NET sys_vga_clk  LOC = AF8;
+NET sys_vga_clk  IOSTANDARD = LVDCI_33;
+NET sys_vga_clk  SLEW = FAST;
+NET sys_vga_clk  DRIVE = 8;
+
+NET sys_vga_green<0> LOC = M22; # VGA_G0
+NET sys_vga_green<1> LOC = M23; # VGA_G1
+NET sys_vga_green<2> LOC = M20; # VGA_G2
+NET sys_vga_green<3> LOC = E4;  # VGA_G3
+NET sys_vga_green<4> LOC = D3;  # VGA_G4
+NET sys_vga_green<5> LOC = H7;  # VGA_G5
+NET sys_vga_green<6> LOC = H8;  # VGA_G6
+NET sys_vga_green<7> LOC = C1;  # VGA_G7
+NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_green<*> SLEW = FAST;
+NET sys_vga_green<*> DRIVE = 8;
+
+NET sys_vga_hsync LOC = C10;
+NET sys_vga_hsync SLEW = FAST;
+NET sys_vga_hsync DRIVE = 8;
+#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_red<0> LOC = N23; #VGA_R0
+NET sys_vga_red<1> LOC = N24; #VGA_R1
+NET sys_vga_red<2> LOC = N25; #VGA_R2
+NET sys_vga_red<3> LOC = C2;  #VGA_R3
+NET sys_vga_red<4> LOC = G7;  #VGA_R4
+NET sys_vga_red<5> LOC = F7;  #VGA_R5
+NET sys_vga_red<6> LOC = E5;  #VGA_R6
+NET sys_vga_red<7> LOC = E6;  #VGA_R7
+NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
+NET sys_vga_red<*> SLEW = FAST;
+NET sys_vga_red<*> DRIVE = 8;
+
+NET sys_vga_vsync LOC = A8;
+NET sys_vga_vsync SLEW = FAST;
+NET sys_vga_vsync DRIVE = 8;
+#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
+
+NET sys_vga_blank_n LOC = M24;
+NET sys_vga_blank_n SLEW = FAST;
+NET sys_vga_blank_n DRIVE = 8;
+NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
+
+NET sys_vga_sync_n LOC = L23;
+NET sys_vga_sync_n SLEW = FAST;
+NET sys_vga_sync_n DRIVE = 8;
+NET sys_vga_sync_n IOSTANDARD = LVCMOS33;

projects/mips_sys/sim/tb_mips_sys.fdo

@@ -0,0 +1,98 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+# Configs
+vcom -explicit  -93 "../src/sdram_config_sim.vhd"
+
+# Packages
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
+vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
+
+# RAMs
+vcom -explicit  -93 "../../../lib/misc/dpram_2w2r.vhd"
+vcom -explicit  -93 "../../../lib/misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../../lib/misc/dpram_1w1r_dist.vhd"
+
+# FIFOS
+vcom -explicit  -93 "../../../lib/FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async.vhd"
+
+# CPU
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/dcache.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/icache.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
+vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
+vcom -explicit  -93 "../src/ram_sim.vhd"
+vcom -explicit  -93 "../src/bootloader.ROM.vhd"
+vcom -explicit  -93 "../../../lib/misc/ram_wb.vhd"
+vcom -explicit  -93 "../../../lib/misc/rom_wb.vhd"
+
+# VGA
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
+
+# UART
+vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
+vcom -explicit  -93 "../../../lib/uart/kcuart_rx.vhd"
+vcom -explicit  -93 "../../../lib/uart/kcuart_tx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_rx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_tx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_wb.vhd"
+
+# GPIO
+vcom -explicit  -93 "../../../lib/misc/gpio_wb.vhd"
+
+# LCD
+vcom -explicit  -93 "../../../lib/misc/lcd_port.vhd"
+
+# Flash and USB
+vcom -explicit  -93 "../src/sys_types.vhd"
+vcom -explicit  -93 "../../../lib/misc/async_port_wb.vhd"
+vcom -explicit  -93 "../../../lib/misc/flash_port_wb.vhd"
+
+# Sync SRAM
+vcom -explicit  -93 "../../../lib/SSRAM/src/package_utility.vhd"
+vcom -explicit  -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
+vcom -explicit  -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
+
+# SDRAM
+vcom -explicit  -93 "../../../lib/misc/clockgen_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
+
+# Top and TB
+vcom -explicit  -93 "../src/mips_sys_sim.vhd"
+vcom -explicit  -93 "../src/tb_mips_sys.vhd"
+
+vsim -t 1ps   -lib work tb_mips_sys
+do {tb_mips_sys.wdo}
+view wave
+view structure
+view signals
+run 20ms