This commit was manufactured by cvs2svn to create tag 'R7'.

git-svn-id: http://moon:8086/svn/vhdl/tags/R7@121 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/core/dcache.vhd

@@ -92,14 +92,13 @@ END COMPONENT;
 	constant cache_index_width	: natural := lg2(cache_size) - word_index_width;
 	constant tag_width			: natural := 32 - word_index_width - cache_index_width - 2;
 	constant tag_parity_width	: natural := 3;
-	constant tram_data_width	: natural := 2 + tag_parity_width + tag_width;
+	constant tram_data_width	: natural := 1 + tag_parity_width + tag_width;
 	constant tram_addr_width	: natural := cache_index_width;
 	
 	subtype	tram_data_t is unsigned (tram_data_width-1 downto 0);
 
 	type dcache_entry_t is record
 		valid	: std_logic;
-		dirty	: std_logic;
 		tv_p	: unsigned(tag_parity_width-1 downto 0);
 		tag		: unsigned(tag_width-1 downto 0);
 	end record;
@@ -112,9 +111,8 @@ END COMPONENT;
 	variable result : dcache_entry_t;
 	begin
 		result.valid	:= x(0);
-		result.dirty	:= x(1);
-		result.tv_p		:= x(4 downto 2);
-		result.tag		:= x(tag_width+4 downto 5);
+		result.tv_p		:= x(3 downto 1);
+		result.tag		:= x(tag_width+3 downto 4);
 		
 		return result;
 	end to_dcache_entry;
@@ -123,9 +121,8 @@ END COMPONENT;
 	variable result : tram_data_t;
 	begin
 		result(0)										:= x.valid;
-		result(1)										:= x.dirty;
-		result(4 downto 2)								:= x.tv_p;
-		result(tag_width+4 downto 5)					:= x.tag;
+		result(3 downto 1)								:= x.tv_p;
+		result(tag_width+3 downto 4)					:= x.tag;
 		
 		return result;
 	end to_tram_data;
@@ -321,7 +318,6 @@ cache_state:
 		cache_entry_in.tv_p		<= (others => '0');
 		cache_entry_in.tag		<= tag_index_reg;
 		cache_entry_in.valid	<= '0';
-		cache_entry_in.dirty	<= '0';
 		sn	<= s;
 		
 		case s is

lib/CPUs/MIPS/src/core/mips_bui.vhd

@@ -29,6 +29,11 @@ library work;
 use work.mips_types.all;
 
 entity bui is
+	Generic
+	(
+		icache_size	: natural := 2048;	-- words
+		dcache_size	: natural := 2048	-- words
+	);
 	Port
 	(
 		RST_I			: in  STD_LOGIC;
@@ -64,8 +69,8 @@ architecture behavior of bui is
 	COMPONENT icache
 	GENERIC
 	(
-		cache_size	: natural := 2048;	-- words
-		line_size	: natural := 8		-- words
+		cache_size	: natural;	-- words
+		line_size	: natural	-- words
 	);
 	PORT
 	(
@@ -88,8 +93,8 @@ architecture behavior of bui is
 	COMPONENT dcache
 	GENERIC
 	(
-		cache_size	: natural := 2048;	-- words
-		line_size	: natural := 8		-- words
+		cache_size	: natural;	-- words
+		line_size	: natural	-- words
 	);
 	PORT
 	(
@@ -217,7 +222,7 @@ read_cyc_register:
 inst_icache : icache
 	GENERIC MAP
 	(
-		cache_size	=> 2048,	-- words
+		cache_size	=> icache_size,	-- words
 		line_size	=> 8
 	)	
 	PORT MAP
@@ -242,7 +247,7 @@ inst_icache : icache
 inst_dcache : dcache
 	GENERIC MAP
 	(
-		cache_size	=> 2048,	-- words
+		cache_size	=> dcache_size,	-- words
 		line_size	=> 8
 	)
 	PORT MAP
@@ -295,11 +300,6 @@ inst_bout_fifo: entity work.fifo_sync_dist
 	bout_fifo_re		<= not bout_fifo_empty and SRDY_I;
 	
 	bout_fifo_we		<= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
--- 	bout_fifo_we		<= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
--- 						   STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
--- 						   STB_O_dcache when dcache_mem_gnt = '1' else
--- 						   STB_O_icache when icache_mem_gnt = '1' else '0';
-						   
 
 	bout_fifo_data_in	<= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
 	

lib/CPUs/MIPS/src/core/mips_cop.vhd

@@ -338,7 +338,7 @@ cop_register_read:
 				reg	:= test_reg;
 
 			when others =>
-				reg	:= X"DEADBEEF";
+				reg	:= (others => '-');
 
 			end case;	
 			dout	<= reg;

lib/CPUs/MIPS/src/core/mips_top.vhd

@@ -89,6 +89,11 @@ architecture rtl of mips_top is
 
 
 	COMPONENT bui
+	GENERIC
+	(
+		icache_size	: natural;
+		dcache_size	: natural
+	);
 	PORT
 	(
 		RST_I			: in  STD_LOGIC;
@@ -148,6 +153,11 @@ inst_pipeline: pipeline
 	);
 
 inst_bui: bui
+	GENERIC MAP
+	(
+		icache_size	=> 4096,	-- words
+		dcache_size	=> 4096		-- words
+	)
 	PORT MAP
 	(
 		RST_I			=> RST_I,

lib/CPUs/MIPS/syn/ise101/mips_top.prj

@@ -0,0 +1,20 @@
+vhdl work "../../src/core/mips_types.vhd"
+vhdl work "../../../../misc/dpram_2w2r.vhd"
+vhdl work "../../../../misc/dpram_1w1r_dist.vhd"
+vhdl work "../../../../misc/dpram_1w1r.vhd"
+vhdl work "../../../../FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../src/core/mips_instr.vhd"
+vhdl work "../../../../FIFO/src/fifo_sync_dist.vhd"
+vhdl work "../../src/core/mips_shifter.vhd"
+vhdl work "../../src/core/mips_reg.vhd"
+vhdl work "../../src/core/mips_muldiv.vhd"
+vhdl work "../../src/core/mips_idecode_rom.vhd"
+vhdl work "../../src/core/mips_cop.vhd"
+vhdl work "../../src/core/mips_bcu.vhd"
+vhdl work "../../src/core/mips_alu.vhd"
+vhdl work "../../src/core/icache.vhd"
+vhdl work "../../src/core/dcache.vhd"
+vhdl work "../../src/core/mips_pipeline.vhd"
+vhdl work "../../src/core/mips_bui.vhd"
+vhdl work "../../src/core/mips_top.vhd"

lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj

@@ -0,0 +1,20 @@
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"

lib/VGA_ctrl/src/char_gen.vhd

@@ -206,7 +206,7 @@ begin
 	    DATA        => char_rom_data
     );
 
-	inst_ascii_ram: entity work.dpram
+	inst_ascii_ram: entity work.dpram_1w1r
 	GENERIC MAP (
 		addr_width	=> A_RAM_ADDR_WIDTH,
 		data_width	=> A_RAM_DATA_WIDTH

projects/mips_sys/ise101/mips_sys/mips_sys.prj

@@ -9,7 +9,6 @@ vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
 vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
 vhdl work "../../../../lib/uart/kcuart_tx.vhd"
 vhdl work "../../../../lib/uart/kcuart_rx.vhd"
@@ -25,14 +24,14 @@ vhdl work "../../src/sys_types.vhd"
 vhdl work "../../src/ram_ld.vhd"
 vhdl work "../../src/bootloader.ROM_ld.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/linefifo.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
 vhdl work "../../../../lib/uart/uart_tx.vhd"
 vhdl work "../../../../lib/uart/uart_rx.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
 vhdl work "../../../../lib/uart/uart_wb.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
+vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
 vhdl work "../../../../lib/misc/rom_wb.vhd"
 vhdl work "../../../../lib/misc/ram_wb.vhd"
 vhdl work "../../../../lib/misc/lcd_port.vhd"

projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj

@@ -9,7 +9,6 @@ vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
 vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
@@ -25,14 +24,14 @@ vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\linefifo.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"

projects/mips_sys/ise91/mips_sys/mips_sys.prj

@@ -1,35 +0,0 @@
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
-vhdl work "../../src/sdram_config.vhd"
-vhdl work "../../../../lib/misc/utils_pkg.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../../../lib/misc/dpram_1w2r.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd"
-vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
-vhdl work "../../../../lib/uart/kcuart_tx.vhd"
-vhdl work "../../../../lib/uart/kcuart_rx.vhd"
-vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
-vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
-vhdl work "../../src/ram_ld.vhd"
-vhdl work "../../asm/bootloader/bootloader.ROM_ld.vhd"
-vhdl work "../../../../lib/uart/uart_tx.vhd"
-vhdl work "../../../../lib/uart/uart_rx.vhd"
-vhdl work "../../../../lib/misc/lcd_port.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
-vhdl work "../../src/mips_sys.vhd"

projects/mips_sys/ise91/mips_sys/mips_sys_vhdl.prj

@@ -1,35 +0,0 @@
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
-vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w2r.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
-vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\asm\bootloader\bootloader.ROM_ld.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
-vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"

projects/mips_sys/ise91/mips_sys/ucf/systest.ucf

@@ -1,245 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-CONFIG STEPPING = "ES";
-
-# Bus clock nets
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
-
-NET "sys_clk_in" LOC = "AE14";
-#NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET "sys_rst_n_in" LOC = "D6";
-NET sys_rst_n_in PULLUP;
-NET "sys_rst_n_in" TIG;
-NET "rst" TIG;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET sys_error<0> LOC = V6;
-NET sys_error<1> LOC = L24;
-#NET sys_error<*> IOSTANDARD = LVCMOS33;
-NET sys_error<*> DRIVE = 2;
-NET sys_error<*> TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// RS-232
-////////////////////////////////////////////////////////////////////////////
-NET sys_rx LOC = W2;
-#NET sys_rx IOSTANDARD = LVCMOS33;
-NET sys_rx TIG;
-NET "sys_tx" LOC = "W1";
-#NET sys_tx IOSTANDARD = LVCMOS33;
-NET "sys_tx" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches
-////////////////////////////////////////////////////////////////////////////
-# GPLED 0-3
-NET "sys_led<0>" LOC = "G5"; #GPLED0
-NET "sys_led<1>" LOC = "G6"; #GPLED1
-NET "sys_led<2>" LOC = "A11"; #GPLED2
-NET "sys_led<3>" LOC = "A12"; #GPLED3
-# North-East-South-West-Center LEDs
-NET "sys_led<4>" LOC = "F9"; # W LED
-NET "sys_led<5>" LOC = "E2"; # N LED
-NET "sys_led<6>" LOC = "E10"; # E LED
-NET "sys_led<7>" LOC = "A5"; # S LED
-NET "sys_led<8>" LOC = "C6"; # C LED
-NET "sys_led<*>" TIG;
-NET "sys_led<*>" SLEW = SLOW;
-NET "sys_led<*>" DRIVE = 2;
-#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
-# North-East-South-West-Center Buttons
-NET "sys_btn<0>" LOC = "E9"; # W Button
-NET "sys_btn<1>" LOC = "E7"; # N Button
-NET "sys_btn<2>" LOC = "F10"; # E Button
-NET "sys_btn<3>" LOC = "A6"; # S Button
-NET "sys_btn<4>" LOC = "B6"; # C Button
-NET "sys_btn<*>" TIG;
-NET "sys_btn<*>" PULLDOWN;
-#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
-# Dip Switches 1-8
-NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
-NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
-NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
-NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
-NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
-NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
-NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
-NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
-NET "sys_dip<*>" PULLDOWN;
-#NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
-NET "sys_dip<*>" TIG;
-////////////////////////////////////////////////////////////////////////////
-// LCD
-////////////////////////////////////////////////////////////////////////////
-NET sys_lcd_e LOC = AE13; # LCD_E
-#NET sys_lcd_e IOSTANDARD = LVCMOS33;
-NET sys_lcd_e SLEW = SLOW;
-NET sys_lcd_e DRIVE = 2;
-NET sys_lcd_e TIG;
-NET sys_lcd_rs LOC = AC17; # LCD_RS
-#NET sys_lcd_rs IOSTANDARD = LVCMOS33;
-NET sys_lcd_rs SLEW = SLOW;
-NET sys_lcd_rs DRIVE = 2;
-NET sys_lcd_rs TIG;
-NET sys_lcd_rw LOC = AB17; # LCD_RW
-#NET sys_lcd_rw IOSTANDARD = LVCMOS33;
-NET sys_lcd_rw SLEW = SLOW;
-NET sys_lcd_rw DRIVE = 2;
-NET sys_lcd_rw TIG;
-NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
-NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
-NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
-NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
-#NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
-NET sys_lcd_d<*> SLEW = SLOW;
-NET sys_lcd_d<*> DRIVE = 2;
-NET sys_lcd_d<*> PULLDOWN;
-NET sys_lcd_d<*> TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
-NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
-NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
-NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
-NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
-NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
-NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
-NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
-NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
-NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
-NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
-NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
-NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
-NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
-NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
-NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
-NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
-NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
-NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
-NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
-
-NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
-NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
-
-NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
-NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
-NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
-NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
-
-NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
-NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
-NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
-NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
-
-NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
-NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
-NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
-NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
-NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
-NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
-NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
-NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
-NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
-NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
-NET sys_sdr_data<10>	LOC = C23; # DDR_D10
-NET sys_sdr_data<11>	LOC = C24; # DDR_D11
-NET sys_sdr_data<12>	LOC = A20; # DDR_D12
-NET sys_sdr_data<13>	LOC = A21; # DDR_D13
-NET sys_sdr_data<14>	LOC = D24; # DDR_D14
-NET sys_sdr_data<15>	LOC = E18; # DDR_D15
-NET sys_sdr_data<16>	LOC = F18; # DDR_D16
-NET sys_sdr_data<17>	LOC = A19; # DDR_D17
-NET sys_sdr_data<18>	LOC = F19; # DDR_D18
-NET sys_sdr_data<19>	LOC = B23; # DDR_D19
-NET sys_sdr_data<20>	LOC = E21; # DDR_D20
-NET sys_sdr_data<21>	LOC = D22; # DDR_D21
-NET sys_sdr_data<22>	LOC = D23; # DDR_D22
-NET sys_sdr_data<23>	LOC = B24; # DDR_D23
-NET sys_sdr_data<24>	LOC = E22; # DDR_D24
-NET sys_sdr_data<25>	LOC = F20; # DDR_D25
-NET sys_sdr_data<26>	LOC = H23; # DDR_D26
-NET sys_sdr_data<27>	LOC = G25; # DDR_D27
-NET sys_sdr_data<28>	LOC = G26; # DDR_D28
-NET sys_sdr_data<29>	LOC = H25; # DDR_D29
-NET sys_sdr_data<30>	LOC = H24; # DDR_D30
-NET sys_sdr_data<31>	LOC = H21; # DDR_D31
-
-NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_a_q<*>	FAST; 
-
-NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ba_q<*>	FAST; 
-
-NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cke_q		FAST; 
-
-NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_p		FAST; 
-NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
-NET sys_sdr_clk_fb	IOBDELAY = NONE; 
-NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_n		FAST; 
-
-NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_cs_qn		FAST; 
-
-NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ras_qn	FAST; 
-
-NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_we_qn		FAST; 
-
-NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
-NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dqs_q<*>	FAST; 
-
-NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dm_q<*>	FAST; 
-
-NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_data<*>	IOBDELAY = NONE; 
-NET sys_sdr_data<*>	FAST; 
-
-#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
-
-
-# Timing Constraint for DDR Feedback Clock
-NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
-

projects/mips_sys/sim/tb_mips_sys.fdo

@@ -23,6 +23,7 @@ vcom -explicit  -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
 vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync.vhd"
 vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd"
 vcom -explicit  -93 "../../../lib/FIFO/src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async.vhd"
 
 # CPU
 vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
@@ -45,14 +46,12 @@ vcom -explicit  -93 "../../../lib/misc/rom_wb.vhd"
 # VGA
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/dpram.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/linefifo.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend.vhd"
+vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
 
 # UART
 vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
@@ -85,7 +84,7 @@ vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
 vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
 vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
 vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
+vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
 
 # Top and TB
 vcom -explicit  -93 "../src/mips_sys_sim.vhd"

projects/mips_sys/sim/tb_mips_sys.wdo

@@ -13,11 +13,11 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
 add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
 add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
 add wave -noupdate -format Logic /tb_mips_sys/refresh
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
 add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
@@ -31,15 +31,15 @@ add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
 add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_dm_wr_in
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_in
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_rd
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_wr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_data_r
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_data_vld
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/u_data_req_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/read_fifo_data_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/read_fifo_data_out
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_dm_wr_in
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_tag_in
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_tag_rd
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_tag_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_data_r
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/u_data_vld
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/inst_sdram_ctrl/u_data_req_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/read_fifo_data_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend64_wb/read_fifo_data_out
 add wave -noupdate -format Literal /tb_mips_sys/sys_error
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
@@ -83,20 +83,33 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
 add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
 add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
 add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_almost_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_almost_full
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/request_cnt
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/read_cnt
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/s
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/vga_master_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/vga_scan_rdy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_color_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_color_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/fifo_color_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/fifo_color_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/scan_rdy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_full
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_empty
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_almost_empty
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_almost_full
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/request_cnt
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/read_cnt
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/s
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/vga_master_en
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/vga_scan_rdy
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_color_re
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/fifo_color_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend64/fifo_color_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend64/fifo_color_in
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/scan_rdy
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_vga_frontend64/color_in
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/stat_scan
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/stat_hpos
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/stat_vpos
+add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend64/odd_pixel
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/we_w
+add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/re_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/ptr_w
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/ptr_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/inst_fifo_ctrl/gcnt_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/inst_fifo_ctrl/bcnt_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/inst_fifo_ctrl/gnxt_r
+add wave -noupdate -format Literal -radix unsigned /tb_mips_sys/uut/inst_vga_frontend64/inst_linefifo/inst_fifo_ctrl/bnxt_r
 add wave -noupdate -divider BUI
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_icache
@@ -253,10 +266,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_rdy
 add wave -noupdate -divider {User ROM}
-add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_addr
 add wave -noupdate -divider UUT
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
@@ -331,7 +340,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {971060308 ps} 0}
+WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {2346072600 ps} 0}
 configure wave -namecolwidth 218
 configure wave -valuecolwidth 130
 configure wave -justifyvalue left
@@ -345,4 +354,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {970843856 ps} {971236215 ps}
+WaveRestoreZoom {8083733091 ps} {8083879943 ps}