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BRANCH_MIPS_R14

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• 5fe93ed9ac - removed BURSTLEN from generics - fixed burst counter - fixed SDR PHY jens 2015-05-25 08:03:05 +00:00
• 5427d4cae0 - removed constants from sdram_types.vhd and put them to sdram_const.vhd - define burst length in sdram_config jens 2015-05-25 07:25:49 +00:00
• 0a90acac6d - fixed read clock jens 2015-05-24 18:43:27 +00:00
• e20785fc1e - added TPD_BOARD_SIM for wb32 - TPD_BOARD_SIM is still in work for DDR PHY jens 2015-05-24 18:29:28 +00:00
• 3a234769af - update wave jens 2015-05-24 18:27:52 +00:00
• bfa747571f - added RPD_BOARD_SIM - cleaned up - reduced SDRAM CLock to 100 MHz jens 2015-05-24 17:36:21 +00:00
• 32f0d8c23a - model clock skew correctly jens 2015-05-24 16:10:12 +00:00
• 2005b700c1 - fixed clock jens 2015-05-24 15:48:20 +00:00
• 5beeee9fa7 - wave update jens 2015-05-24 14:35:47 +00:00
• ca5a2b4958 - wave update jens 2015-05-24 14:33:40 +00:00
• 5c1b83fb1e - fixed unconstrained array jens 2015-05-24 14:33:27 +00:00
• d5ff73eb3c - removed unused port signals jens 2015-05-24 13:19:25 +00:00
• 06bc5d193e - fixed timing in config - fixed data drive jens 2015-05-24 13:13:17 +00:00
• bd65d611dd - adedd single data rate SDRAM jens 2015-05-24 12:54:57 +00:00
• fa8fadd8cc - renamed constants jens 2015-05-24 11:43:38 +00:00
• dfd8330e50 - removed hard coded constants jens 2015-05-24 11:41:39 +00:00
• 246d511246 - removed hard coded constants jens 2015-05-24 11:40:30 +00:00
• fa1bed5497 - removed hard coded constants jens 2015-05-24 11:35:09 +00:00
• 1b8dd20871 - removed hard coded constants jens 2015-05-24 11:28:03 +00:00
• dc0762a753 - removed unused port signals jens 2015-05-24 11:16:04 +00:00
• 670bad910d - fixed testbench jens 2015-05-24 10:45:48 +00:00
• 965590d383 - renamed config constants jens 2015-05-24 10:44:20 +00:00
• ddc3b8050e - renamed config constants - added dedicated config for DDR mt46v16m16 jens 2015-05-24 10:39:18 +00:00
• a0ad9a9182 - fixed mips_sys.vhd due to SDRAM changes jens 2015-05-24 10:15:01 +00:00
• b586cba1b0 - removed multi-source issue (Xilinx systhesis) for struct using in ports where individual elements are driven by different entities - turned async. reset into sync. reset jens 2015-05-24 10:11:56 +00:00
• 4cd72abd34 - fixed mips_sys_sim.vhd due to SDRAM changes jens 2015-05-24 09:58:56 +00:00
• 3f4cbf0377 - renamed to wb64 jens 2015-05-24 09:32:23 +00:00
• b828537c4d - sdram_ctrl_frontend_wb32.vhd.vhd implements J-Bus interface and exports abstract PHY interface - ctrl_ddr_wb32 wraps sdram_ctrl_frontend_wb32 and adds specific PHY. This is now our new top level file jens 2015-05-24 09:29:34 +00:00
• 678f09b925 - renamed jens 2015-05-24 09:23:10 +00:00
• f06a5b3eb8 - fixed Zwischenstand jens 2015-05-24 09:22:21 +00:00
• 477467abaa - renamed jens 2015-05-24 09:16:27 +00:00
• a4395aba8a - fixed jens 2015-05-24 09:10:18 +00:00
• 75583b4cc4 - renamed jens 2015-05-24 09:08:55 +00:00
• a0525f2d6b - renamed jens 2015-05-24 09:07:00 +00:00
• f55028c696 - pulled PHY out of sdram_ctrl_top.vhd - sdram_ctrl_frontend64_wb.vhd implements J-Bus interface and exports abstract PHY interface - ctrl_ddr_wb64 wraps sdram_ctrl_frontend64_wb and adds specific PHY. This is now our new top level file jens 2015-05-24 09:05:49 +00:00
• ce636ef1ec - introduced phy_in_t and phy_out_t jens 2015-05-24 08:15:35 +00:00
• 88d51424b9 - cleaned up interfaces - prepared for separating phy jens 2015-05-24 07:28:22 +00:00
• 4896105caf - deleted jens 2015-05-24 06:05:24 +00:00
• e18657267d - fixed path jens 2015-05-23 16:18:15 +00:00
• fc552de5b5 - added addional rom path from build folder jens 2015-05-23 16:10:10 +00:00
• f0c6196710 - fixed compile scripts jens 2015-05-23 16:04:34 +00:00
• 81b5e2f867 - added jens 2015-05-23 15:37:00 +00:00
• b9e398cd4b - deleted jens 2015-05-23 15:34:14 +00:00
• fea271f21e - deleted jens 2015-05-23 15:30:35 +00:00
• 9f42f0977e - cleaned up jens 2015-05-23 13:28:33 +00:00
• 2acd911f1a - cleaned up - removed concurrent statement from process jens 2015-05-23 11:42:43 +00:00
• bcb0678984 - partially fixed DCM nightmare jens 2015-05-23 11:32:09 +00:00
• 811eb68146 Synthesis depends also on UCF jens 2015-05-23 09:36:20 +00:00
• 97de048b7f - fixed ucf - cleaned up jens 2015-05-23 09:34:16 +00:00
• 1dc522c559 - keep clk0 jens 2015-05-23 09:33:27 +00:00
• 3c0747a0a3 - fixed jens 2015-05-23 08:58:36 +00:00
• 17eb8faee1 - fixed mips_sys jens 2015-05-23 08:56:24 +00:00
• a08fda26f5 - updated boot loader jens 2015-05-23 08:56:14 +00:00
• 3ddbfdff33 - cleaned up jens 2015-05-23 08:44:57 +00:00
• b1dfffbc2a renamed clock entity jens 2015-05-23 08:42:51 +00:00
• c6323411e1 - added jens 2015-05-23 08:35:44 +00:00
• 55f1bfea82 - cleaned up jens 2015-05-23 08:34:38 +00:00
• 208c2a6eec - fixed jens 2015-05-23 08:33:30 +00:00
• 1dc80701fe - renamed jens 2015-05-23 08:30:25 +00:00
• 628593a879 - simplified clock stuff jens 2015-05-23 08:30:01 +00:00
• 752b788327 moved jens 2015-05-23 08:18:37 +00:00
• 910638fa11 moved jens 2015-05-23 08:18:04 +00:00
• f1db5927e2 - reverted: SRDY dependent on SDRAM_RST0 jens 2015-05-23 08:05:31 +00:00
• 0d68ca00ac - working (SDRAM head) - use hello_sim for test bench - changed sys clock gen jens 2015-05-23 08:02:23 +00:00
• 7668dd7814 - fixed delta delay. clk0 is generated and evaluated ddr_phy_virtex4 in simulation step n. Entities using clk0_out are evaluated in simulation step n+1, causing data sampling during data change. jens 2015-05-23 07:38:25 +00:00
• 38593077e9 - changed props jens 2015-05-23 05:25:32 +00:00
• 47b93c6228 - ignore jens 2015-05-23 05:24:45 +00:00
• 22152cee0f - use old bootloader and run dhrystone jens 2015-05-22 22:10:13 +00:00
• 7c1cc7980b - working (SDRAM R1153) jens 2015-05-22 21:53:31 +00:00
• dfffc2ffc7 - SRDY dependent on SDRAM_RST0 jens 2015-05-22 19:47:38 +00:00
• be1bae5243 - added reset out jens 2015-05-22 19:35:46 +00:00
• 94665d9c19 [SDRAM-Controller] - refactored: moved clockgen into phy - removed async resets jens 2015-05-22 17:49:58 +00:00
• ba98d8e13e - added SDRAM model jens 2015-05-22 06:16:03 +00:00
• 62499069a2 - fixed type cast in test bench jens 2015-05-22 06:14:32 +00:00
• 1d6bd6979a - pull bootloader from mips software build jens 2015-05-22 06:03:51 +00:00
• 7314433047 - no extra effort jens 2015-05-21 19:19:30 +00:00
• 0dec1e970c - use 16k I/D-Cache jens 2015-05-21 18:43:48 +00:00
• b941473d61 - use default mapping and par settings jens 2015-05-21 18:42:56 +00:00
• a342eac188 - use area GOOD 3 jens 2015-05-21 18:34:47 +00:00
• 31de77081c Fixed jens 2015-05-21 18:12:33 +00:00
• 943a081c61 - fixed jens 2015-05-21 17:58:43 +00:00
• 08e0105ab2 - deleted jens 2015-05-21 17:53:07 +00:00
• 016c84ee80 - fixed jens 2015-05-21 17:52:39 +00:00
• ac38fe2513 Moved jens 2015-05-21 17:49:48 +00:00
• 2e66c57e0c - moved synthesis relevant files to project jens 2015-05-21 06:48:46 +00:00
• 0bbc4aeb6c - deleted jens 2015-05-21 06:43:20 +00:00
• a7f2f3e5bb Moved jens 2015-05-21 06:41:43 +00:00
• 6a6e02a46b - added jens 2015-05-21 06:39:25 +00:00
• a830a1e650 - fixed bitgen jens 2015-05-20 23:22:50 +00:00
• b4e40f2045 - fixed targets jens 2015-05-20 23:07:20 +00:00
• 35ff958aec - no copy jens 2015-05-20 22:48:37 +00:00
• 97c90054da - added jens 2015-05-20 22:47:16 +00:00
• 38bd9acd52 -deleted jens 2015-05-20 22:31:46 +00:00
• 1423984428 -deleted jens 2015-05-20 22:31:20 +00:00
• 4b9cba542b - deleted jens 2015-05-20 21:55:12 +00:00
• 7f780a37a5 - added mips_sys full flow jens 2015-05-20 21:54:44 +00:00
• d8c54b3aaf - added jens 2015-05-20 20:38:43 +00:00
• 0a8974c7cd - added jens 2015-05-20 20:30:34 +00:00
• 6034b51816 - fixed jens 2015-05-20 20:30:02 +00:00
• 136ce46020 - fixed jens 2015-05-20 20:29:40 +00:00