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BRANCH_MIPS_R14

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BRANCH_TEST

BRANCH_TEST_2

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EMAC_R0

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MIPS_R10

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MIPS_R10b

MIPS_R11

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• deb2fdbb90 - update fixed_pkg jens 2015-10-24 14:56:24 +00:00
• 6226f79562 - add generics for rounding mode and saturation mode jens 2015-10-24 14:39:32 +00:00
• e7e1b9118e - fixed valid signal - fixed wav write jens 2015-10-24 09:09:02 +00:00
• ee627567f2 - fixed fir_stage_sys-based filters jens 2015-10-24 08:39:35 +00:00
• 34ef0ebe93 no vmap of lib jens 2015-10-24 07:03:19 +00:00
• 46e1bd322c - fixed fir_stage_sys jens 2015-10-24 07:02:37 +00:00
• 41d5b6e409 - fixed rams jens 2015-10-23 05:50:48 +00:00
• fff35dc404 no vmap of lib jens 2015-10-23 05:49:32 +00:00
• c3ed579118 deleted jens 2015-10-23 05:44:17 +00:00
• 9a27ebc627 no vmap of lib jens 2015-10-23 05:43:53 +00:00
• e476537d89 deleted jens 2015-10-23 05:41:15 +00:00
• 1f37f0bfce no vmap of lib jens 2015-10-23 05:40:51 +00:00
• 988c245f76 deleted jens 2015-10-23 05:34:28 +00:00
• d0e2af2ee7 - fixed rams jens 2015-10-23 05:33:41 +00:00
• 374566a294 - use correct rams jens 2015-10-23 05:29:54 +00:00
• 7fff4289e3 deleted jens 2015-10-23 05:20:33 +00:00
• 70c9bcb8bc no vmap of lib jens 2015-10-23 05:20:05 +00:00
• 61bcdc2caa no vmap of lib jens 2015-10-23 05:19:18 +00:00
• 951713990f no vmap of lib jens 2015-10-23 04:52:27 +00:00
• c229af0f71 - added ieee_proposed jens 2015-10-23 04:43:48 +00:00
• f862b2a5ae - always consume command jens 2015-06-15 19:54:33 +00:00
• ed3a943777 [spi_flash_wb.vhd] - removed register interface - first write data, then command jens 2015-06-13 13:52:35 +00:00
• 2b459949bb - fixed pipelined access jens 2015-06-13 11:37:26 +00:00
• bdf60c1304 - fixed - reduced cache size in TB jens 2015-06-13 10:28:23 +00:00
• b22c3f79fa - fixed cache size dependent prefetch jens 2015-06-13 10:14:56 +00:00
• ad21a2febb - updated sim time jens 2015-06-13 10:02:07 +00:00
• f08e17b23f [spi_flash_wb.vhd] - added caching jens 2015-06-13 10:00:05 +00:00
• c7eed7504d [spi_flash_wb.vhd] - added caching jens 2015-06-13 09:57:36 +00:00
• f96a017bc7 [SPI master] - added XFER Busy to status - don't enqueue data or commands if in reset state jens 2015-06-13 09:56:57 +00:00
• ec40c08234 - added WB TB jens 2015-06-11 16:58:46 +00:00
• ed26cf7449 - updated jens 2015-06-10 20:04:20 +00:00
• 295095e2b0 - use SPI flash as SPI slave jens 2015-06-10 20:01:26 +00:00
• b19c4c2883 - added model jens 2015-06-10 20:00:51 +00:00
• 2edaa4d7cb - added models jens 2015-06-10 19:27:35 +00:00
• 8eb6b3ff9e - spi_master_wb: route through generics jens 2015-06-04 20:27:50 +00:00
• 53b731a4eb - read streaming with FIFO full wait jens 2015-06-04 18:49:49 +00:00
• 8f12925523 - addedtest with more than 32 bit read data jens 2015-06-04 16:39:42 +00:00
• 360bd90d0f - fixed read fifo clocks jens 2015-06-04 16:16:18 +00:00
• c9d75c5d52 - fixed spi reset jens 2015-06-04 15:55:58 +00:00
• 97543c8bbd - fixed cmd reg latching jens 2015-06-04 15:30:09 +00:00
• 84953b98b9 - added J-Bus interface jens 2015-06-04 13:45:05 +00:00
• bae4ed7e62 - fixed command size jens 2015-06-04 13:44:21 +00:00
• ca0b04c733 - increased CAT FIFO depth jens 2015-06-04 12:36:45 +00:00
• d1407db11d - added clock divider - fixed clock edge of Slave TX jens 2015-06-04 12:17:00 +00:00
• 8097a4f41c - fixes after renaming jens 2015-06-04 11:16:21 +00:00
• 2f16cf461a - renamed jens 2015-06-04 11:13:15 +00:00
• 407a33db94 - renamed jens 2015-06-04 11:12:48 +00:00
• 6605ecc2ac - Master RX and TX working jens 2015-06-04 11:09:56 +00:00
• 7ad5c7f3c2 [SPI] - use async. FIFOs jens 2015-06-02 19:16:16 +00:00
• fb41f345fa - use full address space jens 2015-05-31 16:56:10 +00:00
• 41f9574600 - added SPI (Zwischenstand) jens 2015-05-31 16:44:51 +00:00
• 4f08ade4e2 - fixed Piso data loss jens 2015-05-31 10:13:33 +00:00
• fd05664b04 - fixed A0 jens 2015-05-31 08:30:24 +00:00
• c569ae0bf0 - fixed bad timing jens 2015-05-30 18:33:56 +00:00
• 1963853702 - fixed byte order on sub-word writes jens 2015-05-30 16:35:13 +00:00
• 621e5b1747 - fixed multiple drivers jens 2015-05-30 14:09:05 +00:00
• bca2359c65 - use BL=2 jens 2015-05-30 14:00:04 +00:00
• dabea0e2ab - fixed write latency, which shall be zero jens 2015-05-30 13:59:21 +00:00
• 4016d60a4c - fixed port map jens 2015-05-30 12:30:18 +00:00
• 0e0a7e48a6 - reworked PISO and SIPO jens 2015-05-30 12:27:45 +00:00
• 99b30ba0cc - adde SIPO and PISO jens 2015-05-30 12:27:20 +00:00
• 5e4798bbab - minor change jens 2015-05-30 09:07:50 +00:00
• ec35a40898 - simplified PHY control signals jens 2015-05-30 09:07:36 +00:00
• 4646c2ef34 - simplified PHY control signals - revert apparent BURST fix jens 2015-05-30 08:31:08 +00:00
• b2c5bcb279 - minor changes to frontend - increased POWER_UP wait - added reset delay jens 2015-05-29 19:18:52 +00:00
• ae98d5f2d3 - added jens 2015-05-29 19:16:53 +00:00
• 9b65c9429e - added altera_mf jens 2015-05-29 13:15:53 +00:00
• bd1bb90bb0 - added Altera/De0-NAno implementation jens 2015-05-29 13:15:30 +00:00
• 2da60e2b54 - added Altera/De0-NAno implementation jens 2015-05-29 13:09:20 +00:00
• 4afbac8e59 - added altera_mf - fixed compile scripts jens 2015-05-29 11:06:47 +00:00
• a5bd5bf099 - update jens 2015-05-28 08:44:58 +00:00
• 8cac4b62d9 - fixed port map (Xilinx bug) jens 2015-05-28 05:40:41 +00:00
• 34b05078c4 - minor fix jens 2015-05-27 20:26:11 +00:00
• 6a777f0b86 - set TX-half full (S/W depends on it) jens 2015-05-27 19:05:25 +00:00
• b0c03c4449 - deleted jens 2015-05-27 16:30:05 +00:00
• b0a3645610 - fixed jens 2015-05-27 16:29:27 +00:00
• 84e492a1e8 [uart] - fixed Xilinx implementation jens 2015-05-27 16:28:42 +00:00
• d4008485e3 - fixed jens 2015-05-27 16:20:33 +00:00
• 194720b817 - added uart_types to prj jens 2015-05-27 16:19:15 +00:00
• 8a7119fa2f - deleted jens 2015-05-27 16:17:43 +00:00
• f52494f466 - deleted jens 2015-05-27 16:17:14 +00:00
• 7aa1eefb79 - uart changes - cleaned up prj jens 2015-05-27 16:15:56 +00:00
• 13488ae71e [UART] - ctrl is input jens 2015-05-27 15:59:43 +00:00
• 6588eb752a - updated jens 2015-05-27 15:59:10 +00:00
• 11fa96a4e7 [Uart] - uart_wb instantiates uart - merged uart_tx, uart_rx into uart - added uart implementations for Xilinx (kcuart) and Altera (JTAG) jens 2015-05-27 15:50:32 +00:00
• 4d598154ca - updated jens 2015-05-26 17:27:01 +00:00
• 4687df5154 - delete work on startup jens 2015-05-26 17:24:53 +00:00
• 3d9effde77 - reverted: disable gigabit ethernet by default jens 2015-05-26 17:24:11 +00:00
• 0c2fd3e928 - test: enable gigabit ethernet by default jens 2015-05-26 16:48:56 +00:00
• 5630152954 - deleted jens 2015-05-26 14:47:07 +00:00
• 1bc700a041 - generate CKE from SDRAM CMD fsm. Simplified interfaces jens 2015-05-25 12:13:27 +00:00
• ce79902c62 - fixed project files jens 2015-05-25 11:48:26 +00:00
• ca623db33b -added timing report jens 2015-05-25 11:38:22 +00:00
• 3edba6d5a7 - simplified CMD FSM jens 2015-05-25 11:37:41 +00:00
• d1893931ed - fixed cycle counter jens 2015-05-25 10:51:06 +00:00
• d0da5022ef [SDRAM CMD FSM] - bugfix Burst mode jens 2015-05-25 09:32:10 +00:00
• be66661fe9 - fixed jens 2015-05-25 08:14:53 +00:00
• 44551d28fd - fixed jens 2015-05-25 08:13:37 +00:00
• 6ea540f7c7 - fixed project files jens 2015-05-25 08:08:00 +00:00
• 5fe93ed9ac - removed BURSTLEN from generics - fixed burst counter - fixed SDR PHY jens 2015-05-25 08:03:05 +00:00