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- added mips_sys full flow

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1129 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-20 21:54:44 +00:00
parent d8c54b3aaf
commit 7f780a37a5
6 changed files with 391 additions and 1261 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/syn/ise101/Makefile
+11 -8
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@@ -1,12 +1,15 @@
.PHONY: clean
all: mips_top.ngc
all: netlist
PREQ := mips_top.prj mips_top.xst mips_top.lso
PRJ := mips_top
PREQ := $(PRJ).prj $(PRJ).xst $(PRJ).lso
DIRS := ./xst/tmp
mips_top.ngc: $(DIRS) $(PREQ)
xst -ifn mips_top.xst -intstyle xflow
netlist: $(PRJ).ngc
$(PRJ).ngc: $(DIRS) $(PREQ)
xst -ifn $(PRJ).xst -intstyle xflow
$(DIRS):
mkdir -p $(DIRS)
@@ -15,10 +18,10 @@ clean:
rm -rf ./xst
rm -rf ./xlnx_auto_0_xdb
rm -f xlnx_auto_0.ise
rm -f mips_top.ngc
rm -f mips_top.ngr
rm -f mips_top.srp
rm -f mips_top_xst.xrpt
rm -f $(PRJ).ngc
rm -f $(PRJ).ngr
rm -f $(PRJ).srp
rm -f $(PRJ)_xst.xrpt
projects/mips_sys/ise101/mips_sys/mips_sys.par
+98 -83
View File
@@ -1,20 +1,33 @@
Release 10.1.03 par K.39 (nt)
Release 10.1.03 par K.39 (lin64)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
JUPITER:: Tue Mar 09 13:07:50 2010
callisto:: Wed May 20 23:17:06 2015
par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
par -w -intstyle xflow -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
mips_sys.pcf
Constraints file: mips_sys.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE.
Loading device for application Rf_Device from file '4vsx35.nph' in environment /home/jens/Xilinx/10.1/ISE.
"mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
The STEPPING level for this design is ES.
This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is
targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any available performance and functional
enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
WARNING:Timing:3262 - Feedback on DCM or PLL inst_clockgen/inst_DCM_SDRCLK_0 forms an incomplete loop. The Tdcmino
calculation will be invalid. If the DCM or PLL uses external feedback, please apply the FEEDBACK constraint to
indicate the external board delay. Consult the Constraints Guide for further information on how to apply the FEEDBACK
constraint.
Device speed data version: "PRODUCTION 1.68 2008-07-25".
@@ -23,61 +36,54 @@ Device speed data version: "PRODUCTION 1.68 2008-07-25".
Device Utilization Summary:
Number of BSCANs 1 out of 4 25%
Number of BUFGs 12 out of 32 37%
Number of BUFGs 14 out of 32 43%
Number of DCM_ADVs 4 out of 8 50%
Number of ILOGICs 99 out of 448 22%
Number of External IOBs 226 out of 448 50%
Number of LOCed IOBs 226 out of 226 100%
Number of ILOGICs 93 out of 448 20%
Number of External IOBs 248 out of 448 55%
Number of LOCed IOBs 0 out of 248 0%
Number of OLOGICs 182 out of 448 40%
Number of RAMB16s 51 out of 192 26%
Number of Slices 5907 out of 15360 38%
Number of SLICEMs 543 out of 7680 7%
Number of OLOGICs 192 out of 448 42%
Number of RAMB16s 74 out of 192 38%
Number of Slices 7737 out of 15360 50%
Number of SLICEMs 660 out of 7680 8%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting Router
Phase 1: 47928 unrouted; REAL time: 16 secs
Phase 1: 60308 unrouted; REAL time: 10 secs
Phase 2: 40960 unrouted; REAL time: 17 secs
Phase 2: 51172 unrouted; REAL time: 11 secs
Phase 3: 15655 unrouted; REAL time: 24 secs
Phase 3: 18782 unrouted; REAL time: 17 secs
Phase 4: 15655 unrouted; (245197) REAL time: 24 secs
Phase 4: 18782 unrouted; (446154) REAL time: 17 secs
Phase 5: 16281 unrouted; (4341) REAL time: 27 secs
Phase 5: 19345 unrouted; (932) REAL time: 26 secs
Phase 6: 16339 unrouted; (710) REAL time: 28 secs
Phase 7: 0 unrouted; (9891) REAL time: 53 secs
Phase 6: 0 unrouted; (8225) REAL time: 48 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 8: 0 unrouted; (9891) REAL time: 1 mins 4 secs
Phase 7: 0 unrouted; (96274) REAL time: 2 mins 53 secs
Phase 9: 0 unrouted; (5549) REAL time: 1 mins 14 secs
Phase 8: 0 unrouted; (20056) REAL time: 3 mins 18 secs
Phase 10: 0 unrouted; (5549) REAL time: 1 mins 21 secs
Phase 9: 0 unrouted; (20056) REAL time: 3 mins 32 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 10: 0 unrouted; (20056) REAL time: 3 mins 32 secs
Phase 11: 0 unrouted; (5549) REAL time: 2 mins 23 secs
Phase 11: 0 unrouted; (3379) REAL time: 4 mins 19 secs
Phase 12: 0 unrouted; (1304) REAL time: 2 mins 58 secs
Phase 12: 0 unrouted; (3379) REAL time: 4 mins 25 secs
Phase 13: 0 unrouted; (1304) REAL time: 3 mins 2 secs
Phase 13: 0 unrouted; (3379) REAL time: 4 mins 33 secs
Phase 14: 0 unrouted; (1304) REAL time: 3 mins 7 secs
Total REAL time to Router completion: 3 mins 9 secs
Total CPU time to Router completion: 3 mins 3 secs
Total REAL time to Router completion: 4 mins 33 secs
Total CPU time to Router completion: 4 mins 32 secs
Partition Implementation Status
-------------------------------
@@ -95,28 +101,34 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| cpu_clk |BUFGCTRL_X0Y12| No | 1610 | 0.400 | 4.025 |
| CLK_O |BUFGCTRL_X0Y25| No | 2958 | 0.637 | 3.123 |
+---------------------+--------------+------+------+------------+-------------+
| CLK_O | BUFGCTRL_X0Y2| No | 2256 | 0.541 | 3.930 |
| sys_clk_in_IBUFG |BUFGCTRL_X0Y27| No | 59 | 0.315 | 2.895 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_clk1 | BUFGCTRL_X0Y0| No | 76 | 0.190 | 3.686 |
| cpu_clk |BUFGCTRL_X0Y22| No | 1778 | 0.512 | 2.999 |
+---------------------+--------------+------+------+------------+-------------+
| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.408 | 3.881 |
| sdram_clk270 |BUFGCTRL_X0Y16| No | 36 | 0.165 | 3.041 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y31| No | 227 | 0.492 | 3.933 |
| sdram_clk270var |BUFGCTRL_X0Y20| No | 32 | 0.040 | 3.041 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_rx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y24| No | 240 | 0.398 | 2.916 |
+---------------------+--------------+------+------+------------+-------------+
| vga_clk |BUFGCTRL_X0Y17| No | 184 | 0.448 | 3.000 |
+---------------------+--------------+------+------+------------+-------------+
|sys_ac97_bit_clk_IBU | | | | | |
| F | BUFGCTRL_X0Y8| No | 251 | 0.428 | 3.823 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 55 | 0.205 | 3.675 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270 |BUFGCTRL_X0Y16| No | 68 | 0.158 | 3.932 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 |
| F |BUFGCTRL_X0Y10| No | 245 | 0.401 | 3.040 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.044 | 3.631 |
| /bs_clk1 |BUFGCTRL_X0Y31| No | 73 | 0.292 | 2.948 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_update1 |BUFGCTRL_X0Y30| No | 4 | 0.228 | 2.940 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y28| No | 231 | 0.508 | 2.994 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_tx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y18| No | 218 | 0.526 | 3.014 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
@@ -124,20 +136,7 @@ only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 1304
WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and select
the "Timing Improvement Wizard" link for suggestions to correct each problem.
Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
ensure the best options are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Timing Score: 0
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
@@ -148,31 +147,48 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | -0.293ns| 10.193ns| 9| 1107
HIGH 50% | HOLD | 0.365ns| | 0| 0
Autotimespec constraint for clock net CLK | SETUP | N/A| 9.905ns| N/A| 0
_O | HOLD | 0.396ns| | 0| 0
------------------------------------------------------------------------------------------------------
* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.197ns| 10.294ns| 1| 197
ns HIGH 50% | HOLD | 0.346ns| | 0| 0
Autotimespec constraint for clock net sys | SETUP | N/A| 3.644ns| N/A| 0
_clk_in_IBUFG | HOLD | 0.496ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.170ns| 7.330ns| 0| 0
7.5 ns HIGH 50% | HOLD | 0.513ns| | 0| 0
Autotimespec constraint for clock net cpu | SETUP | N/A| 10.524ns| N/A| 0
_clk | HOLD | 0.337ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.386ns| 7.614ns| 0| 0
s HIGH 50% | HOLD | 0.514ns| | 0| 0
Autotimespec constraint for clock net sys | SETUP | N/A| 6.548ns| N/A| 0
_phy_rx_clk_BUFGP | HOLD | 0.353ns| | 0| 0
------------------------------------------------------------------------------------------------------
NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.650ns| 6.700ns| 0| 0
ns HIGH 50% | HOLD | 0.518ns| | 0| 0
Autotimespec constraint for clock net vga | SETUP | N/A| 8.243ns| N/A| 0
_clk | HOLD | 0.320ns| | 0| 0
------------------------------------------------------------------------------------------------------
TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.716ns| 5.284ns| 0| 0
ns HIGH 50% | HOLD | 0.802ns| | 0| 0
Autotimespec constraint for clock net sys | SETUP | N/A| 5.804ns| N/A| 0
_ac97_bit_clk_IBUF | HOLD | 0.483ns| | 0| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.594ns| N/A| 0
Autotimespec constraint for clock net ins | SETUP | N/A| 1.935ns| N/A| 0
t_rom_wb/inst_rom/bs_clk1 | HOLD | 0.480ns| | 0| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.138ns| N/A| 0
Autotimespec constraint for clock net sdr | SETUP | N/A| 8.766ns| N/A| 0
am_clk0 | HOLD | 0.503ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 4.574ns| N/A| 0
_phy_tx_clk_BUFGP | HOLD | 0.342ns| | 0| 0
------------------------------------------------------------------------------------------------------
2 constraints not met.
Derived Constraint Report
Derived Constraints for CLK_O
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|CLK_O | 10.895ns| 9.905ns| N/A| 0| 0| 1632145| 0|
| inst_clockgen/sdr0_clk0 | 10.895ns| N/A| N/A| 0| 0| 0| 0|
| inst_clockgen/sdr0_clk270 | 10.895ns| N/A| N/A| 0| 0| 0| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
@@ -181,18 +197,17 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 3 mins 18 secs
Total CPU time to PAR completion: 3 mins 9 secs
Total REAL time to PAR completion: 5 mins 50 secs
Total CPU time to PAR completion: 5 mins 49 secs
Peak Memory Usage: 428 MB
Peak Memory Usage: 898 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 10 errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 1
Number of info messages: 2
Writing design to file mips_sys.ncd
projects/mips_sys/ise101/mips_sys/mips_sys.xst
-1
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@@ -17,7 +17,6 @@ run
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-sd { "../../../../lib/CPUs/MIPS/syn/ise101/netgen/synthesis" }
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp
+282 -1169
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File diff suppressed because it is too large Load Diff
projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf → projects/mips_sys/ise101/mips_sys/ucf/mips_sys.ssram.ucf
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projects/mips_sys/ise101/mips_sys/ucf/systest.ucf → projects/mips_sys/ise101/mips_sys/ucf/mips_sys.ucf
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