- fixed
git-svn-id: http://moon:8086/svn/vhdl/trunk@1193 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -1,31 +1,31 @@
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## NOTE: Do not edit this file.
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##
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if {[file exists work]} {vdel -lib work -all}
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vlib work
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vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
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vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
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vcom -explicit -93 "../../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../src/sdram_config.vhd"
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vcom -explicit -93 "../src/sdram_types.vhd"
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vcom -explicit -93 "../src/sdram_cmd.vhd"
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vcom -explicit -93 "../src/sdram_ctrl.vhd"
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vcom -explicit -93 "../src/ddr_clk_virtex4.vhd"
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vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
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vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
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vcom -explicit -93 "../src/sdram_ctrl_frontend_wb.vhd"
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vcom -explicit -93 "../src/mt46v16m16.vhd"
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vcom -explicit -93 "../src/tb_sdram_ctrl_frontend_wb.vhd"
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#restart -force
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vsim -t 1ps -lib work tb_sdram_ctrl_frontend_wb
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do {tb_sdram_ctrl_frontend_wb.wdo}
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view wave
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view structure
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view signals
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run 200us
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## NOTE: Do not edit this file.
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##
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if {[file exists work]} {vdel -lib work -all}
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vlib work
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vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
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vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
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vcom -explicit -93 "../../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../src/sdram_config.vhd"
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vcom -explicit -93 "../src/sdram_types.vhd"
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vcom -explicit -93 "../src/sdram_cmd.vhd"
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vcom -explicit -93 "../src/sdram_ctrl.vhd"
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vcom -explicit -93 "../src/ddr_clk_virtex4.vhd"
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vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
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vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
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vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd"
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vcom -explicit -93 "../src/ctrl_ddr_wb64.vhd"
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vcom -explicit -93 "../src/mt46v16m16.vhd"
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vcom -explicit -93 "../src/tb_ctrl_ddr_wb64.vhd"
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vsim -t 1ps -lib work tb_ctrl_ddr_wb64
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do {tb_ctrl_ddr_wb64.wdo}
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view wave
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view structure
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view signals
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run 200us
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@@ -1,61 +1,53 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o
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add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg
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add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt
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add wave -noupdate -divider DEBUG
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_dout
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_re
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_we
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_full
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_empty
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk_fb
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk0
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_rst0
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add wave -noupdate -divider Part
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n
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add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n
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add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba
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add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm
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add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_col_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_row_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/row_addr_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_bank_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_addr_reg
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add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {199582900 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {199427964 ps} {200030108 ps}
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider J-Bus
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/clk_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/rst_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/cyc_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/stb_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/we_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/sel_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/ack_i
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/mrdy_o
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dat_o
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add wave -noupdate -divider SDRAM
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/sdclk
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/sdclk_fb
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_clk_p
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_clk_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cke
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cs_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_we_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_ras_n
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cas_n
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_ba
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_dm
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_dqs
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/part_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/part_data
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add wave -noupdate -divider Test
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/sd_cmd
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add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/dout_rst
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/sddat
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/sdsel
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add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dout_reg
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add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/dout_cnt
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {189465865 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {0 ps} {210 us}
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@@ -28,10 +28,10 @@ use IEEE.numeric_std.ALL;
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use work.sdram_config.all;
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use work.sdram_types.all;
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entity tb_sdram_ctrl_frontend64_wb is
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entity tb_ctrl_ddr_wb64 is
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end;
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architecture struct of tb_sdram_ctrl_frontend64_wb is
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architecture struct of tb_ctrl_ddr_wb64 is
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constant CLK_PERIOD : time := 10 ns;
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constant SDCLK_PERIOD : time := 7.5 ns;
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@@ -115,13 +115,13 @@ begin
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SEL_O <= "0000" & sdsel;
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-- DDR SDRAM Controller Core
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sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
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uut : entity work.ctrl_ddr_wb64
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GENERIC MAP
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(
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BL => BURST_LEN,
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f_sysclk => 100.000,
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f_sdrclk => 133.333,
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fifo_depth => 4
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BURST_LEN => BURST_LEN,
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F_SYSCLK => 100.000,
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F_SDRCLK => 133.333,
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FIFO_DEPTH => 4
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)
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PORT MAP
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(
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