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- renamed config constants

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- added dedicated config for DDR mt46v16m16

git-svn-id: http://moon:8086/svn/vhdl/trunk@1202 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-24 10:39:18 +00:00
parent a0ad9a9182
commit ddc3b8050e
12 changed files with 91 additions and 91 deletions
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lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb32.fdo
+1 -1
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@@ -11,7 +11,7 @@ vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_config_mt46v16m16.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
vcom -explicit -93 "../src/sdram_ctrl.vhd"
lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo
+1 -1
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@@ -11,7 +11,7 @@ vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../src/sdram_config.vhd"
vcom -explicit -93 "../src/sdram_config_mt46v16m16.vhd"
vcom -explicit -93 "../src/sdram_types.vhd"
vcom -explicit -93 "../src/sdram_cmd.vhd"
vcom -explicit -93 "../src/sdram_ctrl.vhd"
lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd
+3 -3
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@@ -65,9 +65,9 @@ entity ctrl_ddr_wb32 is
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
sd_dm : out unsigned(PART_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(PART_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(PART_DATA_WIDTH-1 downto 0)
);
end ctrl_ddr_wb32;
lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd
+6 -6
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@@ -46,14 +46,14 @@ entity ctrl_ddr_wb64 is
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(SDR_DM_WIDTH-1 downto 0);
SEL_I : in unsigned(BUS_DM_WIDTH-1 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0);
DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0);
DAT_I : in unsigned(BUS_DATA_WIDTH-1 downto 0);
DAT_O : out unsigned(BUS_DATA_WIDTH-1 downto 0);
-- SDRAM signals
sd_clk_p : out STD_LOGIC;
@@ -65,9 +65,9 @@ entity ctrl_ddr_wb64 is
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
sd_dm : out unsigned(PART_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(PART_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(PART_DATA_WIDTH-1 downto 0)
);
end ctrl_ddr_wb64;
lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+21 -21
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@@ -48,11 +48,11 @@ entity sdram_phy is
phy_ctrl : in phy_ctrl_t;
part_clk_p : out STD_LOGIC;
part_clk_n : out STD_LOGIC;
part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0);
part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0);
part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0);
part_dm : out unsigned(PART_DM_WIDTH-1 downto 0);
part_dqs : inout unsigned(PART_DQS_WIDTH-1 downto 0);
part_data : inout unsigned(PART_DATA_WIDTH-1 downto 0);
part_ba : out unsigned(PART_BANK_WIDTH-1 downto 0);
part_addr : out unsigned(PART_ADDR_WIDTH-1 downto 0);
part_cs_n : out STD_LOGIC;
part_we_n : out STD_LOGIC;
part_cas_n : out STD_LOGIC;
@@ -65,13 +65,13 @@ architecture tech of sdram_phy is
signal dqs_drive : std_logic;
signal drive : std_logic;
signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0);
signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0);
signal dqs : unsigned(PART_DQS_WIDTH-1 downto 0);
signal dqs_zen : unsigned(PART_DQS_WIDTH-1 downto 0);
signal dqs_rst : std_logic;
signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0);
signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0);
signal ddr_data_w : unsigned(PART_DATA_WIDTH-1 downto 0);
signal data_r : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal data_reg_r : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal drive270 : unsigned(PART_DATA_WIDTH-1 downto 0);
signal part_ctrl_reg : part_ctrl_t;
signal we_reg : std_logic;
signal read_en : std_logic;
@@ -215,7 +215,7 @@ ODDR_clk_n : ODDR
------------------------------------------------------------------------------------------------------------------------------------------------
-- Data OUT DDR-FFs
gen_ddr_data_out:
for n in 0 to DDR_DATA_WIDTH-1 generate
for n in 0 to PART_DATA_WIDTH-1 generate
begin
ODDR_data : ODDR
generic map
@@ -228,7 +228,7 @@ gen_ddr_data_out:
Q => ddr_data_w(n), -- 1-bit DDR output
C => clk_wr, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => phy_in.wr_data(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge)
D1 => phy_in.wr_data(n + PART_DATA_WIDTH), -- 1-bit data input (positive edge)
D2 => phy_in.wr_data(n), -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
@@ -239,7 +239,7 @@ gen_ddr_data_out:
process (clk_wr)
begin
if rising_edge(clk_wr) then
for n in 0 to DDR_DATA_WIDTH-1 loop
for n in 0 to PART_DATA_WIDTH-1 loop
drive270(n) <= drive;
end loop;
end if;
@@ -247,14 +247,14 @@ gen_ddr_data_out:
-- Output mux
out_mux_data:
for n in 0 to DDR_DATA_WIDTH-1 generate
for n in 0 to PART_DATA_WIDTH-1 generate
part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
end generate;
------------------------------------------------------------------------------------------------------------------------------------------------
-- Data-mask OUT DDR-FFs
gen_ddr_dm_out:
for n in 0 to DDR_DM_WIDTH-1 generate
for n in 0 to PART_DM_WIDTH-1 generate
begin
ODDR_dm : ODDR
generic map
@@ -267,7 +267,7 @@ gen_ddr_dm_out:
Q => part_dm(n), -- 1-bit DDR output
C => clk_wr, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => phy_in.wr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge)
D1 => phy_in.wr_dm(n + PART_DM_WIDTH), -- 1-bit data input (positive edge)
D2 => phy_in.wr_dm(n), -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
@@ -277,7 +277,7 @@ gen_ddr_dm_out:
------------------------------------------------------------------------------------------------------------------------------------------------
-- DQS OUT DDR-FFs
gen_dqs_out:
for n in 0 to DDR_DQS_WIDTH-1 generate
for n in 0 to PART_DQS_WIDTH-1 generate
begin
ODDR_dqs : ODDR
generic map
@@ -317,7 +317,7 @@ gen_dqs_out:
-- Tristate-Buffer fuer dqs
gen_out_mux_dqs:
for n in 0 to DDR_DQS_WIDTH-1 generate
for n in 0 to PART_DQS_WIDTH-1 generate
part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
end generate gen_out_mux_dqs;
@@ -353,7 +353,7 @@ gen_out_mux_dqs:
-- READ DATA Processing
-----------------------------------------------------------------
gen_ddr_data_in:
for n in 0 to DDR_DATA_WIDTH-1 generate
for n in 0 to PART_DATA_WIDTH-1 generate
begin
IDDR_data : IDDR
generic map
@@ -366,7 +366,7 @@ gen_ddr_data_in:
port map
(
Q1 => data_r(n), -- 1-bit output for positive edge of clock
Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock
Q2 => data_r(n + PART_DATA_WIDTH), -- 1-bit output for negative edge of clock
C => clk_rd, -- 1-bit clock input
CE => read_en, -- 1-bit clock enable input
D => part_data(n), -- 1-bit DDR data input
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd → lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt46v16m16.vhd
+10 -5
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@@ -27,11 +27,16 @@ USE IEEE.NUMERIC_STD.ALL;
package sdram_config is
constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
constant DDR_COL_ADDR_WIDTH : positive := 9; --
constant PART_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
constant PART_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
constant PART_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
constant PART_ROW_ADDR_WIDTH : positive := 13; --
constant PART_COL_ADDR_WIDTH : positive := 9; --
constant PART_DQS_WIDTH : positive := PART_DATA_WIDTH / 8; -- Number of data strobe lines
constant PART_DM_WIDTH : positive := PART_DATA_WIDTH / 8; -- Number of Data Mask Lines
constant BUS_DATA_WIDTH : positive := 2*PART_DATA_WIDTH; -- DDR => twice part data width
constant BUS_DM_WIDTH : positive := 2*PART_DM_WIDTH; -- DDR => twice part data width
constant LMR_REG_BASE : natural := 0;
constant LMR_REG_EXTENDED : natural := 1;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
+4 -4
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@@ -70,9 +70,9 @@ entity sdram_ctrl_frontend_wb32 is
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
sd_dm : out unsigned(PART_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(PART_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(PART_DATA_WIDTH-1 downto 0)
);
end sdram_ctrl_frontend_wb32;
@@ -86,7 +86,7 @@ architecture struct of sdram_ctrl_frontend_wb32 is
signal u_busy : std_logic;
signal rdy : std_logic;
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + PART_ROW_ADDR_WIDTH + PART_BANK_WIDTH + PART_COL_ADDR_WIDTH;
signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_re : std_logic;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
+18 -18
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@@ -46,14 +46,14 @@ entity sdram_ctrl_frontend_wb64 is
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(SDR_DM_WIDTH-1 downto 0);
SEL_I : in unsigned(BUS_DM_WIDTH-1 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0);
DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0);
DAT_I : in unsigned(BUS_DATA_WIDTH-1 downto 0);
DAT_O : out unsigned(BUS_DATA_WIDTH-1 downto 0);
-- PHY interface
phy_ctrl : out phy_ctrl_t;
@@ -70,9 +70,9 @@ entity sdram_ctrl_frontend_wb64 is
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
sd_dm : out unsigned(PART_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(PART_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(PART_DATA_WIDTH-1 downto 0)
);
end sdram_ctrl_frontend_wb64;
@@ -86,7 +86,7 @@ architecture struct of sdram_ctrl_frontend_wb64 is
signal u_busy : std_logic;
signal rdy : std_logic;
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + PART_ROW_ADDR_WIDTH + PART_BANK_WIDTH + PART_COL_ADDR_WIDTH;
signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
signal cat_fifo_re : std_logic;
@@ -94,15 +94,15 @@ architecture struct of sdram_ctrl_frontend_wb64 is
signal cat_fifo_full : std_logic;
signal cat_fifo_empty : std_logic;
signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
signal write_fifo_din : unsigned(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto 0);
signal write_fifo_dout : unsigned(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto 0);
signal write_fifo_re : std_logic;
signal write_fifo_we : std_logic;
signal write_fifo_full : std_logic;
signal write_fifo_empty : std_logic;
signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal read_fifo_din : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal read_fifo_dout : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal read_fifo_re : std_logic;
signal read_fifo_we : std_logic;
signal read_fifo_full : std_logic;
@@ -115,13 +115,13 @@ architecture struct of sdram_ctrl_frontend_wb64 is
alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
alias write_fifo_dm_in is write_fifo_din(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
alias write_fifo_data_in is write_fifo_din(SDR_DATA_WIDTH-1 downto 0);
alias write_fifo_dm_out is write_fifo_dout(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
alias write_fifo_data_out is write_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
alias write_fifo_dm_in is write_fifo_din(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH);
alias write_fifo_data_in is write_fifo_din(BUS_DATA_WIDTH-1 downto 0);
alias write_fifo_dm_out is write_fifo_dout(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH);
alias write_fifo_data_out is write_fifo_dout(BUS_DATA_WIDTH-1 downto 0);
alias read_fifo_data_in is read_fifo_din(SDR_DATA_WIDTH-1 downto 0);
alias read_fifo_data_out is read_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
alias read_fifo_data_in is read_fifo_din(BUS_DATA_WIDTH-1 downto 0);
alias read_fifo_data_out is read_fifo_dout(BUS_DATA_WIDTH-1 downto 0);
begin
@@ -236,7 +236,7 @@ begin
u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
u_cmd <= cmd_fifo_out;
u_addr <= addr_fifo_out;
phy_in.wr_dm <= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when phy_out.tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
phy_in.wr_dm <= (write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-5 downto BUS_DATA_WIDTH) & write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH+4)) when phy_out.tag_wr(0) = '1' else write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH);
u_tag_in <= tag_fifo_out;
phy_in.wr_data <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when phy_out.tag_wr(0) = '1' else write_fifo_data_out(63 downto 0);
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+3 -3
View File
@@ -64,9 +64,9 @@ entity sdram_ctrl_top is
sd_we_n : out STD_LOGIC;
sd_addr : out sdr_addr_t;
sd_ba : out sdr_ba_t;
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
sd_dm : out unsigned(PART_DM_WIDTH-1 downto 0);
sd_dqs : inout unsigned(PART_DQS_WIDTH-1 downto 0);
sd_data : inout unsigned(PART_DATA_WIDTH-1 downto 0)
);
end sdram_ctrl_top;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+11 -16
View File
@@ -35,11 +35,6 @@ package sdram_types is
-- Derived constants from sdram_config
constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; --
constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; --
subtype user_cmd_t is unsigned(1 downto 0);
constant UCMD_NOP : user_cmd_t := "00";
constant UCMD_READ : user_cmd_t := "01";
@@ -59,13 +54,13 @@ package sdram_types is
constant SD_SR : sdr_cmd_t := 9;
type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
subtype user_addr_t is unsigned(PART_BANK_WIDTH+PART_ROW_ADDR_WIDTH+PART_COL_ADDR_WIDTH-1 downto 0);
subtype sdr_addr_t is unsigned(PART_ADDR_WIDTH-1 downto 0);
subtype sdr_ba_t is unsigned(PART_BANK_WIDTH-1 downto 0);
subtype mode_word_t is unsigned(PART_ADDR_WIDTH+PART_BANK_WIDTH-1 downto 0);
subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
subtype bank_addr_t is unsigned(PART_BANK_WIDTH-1 downto 0);
subtype row_addr_t is unsigned(PART_ADDR_WIDTH-1 downto 0);
subtype col_addr_t is unsigned(8 downto 0);
type sdr_cmd_lines_t is
@@ -79,8 +74,8 @@ package sdram_types is
type part_ctrl_t is
record
cmd : sdr_cmd_lines_t;
ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
ba : unsigned(PART_BANK_WIDTH-1 downto 0);
addr : unsigned(PART_ADDR_WIDTH-1 downto 0);
cke : std_logic;
end record part_ctrl_t;
@@ -96,13 +91,13 @@ package sdram_types is
type phy_in_t is
record
wr_dm : unsigned(SDR_DM_WIDTH-1 downto 0);
wr_data : unsigned(SDR_DATA_WIDTH-1 downto 0);
wr_dm : unsigned(BUS_DM_WIDTH-1 downto 0);
wr_data : unsigned(BUS_DATA_WIDTH-1 downto 0);
end record phy_in_t;
type phy_out_t is
record
rd_data : unsigned(SDR_DATA_WIDTH-1 downto 0);
rd_data : unsigned(BUS_DATA_WIDTH-1 downto 0);
rd_data_we : STD_LOGIC;
wr_data_re : STD_LOGIC;
tag_rd : user_tag_t;
lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd
+5 -5
View File
@@ -46,11 +46,11 @@ architecture struct of tb_ctrl_ddr_wb32 is
signal part_we_n : std_logic;
signal part_ras_n : std_logic;
signal part_cas_n : std_logic;
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal part_ba : unsigned(PART_BANK_WIDTH-1 downto 0) := (others => '0');
signal part_dm : unsigned(PART_DM_WIDTH-1 downto 0) := (others => '0');
signal part_dqs : unsigned(PART_DQS_WIDTH-1 downto 0) := (others => '0');
signal part_addr : unsigned(PART_ADDR_WIDTH-1 downto 0) := (others => '0');
signal part_data : unsigned(PART_DATA_WIDTH-1 downto 0) := (others => '0');
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
+8 -8
View File
@@ -46,24 +46,24 @@ architecture struct of tb_ctrl_ddr_wb64 is
signal part_we_n : std_logic;
signal part_ras_n : std_logic;
signal part_cas_n : std_logic;
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal part_ba : unsigned(PART_BANK_WIDTH-1 downto 0) := (others => '0');
signal part_dm : unsigned(PART_DM_WIDTH-1 downto 0) := (others => '0');
signal part_dqs : unsigned(PART_DQS_WIDTH-1 downto 0) := (others => '0');
signal part_addr : unsigned(PART_ADDR_WIDTH-1 downto 0) := (others => '0');
signal part_data : unsigned(PART_DATA_WIDTH-1 downto 0) := (others => '0');
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal WE_O : std_logic := '0';
signal SEL_O : unsigned(SDR_DM_WIDTH-1 downto 0);
signal SEL_O : unsigned(BUS_DM_WIDTH-1 downto 0);
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal DAT_O : unsigned(SDR_DATA_WIDTH-1 downto 0);
signal DAT_I : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal DAT_O : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);