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- fixed mips_sys

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1173 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-23 08:56:24 +00:00
parent a08fda26f5
commit 17eb8faee1
1 changed files with 27 additions and 24 deletions
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projects/mips_sys/src/mips_sys.vhd
+27 -24
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@@ -342,13 +342,13 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
signal cpu_clk : std_logic;
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_rst : std_logic;
signal vga_ce : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
@@ -505,7 +505,6 @@ ARCHITECTURE behavior OF mips_sys IS
attribute KEEP : string;
attribute KEEP of vga_clk : signal is "TRUE";
attribute KEEP of sdram_clk0 : signal is "TRUE";
attribute KEEP of cpu_clk : signal is "TRUE";
attribute KEEP of CLK_O : signal is "TRUE";
attribute KEEP of RST_O : signal is "TRUE";
@@ -554,7 +553,7 @@ BEGIN
sys_uart3_tx <= sys_uart3_rx;
sys_vga_clk <= vga_clk;
vga_ce <= not RST_O;
vga_ce <= not vga_rst;
---------------------------------------------------------------
-- Arbiter
@@ -730,7 +729,7 @@ inst_mips_top: mips_top
debug => debug,
eb => eb,
nmi => nmi,
cpu_clk => cpu_clk,
cpu_clk => CLK_O,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
@@ -908,29 +907,34 @@ inst_uart_wb_1 : uart_wb
);
inst_clockgen : entity work.clockgen
inst_clockgen_cpu : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
cpu_clk_out_freq => cpu_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
clk_in_freq => sys_freq_in,
clk_out_freq => cpu_freq
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O,
sys_clk_out => CLK_O,
vga_clk_out => vga_clk,
cpu_clk_out => cpu_clk,
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
rst_in => rst_in,
clk_in => sys_clk_in,
rst_out => RST_O,
clk_out => CLK_O
);
inst_clocken_vga : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
clk_out_freq => vga_freq
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in,
clk_in => sys_clk_in,
rst_out => vga_rst,
clk_out => vga_clk
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
@@ -946,9 +950,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
RST_I => RST_O,
CLK_I => CLK_O,
SDRAM_CLK0_I => sdram_clk0,
SDRAM_CLK270_I => sdram_clk270,
SDRAM_CLK270VAR_I => sdram_clk270var,
SDRAM_CLK_I => sys_clk_in,
SDRAM_CLK_FB_I => sys_sdr_clk_fb,
CYC_I => CYC_I_sdram,
STB_I => STB_O,