- working (SDRAM R1153)

git-svn-id: http://moon:8086/svn/vhdl/trunk@1156 cc03376c-175c-47c8-b038-4cd826a8556b

projects/mips_sys/sim/tb_mips_sys.fdo

@@ -50,11 +50,8 @@ vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
 vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
 
 # UART
-vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
-vcom -explicit  -93 "../../../lib/uart/kcuart_rx.vhd"
-vcom -explicit  -93 "../../../lib/uart/kcuart_tx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_rx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_tx.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_rx_sim.vhd"
+vcom -explicit  -93 "../../../lib/uart/uart_tx_sim.vhd"
 vcom -explicit  -93 "../../../lib/uart/uart_wb.vhd"
 
 # PS2

projects/mips_sys/src/mips_sys_sim.vhd

@@ -712,10 +712,6 @@ inst_usb_port : entity work.async_port_wb
 	);
 
 inst_uart_wb_0 : entity work.uart_wb
-	GENERIC MAP
-	(
-		simulate_tx		=> true
-	)
 	PORT MAP
 	(
 		CLK_I		=> CLK_O,
@@ -736,10 +732,6 @@ inst_uart_wb_0 : entity work.uart_wb
 	);
 
 inst_uart_wb_1 : entity work.uart_wb
-	GENERIC MAP
-	(
-		simulate_tx		=> true
-	)
 	PORT MAP
 	(
 		CLK_I		=> CLK_O,
@@ -760,10 +752,6 @@ inst_uart_wb_1 : entity work.uart_wb
 	);
 
 inst_uart_wb_2 : entity work.uart_wb
-	GENERIC MAP
-	(
-		simulate_tx		=> true
-	)
 	PORT MAP
 	(
 		CLK_I		=> CLK_O,

projects/mips_sys/src/tb_mips_sys.vhd

@@ -148,9 +148,7 @@ uut: entity work.mips_sys
 	GENERIC MAP
 	(
 		sys_freq_in			=> 100.000,
-		cpu_freq			=> 60.000,
-		WITH_TLB			=> WITH_TLB,
-		TRANSLATE_KSEG0_1	=> KSEG_01_TRANSLATED,
+		cpu_freq			=> 100.000,
 		sdram_phaseshift	=> 0,
 		tsvga				=> ts_vga_800_600_72
 	)