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- fixed compile scripts

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1184 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-23 16:04:34 +00:00
parent 81b5e2f867
commit f0c6196710
3 changed files with 32 additions and 19 deletions
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Common/sim/compile_altera.do
+24 -16
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@@ -1,24 +1,32 @@
vlib altera
vcom -93 -work altera ../libsrc/altera/altera_primitives_components.vhd
vcom -93 -work altera ../libsrc/altera/altera_primitives.vhd
vcom -93 -work altera ../libsrc/altera/altera_internal_syn.vhd
vcom -93 -work altera ../libsrc/altera/altera_europa_support_lib.vhd
vcom -93 -work altera ../libsrc/altera/altera_standard_functions.vhd
vcom -93 -work altera ../libsrc/altera/altera_syn_attributes.vhd
vlib build
vlib build/altera
vlib build/altera
vlib cycloneive
vlib build/altera/altera
vmap altera build/altera/altera
vcom -93 -work cycloneive ../libsrc/cycloneive/cycloneive_atoms.vhd
vcom -93 -work cycloneive ../libsrc/cycloneive/cycloneive_components.vhd
vcom -93 -work altera altera/libsrc/altera/altera_primitives_components.vhd
vcom -93 -work altera altera/libsrc/altera/altera_primitives.vhd
vcom -93 -work altera altera/libsrc/altera/altera_internal_syn.vhd
vcom -93 -work altera altera/libsrc/altera/altera_europa_support_lib.vhd
vcom -93 -work altera altera/libsrc/altera/altera_standard_functions.vhd
vcom -93 -work altera altera/libsrc/altera/altera_syn_attributes.vhd
vlib altera_lnsim
vlib build/altera/cycloneive
vmap cycloneive build/altera/cycloneive
vcom -93 -work altera_lnsim ../libsrc/altera_lnsim/altera_lnsim_components.vhd
vcom -93 -work cycloneive altera/libsrc/cycloneive/cycloneive_atoms.vhd
vcom -93 -work cycloneive altera/libsrc/cycloneive/cycloneive_components.vhd
#vmap work altera_lnsim
vlib cyclonev
vlib build/altera/altera_lnsim
vmap altera_lnsim build/altera/altera_lnsim
vcom -93 -work cyclonev ../libsrc/cyclonev/cyclonev_atoms.vhd
vcom -93 -work cyclonev ../libsrc/cyclonev/cyclonev_components.vhd
vcom -93 -work altera_lnsim altera/libsrc/altera_lnsim/altera_lnsim_components.vhd
vlib build/altera/cyclonev
vmap cyclonev build/altera/cyclonev
vcom -93 -work cyclonev altera/libsrc/cyclonev/cyclonev_atoms.vhd
vcom -93 -work cyclonev altera/libsrc/cyclonev/cyclonev_components.vhd
Common/sim/compile_simprim.do
+3 -2
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@@ -1,6 +1,7 @@
vlib simprim
vlib build
vlib build/xilinx
set XILINX $env(XILINX)
vlib build/xilinx/simprim
vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
Common/sim/compile_unisim.do
+5 -1
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@@ -1,4 +1,8 @@
vlib unisim
vlib build
vlib build/xilinx
vlib build/xilinx/unisim
vmap unisim build/xilinx/unisim
vcom -93 -work unisim xilinx/libsrc/unisims/unisim_vpkg.vhd
vcom -93 -work unisim xilinx/libsrc/unisims/unisim_vcomp.vhd