jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

-deleted

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1132 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-20 22:31:46 +00:00
parent 1423984428
commit 38bd9acd52
1 changed files with 0 additions and 218 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/ise101/mips_sys/mips_sys.par
-218
View File
@@ -1,218 +0,0 @@
Release 10.1.03 par K.39 (lin64)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
callisto:: Thu May 21 00:25:05 2015
par -w -intstyle xflow -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
mips_sys.pcf
Constraints file: mips_sys.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment /home/jens/Xilinx/10.1/ISE.
"mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
The STEPPING level for this design is ES.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.68 2008-07-25".
Device Utilization Summary:
Number of BSCANs 1 out of 4 25%
Number of BUFGs 14 out of 32 43%
Number of DCM_ADVs 4 out of 8 50%
Number of ILOGICs 93 out of 448 20%
Number of External IOBs 255 out of 448 56%
Number of LOCed IOBs 255 out of 255 100%
Number of OLOGICs 192 out of 448 42%
Number of RAMB16s 74 out of 192 38%
Number of Slices 7873 out of 15360 51%
Number of SLICEMs 668 out of 7680 8%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal sys_phy_col_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sys_phy_crs_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sys_phy_int_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1: 60615 unrouted; REAL time: 12 secs
Phase 2: 51231 unrouted; REAL time: 12 secs
Phase 3: 18749 unrouted; REAL time: 19 secs
Phase 4: 18749 unrouted; (1226606) REAL time: 19 secs
Phase 5: 19881 unrouted; (22336) REAL time: 23 secs
Phase 6: 19948 unrouted; (3477) REAL time: 24 secs
Phase 7: 0 unrouted; (17354) REAL time: 48 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 8: 0 unrouted; (17354) REAL time: 56 secs
Phase 9: 0 unrouted; (8655) REAL time: 1 mins 13 secs
Phase 10: 0 unrouted; (8655) REAL time: 1 mins 25 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 11: 0 unrouted; (8655) REAL time: 2 mins 40 secs
Phase 12: 0 unrouted; (4028) REAL time: 3 mins 32 secs
Phase 13: 0 unrouted; (4028) REAL time: 3 mins 38 secs
Phase 14: 0 unrouted; (4028) REAL time: 3 mins 45 secs
Total REAL time to Router completion: 3 mins 49 secs
Total CPU time to Router completion: 3 mins 49 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|sys_ac97_bit_clk_IBU | | | | | |
| F | BUFGCTRL_X0Y8| No | 258 | 0.412 | 3.885 |
+---------------------+--------------+------+------+------------+-------------+
| CLK_O | BUFGCTRL_X0Y2| No | 3156 | 0.591 | 3.980 |
+---------------------+--------------+------+------+------------+-------------+
| cpu_clk |BUFGCTRL_X0Y12| No | 1673 | 0.400 | 4.006 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_tx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y31| No | 240 | 0.358 | 3.792 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y25| No | 237 | 0.394 | 3.948 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_rx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y27| No | 277 | 0.256 | 3.849 |
+---------------------+--------------+------+------+------------+-------------+
| vga_clk | BUFGCTRL_X0Y9| No | 176 | 0.431 | 3.881 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_in_IBUFG |BUFGCTRL_X0Y10| No | 70 | 0.324 | 3.796 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_clk1 |BUFGCTRL_X0Y17| No | 76 | 0.264 | 3.683 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270 |BUFGCTRL_X0Y22| No | 67 | 0.158 | 3.932 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_update1 |BUFGCTRL_X0Y19| No | 4 | 0.044 | 3.521 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 4028
WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and select
the "Timing Improvement Wizard" link for suggestions to correct each problem.
Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
ensure the best options are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.584ns| 10.484ns| 20| 3603
ns HIGH 50% | HOLD | 0.336ns| | 0| 0
------------------------------------------------------------------------------------------------------
* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | -0.130ns| 10.030ns| 6| 425
HIGH 50% | HOLD | 0.373ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.062ns| 7.376ns| 0| 0
7.5 ns HIGH 50% | HOLD | 0.508ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.494ns| 7.506ns| 0| 0
s HIGH 50% | HOLD | 0.436ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_phy_tx_clk = PERIOD TIMEGRP "phy_tx_cl | SETUP | 1.474ns| 6.526ns| 0| 0
k" 8 ns HIGH 50% | HOLD | 0.329ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_phy_rx_clk = PERIOD TIMEGRP "phy_rx_cl | SETUP | 1.534ns| 6.466ns| 0| 0
k" 8 ns HIGH 50% | HOLD | 0.323ns| | 0| 0
------------------------------------------------------------------------------------------------------
NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 37.032ns| 8.893ns| 0| 0
ns HIGH 50% | HOLD | 0.521ns| | 0| 0
------------------------------------------------------------------------------------------------------
TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 75.276ns| 4.724ns| 0| 0
ns HIGH 50% | HOLD | 0.811ns| | 0| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.485ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 7.217ns| N/A| 0
------------------------------------------------------------------------------------------------------
2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 3 mins 55 secs
Total CPU time to PAR completion: 3 mins 55 secs
Peak Memory Usage: 870 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 26 errors found.
Number of error messages: 0
Number of warning messages: 6
Number of info messages: 1
Writing design to file mips_sys.ncd
PAR done!