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- added RPD_BOARD_SIM

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- cleaned up
- reduced SDRAM CLock to 100 MHz

git-svn-id: http://moon:8086/svn/vhdl/trunk@1219 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-24 17:36:21 +00:00
parent 32f0d8c23a
commit bfa747571f
3 changed files with 60 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd
+4 -2
View File
@@ -35,7 +35,8 @@ entity ctrl_ddr_wb64 is
BURST_LEN : natural := 2;
F_SYSCLK : real := 100.0;
F_SDRCLK : real := 100.0;
FIFO_DEPTH : integer := 4
FIFO_DEPTH : integer := 4;
TPD_BOARD_SIM : time := 0 ns
);
Port
(
@@ -120,7 +121,8 @@ begin
inst_sdram_phy : entity work.sdram_phy
Generic map
(
F_SDRCLK => F_SDRCLK
F_SDRCLK => F_SDRCLK,
TPD_BOARD_SIM => TPD_BOARD_SIM
)
Port map
(
lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+50 -56
View File
@@ -34,7 +34,8 @@ use UNISIM.vcomponents.all;
entity sdram_phy is
Generic
(
F_SDRCLK : real := 100.0
F_SDRCLK : real := 100.0;
TPD_BOARD_SIM : time := 0 ns
);
Port
(
@@ -68,7 +69,7 @@ architecture tech of sdram_phy is
signal dqs : unsigned(PART_DQS_WIDTH-1 downto 0);
signal dqs_zen : unsigned(PART_DQS_WIDTH-1 downto 0);
signal dqs_rst : std_logic;
signal ddr_data_w : unsigned(PART_DATA_WIDTH-1 downto 0);
signal wr_data : unsigned(PART_DATA_WIDTH-1 downto 0);
signal data_r : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal data_reg_r : unsigned(BUS_DATA_WIDTH-1 downto 0);
signal drive270 : unsigned(PART_DATA_WIDTH-1 downto 0);
@@ -77,10 +78,12 @@ architecture tech of sdram_phy is
signal read_en : std_logic;
signal clk0 : std_logic;
signal clk0_s : std_logic;
signal clk0_temp : std_logic;
signal rst0 : std_logic;
signal clk_rd : std_logic;
signal clk_wr : std_logic;
signal clk0_rd : std_logic;
signal clk270_rd : std_logic;
signal clk270 : std_logic;
signal locked : std_logic;
signal error : std_logic;
@@ -93,10 +96,10 @@ architecture tech of sdram_phy is
begin
clk0_out <= clk0_s;
clk0 <= clk0_s after 10 ps; -- fix delta delay
rst0_out <= rst0;
clk0_out <= clk0_temp;
clk0 <= clk0_temp after 10 ps; -- fix delta delay
rst0_out <= rst0;
------------------------------------------------------------------------------------------------------------------------------------------------
inst_sdram_clk : entity work.sdram_clk
GENERIC MAP
@@ -111,10 +114,10 @@ inst_sdram_clk : entity work.sdram_clk
rst => rst, -- external async reset, low active
clk_in => clk, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_fb, -- feedback clock
clk0_0_out => clk0_s, -- System clock #0, dcm#0 output 0°
clk0_270_out => clk_wr, -- System clock #0, dcm#0 output 270°
clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out => clk_rd, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
clk0_0_out => clk0_temp, -- System clock #0, dcm#0 output 0°
clk0_270_out => clk270, -- System clock #0, dcm#0 output 270°
clk1_0_out => clk0_rd, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out => clk270_rd, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => locked, -- DCM locked status
error_out => error
);
@@ -225,8 +228,8 @@ gen_ddr_data_out:
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => ddr_data_w(n), -- 1-bit DDR output
C => clk_wr, -- 1-bit clock input
Q => wr_data(n), -- 1-bit DDR output
C => clk270, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => phy_in.wr_data(n + PART_DATA_WIDTH), -- 1-bit data input (positive edge)
D2 => phy_in.wr_data(n), -- 1-bit data input (negative edge)
@@ -236,9 +239,9 @@ gen_ddr_data_out:
end generate gen_ddr_data_out;
-- Sample tristate on clock90
process (clk_wr)
process (clk270)
begin
if rising_edge(clk_wr) then
if rising_edge(clk270) then
for n in 0 to PART_DATA_WIDTH-1 loop
drive270(n) <= drive;
end loop;
@@ -248,11 +251,11 @@ gen_ddr_data_out:
-- Output mux
out_mux_data:
for n in 0 to PART_DATA_WIDTH-1 generate
part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
part_data(n) <= wr_data(n) when drive270(n) = '1' else 'Z';
end generate;
------------------------------------------------------------------------------------------------------------------------------------------------
-- Data-mask OUT DDR-FFs
-- Part DM OUT DDR-FFs
gen_ddr_dm_out:
for n in 0 to PART_DM_WIDTH-1 generate
begin
@@ -265,7 +268,7 @@ gen_ddr_dm_out:
)
port map (
Q => part_dm(n), -- 1-bit DDR output
C => clk_wr, -- 1-bit clock input
C => clk270, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => phy_in.wr_dm(n + PART_DM_WIDTH), -- 1-bit data input (positive edge)
D2 => phy_in.wr_dm(n), -- 1-bit data input (negative edge)
@@ -297,30 +300,34 @@ gen_dqs_out:
);
end generate gen_dqs_out;
-- Tristate-Control fuer dqs
process (clk0) is
variable zctrl : boolean;
begin
if rising_edge(clk0) then
if dqs_drive = '1' then
zctrl := false;
else
zctrl := true;
end if;
if zctrl then
dqs_zen <= (others => '1');
else
dqs_zen <= (others => '0');
end if;
end if;
end process;
-- Tristate-Buffer fuer dqs
-- Part DQS Z-Control
proc_dqs_zen:
process (clk0) is
begin
if rising_edge(clk0) then
dqs_zen <= (others => not dqs_drive);
end if;
end process;
gen_out_mux_dqs:
for n in 0 to PART_DQS_WIDTH-1 generate
part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
end generate gen_out_mux_dqs;
-- Part Control signals
process (clk0) is
begin
if falling_edge(clk0) then
part_ras_n <= part_ctrl_reg.cmd.ras_n;
part_cas_n <= part_ctrl_reg.cmd.cas_n;
part_we_n <= part_ctrl_reg.cmd.we_n;
part_cs_n <= part_ctrl_reg.cmd.cs_n;
part_ba <= part_ctrl_reg.ba;
part_addr <= part_ctrl_reg.addr;
part_cke <= part_ctrl_reg.cke;
end if;
end process;
------------------------------------------------------------------------------------------------------------------------------------------------
process (clk0) is
begin
@@ -336,19 +343,6 @@ gen_out_mux_dqs:
end if;
end process;
process (clk0) is
begin
if falling_edge(clk0) then
part_ras_n <= part_ctrl_reg.cmd.ras_n;
part_cas_n <= part_ctrl_reg.cmd.cas_n;
part_we_n <= part_ctrl_reg.cmd.we_n;
part_cs_n <= part_ctrl_reg.cmd.cs_n;
part_ba <= part_ctrl_reg.ba;
part_addr <= part_ctrl_reg.addr;
part_cke <= part_ctrl_reg.cke;
end if;
end process;
-----------------------------------------------------------------
-- READ DATA Processing
-----------------------------------------------------------------
@@ -367,7 +361,7 @@ gen_ddr_data_in:
(
Q1 => data_r(n), -- 1-bit output for positive edge of clock
Q2 => data_r(n + PART_DATA_WIDTH), -- 1-bit output for negative edge of clock
C => clk_rd, -- 1-bit clock input
C => clk270_rd, -- 1-bit clock input
CE => read_en, -- 1-bit clock enable input
D => part_data(n), -- 1-bit DDR data input
R => '0', -- 1-bit reset
@@ -377,9 +371,9 @@ gen_ddr_data_in:
data_sample_stage:
process (clk0)
process (clk0_rd)
begin
if falling_edge(clk0) then
if falling_edge(clk0_rd) then
data_reg_r <= data_r;
end if;
end process;
lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
+6 -4
View File
@@ -34,7 +34,8 @@ end;
architecture struct of tb_ctrl_ddr_wb64 is
constant CLK_PERIOD : time := 10 ns;
constant SDCLK_PERIOD : time := 7.5 ns;
constant TPD_BOARD_SIM : time := 1 ns;
constant SDCLK_PERIOD : time := 10 ns;
constant BURST_LEN : natural := 2;
signal sdclk : std_logic := '1';
@@ -109,7 +110,7 @@ begin
end if;
end process;
sdclk_fb <= part_clk_p after 1 ns;
sdclk_fb <= part_clk_p;
DAT_O <= X"DEADBEEF" & sddat;
SEL_O <= "0000" & sdsel;
@@ -120,8 +121,9 @@ begin
(
BURST_LEN => BURST_LEN,
F_SYSCLK => 100.000,
F_SDRCLK => 133.333,
FIFO_DEPTH => 4
F_SDRCLK => 100.000,
FIFO_DEPTH => 4,
TPD_BOARD_SIM => TPD_BOARD_SIM
)
PORT MAP
(