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- add generics for rounding mode and saturation mode

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1322 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-10-24 14:39:32 +00:00
parent e7e1b9118e
commit 6226f79562
1 changed files with 7 additions and 5 deletions
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lib/filter/src/fir_stage_sys.vhd
+7 -5
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@@ -42,7 +42,9 @@ Generic
nbits_in_frac : integer := 12;
nbits_out : integer := 12;
nbits_out_frac : integer := 12;
pipe_latency : integer := 2
pipe_latency : integer := 2;
round_style : fixed_round_style_type := fixed_truncate;
overflow_style : fixed_overflow_style_type := fixed_wrap
);
Port
(
@@ -67,7 +69,7 @@ signal yin : in_t;
signal prod : out_t;
signal x_reg : out_t;
signal y_reg : out_t;
signal vld : unsigned(1 downto 0);
signal vld : unsigned(pipe_latency-1 downto 0);
------------------------------------------------------------
begin
@@ -86,9 +88,9 @@ begin
vld <= (others => '0');
elsif ce = '1' then
vld <= vld(vld'left-1 downto 0) & '1';
prod <= resize(x_in * h_in, prod, fixed_wrap, fixed_truncate);
x_reg <= resize(x_in, x_reg, fixed_wrap, fixed_truncate);
y_reg <= resize(yin + prod, y_reg, fixed_wrap, fixed_truncate);
prod <= resize(x_in * h_in, prod, overflow_style, round_style);
x_reg <= resize(x_in, x_reg, overflow_style, round_style);
y_reg <= resize(yin + prod, y_reg, overflow_style, round_style);
x_out <= x_reg;
end if;
end if;