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git-svn-id: http://moon:8086/svn/vhdl/trunk@1304 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2015-10-23 04:43:48 +00:00
parent f862b2a5ae
commit c229af0f71
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Common/sim/compile_ieee_proposed.do
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#
# Compile script for Modeltech
#
if {![file exists build]} {mkdir build}
cd build
if {![file exists modelsim]} {mkdir modelsim}
cd modelsim
if {[file exists modelsim]} {vdel -lib modelsim -all}
vlib ieee_proposed
vcom -work ieee_proposed ../../ieee_proposed/modelsim/standard_additions_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/standard_textio_additions_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/env_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/std_logic_1164_additions.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/numeric_std_additions.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/numeric_std_unsigned_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/math_utility_pkg_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/fixed_pkg_c.vhdl
vcom -work ieee_proposed ../../ieee_proposed/modelsim/float_pkg_c.vhdl
Common/sim/ieee_proposed/modelsim/README
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This is the "ieee_proposed" library. This is a compatability library,
which is designed to provide all of the functionality of the VHDL-200X-FT
packages in VHDL-93. The "_c" after the package name is used to denote
that this is a 1993 compliant version of this package. Otherwise, the
name of the file and the name of the package are the same.
Please compile the following files into a library named "ieee_proposed":
standard_additions_c.vhdl
env_c.vhdl
standard_textio_additions_c.vhdl
std_logic_1164_additions.vhdl
numeric_std_additions.vhdl
numeric_std_unsigned_c.vhdl
fixed_pkg_c.vhdl
float_pkg_c.vhdl
New/Updated functions
A) standard_additions -- Additions to the package "std.standard"
Use model:
use ieee_proposed.standard_additions.all;
Dependancies: None.
Notes: The functions "rising_edge" and "falling_edge" are defined in
this package. If you use "numeric_bit" they are ALSO defined in that
package, causing a conflict. The VHDL-200X-FT version of numeric_bit
has these functions commented out, as well as the "sll", "srl", "ror"
and "rol" functions which are implicit.
New types defined in this package:
REAL_VECTOR
TIME_VECTOR
INTEGER_VECTOR
BOOLEAN_VECTOR
New constants defined in this package:
SIM_RESOLUTION : TIME - returns the simulator's resolution (1 ns default)
1) "maximum" and "minimum" are defined for all default datatypes
2) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
These functions reduce a bit_vector to a single bit. Example:
or_reduce ("0101") = '1'. In VHDL-2006 syntax these will be "or".
3) "vector" and "bit" operations are defined. These will perform a
boolean operation of a vector. Example:
"1" xor "1010" = "0101";
5) /??/ function is defined for "bit" ("??" operator is release)
if (/??/('1')) then -- will return a "true".
6) rising_edge and falling_edge functions are defined (see Notes).
7) to_string function - Converts any of the base types into a string.
Example:
assert (bv = "101") report "result was " & to_string(bv) severity note;
8) to_hstring and to_ostring function (bit_vector to hex or octal string)
B) standard_textio_additions - Additions to the package "std.textio"
Use model:
use ieee_proposed.standard_textio_additions.all;
Dependencies: std.textio, ieee_proposed.standard_additions
1) tee - Echos the string to BOTH the file and the screen
2) SREAD and SWRITE - String read and write routines (so you no longer
need to do write (L, string'("ABCEDFG"));
3) HREAD and HWRITE (Hex read and write) for bit_vector
4) OREAD and OWRITE (octal read and write) for bit_vector
5) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
bit_vector
6) justify - Justify a string left or right with a width. Example:
justify ("ABCD", left, 6); will result in "ABCD "
C) std_logic_1164_additions - Additions to the package "ieee.std_logic_1164"
Usage model:
use ieee.std_logic_1164.all;
-- use ieee.std_logic_textio.all; -- Comment out, included in "_additions".
use ieee_proposed.std_logic_1164_additions.all;
Dependencies: ieee.std_logic_1164
Note: The contents of the "std_logic_textio" package have now been
included in the "std_logic_1164" package, and an EMPTY "std_logic_textio"
package is provided in the new release.
1) Short had aliases:
a) to_bv - calls "to_BitVector"
b) to_slv - calls "to_StdLogicVector"
c) to_suv - calls "to_stdULogicVector"
2) Long hand aliases:
a) to_bit_vector - calls "to_BitVector"
b) to_std_logic_vector - calls "to_StdLogicVector"
c) to_std_ulogic_vector - calls "to_StdULogicVector"
3) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
These functions reduce a std_logic_vector (or ulogic) to a single bit.
In vhdl-2006 these will be unary "or", example "or "11011" = '1'"
4) "vector" and "std_ulogic" operations are defined. These will perform a
boolean operation of a vector. Example:
"1" xor "1010" = "0101";
5) "std_ulogic" and "boolean" operations are defined. Thus:
if '1' and true then -- returns a "true".
6) "\??\" function is defined for "std_ulogic" ("??" operator is release)
if (bool('1')) then -- will return a "true".
7) READ and WRITE procedures for "std_logic_vector", "std_ulogic_vector"
and "std_ulogic" are defined.
8) HREAD and HWRITE (Hex read and write) for std_logic_vector
and std_ulogic_vector. These are more "forgiving" than the ones
originally from "std_logic_textio"
9) OREAD and OWRITE (octal read and write) for std_logic_vector
and std_ulogic_vector. These are more "forgiving" than the ones
originally from "std_logic_textio"
10) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
std_logic_vector and std_ulogic_vector.
11) to_string function - Converts a "std_ulogic", "std_logic_vector" or
"std_ulogic_vector" types into a string.
Example:
assert (slv = "101") report "result was " & to_string(slv) severity note;
12) to_hstring and to_ostring function (std_(u)logic_vector to hex or octal
string)
D) numeric_std_additions - additions the the package "ieee.numeric_std"
Usage Model:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.numeric_std_additions.all;
Dependencies: ieee.std_logic_1164, ieee.numeric_std
1) SIGNED or UNSIGNED + std_ulogic operators
2) SIGNED or UNSIGNED - std_ulogic operators
3) type UNRESOLVED_UNSIGNED (aliased to U_UNSIGNED) is an unresolved
verion of UNSIGNED. It is aliased to "UNSIGNED" for compatability.
4) type UNRESOLVED_SIGNED (aliased to U_SIGNED) is an unresolved
verion of SIGNED. It is aliased to "SIGNED" for compatability.
5) \?=\, \?/=\ - similar to "std_match", but return std_ulogic values.
\?<\, \?<=\, \?>\, \?>=\ - compare functions which retrun std_ulogic.
(these will be "?="... operators in the release)
7) To_X01, To_X01Z, To_U01X, Is_X - same as std_logic_1164 functions,
but overloaded for SIGNED and UNSIGNED.
8) "sla" and "sra" - Mathmetically correct versions of these functions.
9) minimum and maximum - smaller or larger of two SIGNED or UNSIGNED values.
10) find_rightmost and find_leftmost - finds the first bit in a string.
Example:
find_leftmost (c12, '1'); -- returns the Log2 of "c12".
returns -1 if not found.
11) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
These functions reduce a SIGNED or an UNSIGNED to a single bit.
(will overload the "or" and "and", ... operators in the release)
12) SIGNED or UNSIGNED and "std_ulogic" operations are defined.
These will perform a boolean operation of a vector. Example:
"1" xor "1010" = "0101";
13) READ and WRITE procedures for "SIGNED", and "UNSIGNED" are defined.
14) HREAD and HWRITE (Hex read and write) for SIGNED and UNSIGNED.
These are more "forgiving" than the ones
originally from "std_logic_textio"
15) OREAD and OWRITE (octal read and write) for "SIGNED" and "UNSIGNED.
These are more "forgiving" than the ones
originally from "std_logic_textio"
16) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
SIGNED and UNSIGNED.
17) to_string function - Converts a "SIGNED" or "UNSIGNED" types into a
string. Example:
assert (UNS = "101") report "result was " & to_string(UNS) severity note;
18) to_hstring and to_ostring function (SIGNED or UNSIGNED to hex or octal
string)
E) numeric_std_unsigned - Simular to the "std_logic_unsigned" packages, but
with all of the functionality of the "numeric_std" package.
use model:
use ieee.std_logic_1164.all;
use ieee_proposed.numeric_std_unsigned.all;
dependencies: ieee.numeric_std, ieee_proposed.numeric_std_additions
F) For fixed point package:
use model:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
See fixed point package documentation
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf
G) For floating point package:
use model:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
See floating point package documentation
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Float_ug.pdf
Common/sim/ieee_proposed/modelsim/compile.mti
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#
# Compile script for Modeltech
#
vlib ieee_proposed.lib
vmap ieee_proposedx ieee_proposed.lib
vcom -work ieee_proposed standard_additions_c.vhdl
vcom -work ieee_proposed standard_textio_additions_c.vhdl
vcom -work ieee_proposed env_c.vhdl
vcom -work ieee_proposed std_logic_1164_additions.vhdl
vcom -work ieee_proposed numeric_std_additions.vhdl
vcom -work ieee_proposed numeric_std_unsigned_c.vhdl
vcom -work ieee_proposed math_utility_pkg_c.vhdl
vcom -work ieee_proposed fixed_pkg_c.vhdl
vcom -work ieee_proposed float_pkg_c.vhdl
Common/sim/ieee_proposed/modelsim/env_c.vhdl
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package ENV is
procedure STOP (STATUS : INTEGER);
procedure FINISH (STATUS : INTEGER);
function RESOLUTION_LIMIT return DELAY_LENGTH;
end package ENV;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body ENV is
procedure STOP (STATUS : INTEGER) is
begin
report "Procedure STOP called with status: " & INTEGER'image(STATUS)
severity failure;
end procedure STOP;
procedure FINISH (STATUS : INTEGER) is
begin
report "Procedure FINISH called with status: " & INTEGER'image(STATUS)
severity failure;
end procedure FINISH;
constant BASE_TIME_ARRAY : time_vector :=
(
1 fs, 10 fs, 100 fs,
1 ps, 10 ps, 100 ps,
1 ns, 10 ns, 100 ns,
1 us, 10 us, 100 us,
1 ms, 10 ms, 100 ms,
1 sec, 10 sec, 100 sec,
1 min, 10 min, 100 min,
1 hr, 10 hr, 100 hr
) ;
function RESOLUTION_LIMIT return DELAY_LENGTH is
begin
for i in BASE_TIME_ARRAY'range loop
if BASE_TIME_ARRAY(i) > 0 hr then
return BASE_TIME_ARRAY(i);
end if;
end loop;
report "STANDATD.RESOLUTION_LIMIT: Simulator resolution not less than 100 hr"
severity failure;
return 1 ns;
end function RESOLUTION_LIMIT;
end package body ENV;
Common/sim/ieee_proposed/modelsim/fixed_pkg_c.vhdl
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Common/sim/ieee_proposed/modelsim/float_pkg_c.vhdl
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Common/sim/ieee_proposed/modelsim/math_utility_pkg_c.vhdl
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-- --------------------------------------------------------------------
-- "math_utility_pkg" package contains types used by the both the fixed
-- and floating point packages.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.math_utility.all;
-- use ieee_proposed.fixed_pkg.all;
-- use ieee_proposed.float_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 1.1 $
-- Date : $Date: 2007-04-04 14:00:18-04 $
-- --------------------------------------------------------------------
package math_utility_pkg is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package math_utility_pkg;
Common/sim/ieee_proposed/modelsim/numeric_std_additions.vhdl
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Common/sim/ieee_proposed/modelsim/numeric_std_unsigned_c.vhdl
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Common/sim/ieee_proposed/modelsim/standard_additions_c.vhdl
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Common/sim/ieee_proposed/modelsim/standard_textio_additions_c.vhdl
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------------------------------------------------------------------------------
-- "standard_textio_additions" package contains the additions to the built in
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007-03-13 14:25:58-04 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007-03-13 14:25:58-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
------------------------------------------------------------------------------
use std.textio.all;
package standard_textio_additions is
-- procedure DEALLOCATE (P : inout LINE);
procedure FLUSH (file F : TEXT);
function MINIMUM (L, R : SIDE) return SIDE;
function MAXIMUM (L, R : SIDE) return SIDE;
function TO_STRING (VALUE : SIDE) return STRING;
function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
procedure TEE (file F : TEXT; L : inout LINE);
procedure WRITE (L : inout LINE; VALUE : in REAL;
FORMAT : in STRING);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package standard_textio_additions;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body standard_textio_additions is
-- pragma synthesis_off
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- Writes L to a file without modifying the contents of the line
procedure TEE (file F : TEXT; L : inout LINE) is
begin
write (OUTPUT, L.all & LF);
writeline(F, L);
end procedure TEE;
procedure FLUSH (file F: TEXT) is -- Implicit
begin
file_close (F);
end procedure FLUSH;
-- Read and Write procedure for strings
procedure SREAD (L : inout LINE;
VALUE : out STRING;
STRLEN : out natural) is
variable ok : BOOLEAN;
variable c : CHARACTER;
-- Result is padded with space characters
variable result : STRING (1 to VALUE'length) := (others => ' ');
begin
VALUE := result;
loop -- skip white space
read(L, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
STRLEN := 0;
return;
end if;
result (1) := c;
STRLEN := 1;
for i in 2 to VALUE'length loop
read(L, c, ok);
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
exit;
else
result (i) := c;
end if;
STRLEN := i;
end loop;
VALUE := result;
end procedure SREAD;
-- Hex Read and Write procedures for bit_vector.
-- Procedure only visible internally.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out BIT_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when others =>
assert not ISSUE_ERROR report
"TEXTIO.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)." severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.HREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.HREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.HREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
-- Procedure only visible internally.
procedure Char2TriBits (C : CHARACTER;
RESULT : out BIT_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when others =>
assert not ISSUE_ERROR
report
"TEXTIO.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
-- Read and Write procedures for Octal values
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.OREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.OREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.OREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
-- read and write for vector versions
-- These versions produce "value1, value2, value3 ...."
procedure read (L : inout LINE;
VALUE : out boolean_vector;
GOOD : out BOOLEAN) is
variable dummy : CHARACTER;
variable igood : BOOLEAN := true;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
GOOD => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
good := false;
return;
end if;
end loop;
good := true;
end procedure read;
procedure read (L : inout LINE;
VALUE : out boolean_vector) is
variable dummy : CHARACTER;
variable igood : BOOLEAN;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
good => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
& "Read error ecounted during vector read" severity error;
return;
end if;
end loop;
end procedure read;
procedure write (L : inout LINE;
VALUE : in boolean_vector;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
for i in VALUE'range loop
write (L => L,
VALUE => VALUE(i),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
if (i /= value'right) then
swrite (L, ", ");
end if;
end loop;
end procedure write;
procedure WRITE (L: inout LINE; VALUE: in REAL;
FORMAT: in STRING) is
begin
swrite ( L => L,
VALUE => to_string (VALUE, FORMAT));
end procedure WRITE;
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_string (
VALUE : SIDE) return STRING is
begin
return SIDE'image(VALUE);
end function to_string;
-- pragma synthesis_on
-- Will be implicit
function minimum (L, R : SIDE) return SIDE is
begin
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : SIDE) return SIDE is
begin
if L > R then return L;
else return R;
end if;
end function maximum;
end package body standard_textio_additions;
Common/sim/ieee_proposed/modelsim/std_logic_1164_additions.vhdl
+1886
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